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f7c70325 PB |
1 | /* |
2 | * Cortex-A9MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2009 CodeSourcery. | |
b12080cd PM |
5 | * Copyright (c) 2011 Linaro Limited. |
6 | * Written by Paul Brook, Peter Maydell. | |
f7c70325 | 7 | * |
8e31bf38 | 8 | * This code is licensed under the GPL. |
f7c70325 PB |
9 | */ |
10 | ||
17b7f2db | 11 | #include "qemu/osdep.h" |
da34e65c | 12 | #include "qapi/error.h" |
0b8fa32f | 13 | #include "qemu/module.h" |
de4c2dcf | 14 | #include "hw/cpu/a9mpcore.h" |
64552b6b | 15 | #include "hw/irq.h" |
a27bd6c7 | 16 | #include "hw/qdev-properties.h" |
2e5b09fd | 17 | #include "hw/core/cpu.h" |
b12080cd | 18 | |
ddd76165 PM |
19 | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
20 | { | |
845769fc | 21 | A9MPPrivState *s = (A9MPPrivState *)opaque; |
9b5f952b AF |
22 | |
23 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); | |
ddd76165 PM |
24 | } |
25 | ||
753bc6e9 AF |
26 | static void a9mp_priv_initfn(Object *obj) |
27 | { | |
28 | A9MPPrivState *s = A9MPCORE_PRIV(obj); | |
29 | ||
30 | memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); | |
31 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); | |
9b5f952b | 32 | |
2ba486e7 | 33 | sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU); |
eb110bd8 | 34 | |
2ba486e7 | 35 | sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC); |
4c25f365 | 36 | |
2ba486e7 TH |
37 | sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer), |
38 | TYPE_A9_GTIMER); | |
57e72f2a | 39 | |
2ba486e7 TH |
40 | sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer), |
41 | TYPE_ARM_MPTIMER); | |
eb110bd8 | 42 | |
2ba486e7 TH |
43 | sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), |
44 | TYPE_ARM_MPTIMER); | |
753bc6e9 AF |
45 | } |
46 | ||
837cf101 | 47 | static void a9mp_priv_realize(DeviceState *dev, Error **errp) |
b12080cd | 48 | { |
837cf101 | 49 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
5126fec7 | 50 | A9MPPrivState *s = A9MPCORE_PRIV(dev); |
57e72f2a FL |
51 | DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; |
52 | SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, | |
53 | *wdtbusdev; | |
837cf101 | 54 | Error *err = NULL; |
b12080cd | 55 | int i; |
4182bbb1 PM |
56 | bool has_el3; |
57 | Object *cpuobj; | |
b12080cd | 58 | |
4c25f365 PC |
59 | scudev = DEVICE(&s->scu); |
60 | qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); | |
61 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | |
62 | if (err != NULL) { | |
63 | error_propagate(errp, err); | |
64 | return; | |
65 | } | |
66 | scubusdev = SYS_BUS_DEVICE(&s->scu); | |
67 | ||
9b5f952b AF |
68 | gicdev = DEVICE(&s->gic); |
69 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); | |
70 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | |
4182bbb1 PM |
71 | |
72 | /* Make the GIC's TZ support match the CPUs. We assume that | |
73 | * either all the CPUs have TZ, or none do. | |
74 | */ | |
75 | cpuobj = OBJECT(qemu_get_cpu(0)); | |
6533a1fc | 76 | has_el3 = object_property_find(cpuobj, "has_el3", NULL) && |
4182bbb1 PM |
77 | object_property_get_bool(cpuobj, "has_el3", &error_abort); |
78 | qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); | |
79 | ||
837cf101 AF |
80 | object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); |
81 | if (err != NULL) { | |
82 | error_propagate(errp, err); | |
83 | return; | |
84 | } | |
9b5f952b | 85 | gicbusdev = SYS_BUS_DEVICE(&s->gic); |
ddd76165 PM |
86 | |
87 | /* Pass through outbound IRQ lines from the GIC */ | |
837cf101 | 88 | sysbus_pass_irq(sbd, gicbusdev); |
ddd76165 PM |
89 | |
90 | /* Pass through inbound GPIO lines to the GIC */ | |
837cf101 | 91 | qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); |
b12080cd | 92 | |
57e72f2a FL |
93 | gtimerdev = DEVICE(&s->gtimer); |
94 | qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); | |
95 | object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); | |
96 | if (err != NULL) { | |
97 | error_propagate(errp, err); | |
98 | return; | |
99 | } | |
100 | gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); | |
101 | ||
eb110bd8 AF |
102 | mptimerdev = DEVICE(&s->mptimer); |
103 | qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
104 | object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); |
105 | if (err != NULL) { | |
106 | error_propagate(errp, err); | |
107 | return; | |
108 | } | |
d3053e6b | 109 | mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); |
cde4577f | 110 | |
eb110bd8 AF |
111 | wdtdev = DEVICE(&s->wdt); |
112 | qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
113 | object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); |
114 | if (err != NULL) { | |
115 | error_propagate(errp, err); | |
116 | return; | |
117 | } | |
eb110bd8 | 118 | wdtbusdev = SYS_BUS_DEVICE(&s->wdt); |
b12080cd PM |
119 | |
120 | /* Memory map (addresses are offsets from PERIPHBASE): | |
121 | * 0x0000-0x00ff -- Snoop Control Unit | |
122 | * 0x0100-0x01ff -- GIC CPU interface | |
123 | * 0x0200-0x02ff -- Global Timer | |
124 | * 0x0300-0x05ff -- nothing | |
125 | * 0x0600-0x06ff -- private timers and watchdogs | |
126 | * 0x0700-0x0fff -- nothing | |
127 | * 0x1000-0x1fff -- GIC Distributor | |
b12080cd | 128 | */ |
353575f0 PC |
129 | memory_region_add_subregion(&s->container, 0, |
130 | sysbus_mmio_get_region(scubusdev, 0)); | |
b12080cd | 131 | /* GIC CPU interface */ |
ddd76165 PM |
132 | memory_region_add_subregion(&s->container, 0x100, |
133 | sysbus_mmio_get_region(gicbusdev, 1)); | |
57e72f2a FL |
134 | memory_region_add_subregion(&s->container, 0x200, |
135 | sysbus_mmio_get_region(gtimerbusdev, 0)); | |
b12080cd PM |
136 | /* Note that the A9 exposes only the "timer/watchdog for this core" |
137 | * memory region, not the "timer/watchdog for core X" ones 11MPcore has. | |
138 | */ | |
139 | memory_region_add_subregion(&s->container, 0x600, | |
d3053e6b | 140 | sysbus_mmio_get_region(mptimerbusdev, 0)); |
b12080cd | 141 | memory_region_add_subregion(&s->container, 0x620, |
cde4577f | 142 | sysbus_mmio_get_region(wdtbusdev, 0)); |
ddd76165 PM |
143 | memory_region_add_subregion(&s->container, 0x1000, |
144 | sysbus_mmio_get_region(gicbusdev, 0)); | |
b12080cd | 145 | |
ddd76165 | 146 | /* Wire up the interrupt from each watchdog and timer. |
57e72f2a FL |
147 | * For each core the global timer is PPI 27, the private |
148 | * timer is PPI 29 and the watchdog PPI 30. | |
ddd76165 PM |
149 | */ |
150 | for (i = 0; i < s->num_cpu; i++) { | |
151 | int ppibase = (s->num_irq - 32) + i * 32; | |
57e72f2a FL |
152 | sysbus_connect_irq(gtimerbusdev, i, |
153 | qdev_get_gpio_in(gicdev, ppibase + 27)); | |
d3053e6b | 154 | sysbus_connect_irq(mptimerbusdev, i, |
9b5f952b | 155 | qdev_get_gpio_in(gicdev, ppibase + 29)); |
cde4577f | 156 | sysbus_connect_irq(wdtbusdev, i, |
9b5f952b | 157 | qdev_get_gpio_in(gicdev, ppibase + 30)); |
b12080cd | 158 | } |
b12080cd PM |
159 | } |
160 | ||
39bffca2 | 161 | static Property a9mp_priv_properties[] = { |
845769fc | 162 | DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
39bffca2 AL |
163 | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
164 | * IRQ lines (with another 32 internal). We default to 64+32, which | |
165 | * is the number provided by the Cortex-A9MP test chip in the | |
166 | * Realview PBX-A9 and Versatile Express A9 development boards. | |
167 | * Other boards may differ and should set this property appropriately. | |
168 | */ | |
845769fc | 169 | DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
39bffca2 AL |
170 | DEFINE_PROP_END_OF_LIST(), |
171 | }; | |
172 | ||
999e12bb AL |
173 | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
174 | { | |
39bffca2 | 175 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 176 | |
837cf101 | 177 | dc->realize = a9mp_priv_realize; |
39bffca2 | 178 | dc->props = a9mp_priv_properties; |
999e12bb AL |
179 | } |
180 | ||
8c43a6f0 | 181 | static const TypeInfo a9mp_priv_info = { |
5126fec7 | 182 | .name = TYPE_A9MPCORE_PRIV, |
39bffca2 | 183 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 184 | .instance_size = sizeof(A9MPPrivState), |
753bc6e9 | 185 | .instance_init = a9mp_priv_initfn, |
39bffca2 | 186 | .class_init = a9mp_priv_class_init, |
f7c70325 PB |
187 | }; |
188 | ||
83f7d43a | 189 | static void a9mp_register_types(void) |
f7c70325 | 190 | { |
39bffca2 | 191 | type_register_static(&a9mp_priv_info); |
f7c70325 PB |
192 | } |
193 | ||
83f7d43a | 194 | type_init(a9mp_register_types) |