[thirdparty/qemu.git] / hw / cris / axis_dev88.c

/*
 * QEMU model for the AXIS devboard 88.
 *
 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/cris/etraxfs.h"
#include "hw/loader.h"
#include "elf.h"
#include "boot.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"

#define D(x)
#define DNAND(x)

struct nand_state_t
{
    DeviceState *nand;
    MemoryRegion iomem;
    unsigned int rdy:1;
    unsigned int ale:1;
    unsigned int cle:1;
    unsigned int ce:1;
};

static struct nand_state_t nand_state;
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
    struct nand_state_t *s = opaque;
    uint32_t r;
    int rdy;

    r = nand_getio(s->nand);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;

    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
    return r;
}

static void
nand_write(void *opaque, hwaddr addr, uint64_t value,
           unsigned size)
{
    struct nand_state_t *s = opaque;
    int rdy;

    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
    nand_setio(s->nand, value);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;
}

static const MemoryRegionOps nand_ops = {
    .read = nand_read,
    .write = nand_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct tempsensor_t
{
    unsigned int shiftreg;
    unsigned int count;
    enum {
        ST_OUT, ST_IN, ST_Z
    } state;

    uint16_t regs[3];
};

static void tempsensor_clkedge(struct tempsensor_t *s,
                               unsigned int clk, unsigned int data_in)
{
    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
             clk, s->state, s->shiftreg));
    if (s->count == 0) {
        s->count = 16;
        s->state = ST_OUT;
    }
    switch (s->state) {
        case ST_OUT:
            /* Output reg is clocked at negedge.  */
            if (!clk) {
                s->count--;
                s->shiftreg <<= 1;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_IN;
                    s->count = 16;
                }
            }
            break;
        case ST_Z:
            if (clk) {
                s->count--;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_OUT;
                    s->count = 16;
                }
            }
            break;
        case ST_IN:
            /* Indata is sampled at posedge.  */
            if (clk) {
                s->count--;
                s->shiftreg <<= 1;
                s->shiftreg |= data_in & 1;
                if (s->count == 0) {
                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
                    s->regs[0] = s->shiftreg;
                    s->state = ST_OUT;
                    s->count = 16;

                    if ((s->regs[0] & 0xff) == 0) {
                        /* 25 degrees celsius.  */
                        s->shiftreg = 0x0b9f;
                    } else if ((s->regs[0] & 0xff) == 0xff) {
                        /* Sensor ID, 0x8100 LM70.  */
                        s->shiftreg = 0x8100;
                    } else
                        printf("Invalid tempsens state %x\n", s->regs[0]);
                }
            }
            break;
    }
}


#define RW_PA_DOUT    0x00
#define R_PA_DIN      0x01
#define RW_PA_OE      0x02
#define RW_PD_DOUT    0x10
#define R_PD_DIN      0x11
#define RW_PD_OE      0x12

static struct gpio_state_t
{
    MemoryRegion iomem;
    struct nand_state_t *nand;
    struct tempsensor_t tempsensor;
    uint32_t regs[0x5c / 4];
} gpio_state;

static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
    struct gpio_state_t *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_PA_DIN:
            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];

            /* Encode pins from the nand.  */
            r |= s->nand->rdy << 7;
            break;
        case R_PD_DIN:
            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];

            /* Encode temp sensor pins.  */
            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
            break;

        default:
            r = s->regs[addr];
            break;
    }
    return r;
    D(printf("%s %x=%x\n", __func__, addr, r));
}

static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
                       unsigned size)
{
    struct gpio_state_t *s = opaque;
    D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));

    addr >>= 2;
    switch (addr)
    {
        case RW_PA_DOUT:
            /* Decode nand pins.  */
            s->nand->ale = !!(value & (1 << 6));
            s->nand->cle = !!(value & (1 << 5));
            s->nand->ce  = !!(value & (1 << 4));

            s->regs[addr] = value;
            break;

        case RW_PD_DOUT:
            /* Temp sensor clk.  */
            if ((s->regs[addr] ^ value) & 2)
                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
                                   !!(value & 16));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = value;
            break;
    }
}

static const MemoryRegionOps gpio_ops = {
    .read = gpio_read,
    .write = gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

#define INTMEM_SIZE (128 * KiB)

static struct cris_load_info li;

static
void axisdev88_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    CRISCPU *cpu;
    CPUCRISState *env;
    DeviceState *dev;
    SysBusDevice *s;
    DriveInfo *nand;
    qemu_irq irq[30], nmi[2];
    void *etraxfs_dmac;
    struct etraxfs_dma_client *dma_eth;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);

    /* init CPUs */
    cpu = CRIS_CPU(cpu_create(machine->cpu_type));
    env = &cpu->env;

    /* allocate RAM */
    memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);

    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
       internal memory.  */
    memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
                           INTMEM_SIZE, &error_fatal);
    memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);

      /* Attach a NAND flash to CS1.  */
    nand = drive_get(IF_MTD, 0, 0);
    nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
                                NAND_MFR_STMICRO, 0x39);
    memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
                          "nand", 0x05000000);
    memory_region_add_subregion(address_space_mem, 0x10000000,
                                &nand_state.iomem);

    gpio_state.nand = &nand_state;
    memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
                          "gpio", 0x5c);
    memory_region_add_subregion(address_space_mem, 0x3001a000,
                                &gpio_state.iomem);


    dev = qdev_create(NULL, "etraxfs,pic");
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0x3001c000);
    sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
    sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
    for (i = 0; i < 30; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }
    nmi[0] = qdev_get_gpio_in(dev, 30);
    nmi[1] = qdev_get_gpio_in(dev, 31);

    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
    for (i = 0; i < 10; i++) {
        /* On ETRAX, odd numbered channels are inputs.  */
        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
    }

    /* Add the two ethernet blocks.  */
    dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
    etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
    }

    /* The DMA Connector block is missing, hardwire things for now.  */
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
    etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
        etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
    }

    /* 2 timers.  */
    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);

    for (i = 0; i < 4; i++) {
        etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hd(i));
    }

    if (kernel_filename) {
        li.image_filename = kernel_filename;
        li.cmdline = kernel_cmdline;
        cris_load_image(cpu, &li);
    } else if (!qtest_enabled()) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }
}

static void axisdev88_machine_init(MachineClass *mc)
{
    mc->desc = "AXIS devboard 88";
    mc->init = axisdev88_init;
    mc->is_default = 1;
    mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32");
}

DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)
Commit	Line	Data
10c144e2 EI	1	/*
	2	* QEMU model for the AXIS devboard 88.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
4b816985	24
23b0d7df	25	#include "qemu/osdep.h"
a4ed5a35	26	#include "qemu/units.h"
da34e65c	27	#include "qapi/error.h"
4771d756	28	#include "cpu.h"
83c9f4ca	29	#include "hw/sysbus.h"
1422e32d	30	#include "net/net.h"
0d09e41a	31	#include "hw/block/flash.h"
83c9f4ca	32	#include "hw/boards.h"
0d09e41a	33	#include "hw/cris/etraxfs.h"
83c9f4ca	34	#include "hw/loader.h"
ca20cf32	35	#include "elf.h"
47b43a1f	36	#include "boot.h"
022c62cb	37	#include "exec/address-spaces.h"
5efe843a	38	#include "sysemu/qtest.h"
8290de92	39	#include "sysemu/sysemu.h"
10c144e2 EI	40
	41	#define D(x)
	42	#define DNAND(x)
	43
	44	struct nand_state_t
	45	{
d4220389	46	DeviceState *nand;
838335ec	47	MemoryRegion iomem;
10c144e2 EI	48	unsigned int rdy:1;
	49	unsigned int ale:1;
	50	unsigned int cle:1;
	51	unsigned int ce:1;
	52	};
	53
	54	static struct nand_state_t nand_state;
a8170e5e	55	static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	56	{
	57	struct nand_state_t *s = opaque;
	58	uint32_t r;
	59	int rdy;
	60
	61	r = nand_getio(s->nand);
	62	nand_getpins(s->nand, &rdy);
	63	s->rdy = rdy;
	64
	65	DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
	66	return r;
	67	}
	68
	69	static void
a8170e5e	70	nand_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	71	unsigned size)
10c144e2 EI	72	{
	73	struct nand_state_t *s = opaque;
	74	int rdy;
	75
838335ec	76	DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	77	nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
	78	nand_setio(s->nand, value);
	79	nand_getpins(s->nand, &rdy);
	80	s->rdy = rdy;
	81	}
	82
838335ec AK	83	static const MemoryRegionOps nand_ops = {
	84	.read = nand_read,
	85	.write = nand_write,
	86	.endianness = DEVICE_NATIVE_ENDIAN,
10c144e2 EI	87	};
10c144e2 EI	88
4a1e6bea EI	89	struct tempsensor_t
	90	{
	91	unsigned int shiftreg;
	92	unsigned int count;
	93	enum {
	94	ST_OUT, ST_IN, ST_Z
	95	} state;
	96
	97	uint16_t regs[3];
	98	};
	99
	100	static void tempsensor_clkedge(struct tempsensor_t *s,
	101	unsigned int clk, unsigned int data_in)
	102	{
	103	D(printf("%s clk=%d state=%d sr=%x\n", __func__,
	104	clk, s->state, s->shiftreg));
	105	if (s->count == 0) {
	106	s->count = 16;
	107	s->state = ST_OUT;
	108	}
	109	switch (s->state) {
	110	case ST_OUT:
	111	/* Output reg is clocked at negedge. */
	112	if (!clk) {
	113	s->count--;
	114	s->shiftreg <<= 1;
	115	if (s->count == 0) {
	116	s->shiftreg = 0;
	117	s->state = ST_IN;
	118	s->count = 16;
	119	}
	120	}
	121	break;
	122	case ST_Z:
	123	if (clk) {
	124	s->count--;
	125	if (s->count == 0) {
	126	s->shiftreg = 0;
	127	s->state = ST_OUT;
	128	s->count = 16;
	129	}
	130	}
	131	break;
	132	case ST_IN:
	133	/* Indata is sampled at posedge. */
	134	if (clk) {
	135	s->count--;
	136	s->shiftreg <<= 1;
	137	s->shiftreg \|= data_in & 1;
	138	if (s->count == 0) {
	139	D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
	140	s->regs[0] = s->shiftreg;
	141	s->state = ST_OUT;
	142	s->count = 16;
	143
	144	if ((s->regs[0] & 0xff) == 0) {
67cc32eb	145	/* 25 degrees celsius. */
4a1e6bea EI	146	s->shiftreg = 0x0b9f;
	147	} else if ((s->regs[0] & 0xff) == 0xff) {
	148	/* Sensor ID, 0x8100 LM70. */
	149	s->shiftreg = 0x8100;
	150	} else
	151	printf("Invalid tempsens state %x\n", s->regs[0]);
	152	}
	153	}
	154	break;
	155	}
	156	}
	157
	158
	159	#define RW_PA_DOUT 0x00
	160	#define R_PA_DIN 0x01
	161	#define RW_PA_OE 0x02
	162	#define RW_PD_DOUT 0x10
	163	#define R_PD_DIN 0x11
	164	#define RW_PD_OE 0x12
	165
	166	static struct gpio_state_t
10c144e2	167	{
838335ec	168	MemoryRegion iomem;
10c144e2	169	struct nand_state_t *nand;
4a1e6bea	170	struct tempsensor_t tempsensor;
10c144e2 EI	171	uint32_t regs[0x5c / 4];
	172	} gpio_state;
	173
a8170e5e	174	static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	175	{
	176	struct gpio_state_t *s = opaque;
	177	uint32_t r = 0;
	178
	179	addr >>= 2;
	180	switch (addr)
	181	{
	182	case R_PA_DIN:
	183	r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
	184
	185	/* Encode pins from the nand. */
	186	r \|= s->nand->rdy << 7;
	187	break;
4a1e6bea EI	188	case R_PD_DIN:
	189	r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
	190
	191	/* Encode temp sensor pins. */
	192	r \|= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
	193	break;
	194
10c144e2 EI	195	default:
	196	r = s->regs[addr];
	197	break;
	198	}
	199	return r;
	200	D(printf("%s %x=%x\n", __func__, addr, r));
	201	}
	202
a8170e5e	203	static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	204	unsigned size)
10c144e2 EI	205	{
10c144e2 EI	206	struct gpio_state_t *s = opaque;
838335ec	207	D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	208
	209	addr >>= 2;
	210	switch (addr)
	211	{
	212	case RW_PA_DOUT:
	213	/* Decode nand pins. */
	214	s->nand->ale = !!(value & (1 << 6));
	215	s->nand->cle = !!(value & (1 << 5));
	216	s->nand->ce = !!(value & (1 << 4));
	217
	218	s->regs[addr] = value;
	219	break;
4a1e6bea EI	220
	221	case RW_PD_DOUT:
	222	/* Temp sensor clk. */
	223	if ((s->regs[addr] ^ value) & 2)
	224	tempsensor_clkedge(&s->tempsensor, !!(value & 2),
	225	!!(value & 16));
	226	s->regs[addr] = value;
	227	break;
	228
10c144e2 EI	229	default:
	230	s->regs[addr] = value;
	231	break;
	232	}
	233	}
	234
838335ec AK	235	static const MemoryRegionOps gpio_ops = {
	236	.read = gpio_read,
	237	.write = gpio_write,
	238	.endianness = DEVICE_NATIVE_ENDIAN,
	239	.valid = {
	240	.min_access_size = 4,
	241	.max_access_size = 4,
	242	},
10c144e2 EI	243	};
10c144e2 EI	244
a4ed5a35	245	#define INTMEM_SIZE (128 * KiB)
10c144e2	246
77d4f95e	247	static struct cris_load_info li;
409dbce5	248
10c144e2	249	static
3ef96221	250	void axisdev88_init(MachineState *machine)
10c144e2	251	{
3ef96221	252	ram_addr_t ram_size = machine->ram_size;
3ef96221 MA	253	const char *kernel_filename = machine->kernel_filename;
3ef96221 MA	254	const char *kernel_cmdline = machine->kernel_cmdline;
ddeb9ae5	255	CRISCPU *cpu;
fc9bb176	256	CPUCRISState *env;
fd6dc90b EI	257	DeviceState *dev;
fd6dc90b EI	258	SysBusDevice *s;
522f253c	259	DriveInfo *nand;
4a6da670	260	qemu_irq irq[30], nmi[2];
10c144e2	261	void *etraxfs_dmac;
1da005b3	262	struct etraxfs_dma_client *dma_eth;
10c144e2	263	int i;
b0e3d5ac AK	264	MemoryRegion *address_space_mem = get_system_memory();
	265	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
	266	MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
10c144e2 EI	267
10c144e2 EI	268	/* init CPUs */
5eab493d	269	cpu = CRIS_CPU(cpu_create(machine->cpu_type));
ddeb9ae5	270	env = &cpu->env;
10c144e2 EI	271
10c144e2 EI	272	/* allocate RAM */
c0c85841 DM	273	memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
c0c85841 DM	274	ram_size);
b0e3d5ac	275	memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
10c144e2 EI	276
	277	/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
	278	internal memory. */
98a99ce0 PM	279	memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
98a99ce0 PM	280	INTMEM_SIZE, &error_fatal);
b0e3d5ac	281	memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
10c144e2 EI	282
10c144e2 EI	283	/* Attach a NAND flash to CS1. */
522f253c	284	nand = drive_get(IF_MTD, 0, 0);
4be74634	285	nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
522f253c	286	NAND_MFR_STMICRO, 0x39);
2c9b15ca	287	memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
838335ec AK	288	"nand", 0x05000000);
	289	memory_region_add_subregion(address_space_mem, 0x10000000,
	290	&nand_state.iomem);
10c144e2 EI	291
10c144e2 EI	292	gpio_state.nand = &nand_state;
2c9b15ca	293	memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
838335ec AK	294	"gpio", 0x5c);
	295	memory_region_add_subregion(address_space_mem, 0x3001a000,
	296	&gpio_state.iomem);
10c144e2 EI	297
10c144e2 EI	298
fd6dc90b EI	299	dev = qdev_create(NULL, "etraxfs,pic");
fd6dc90b EI	300	/* FIXME: Is there a proper way to signal vectors to the CPU core? */
ee6847d1	301	qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
e23a1b33	302	qdev_init_nofail(dev);
1356b98d	303	s = SYS_BUS_DEVICE(dev);
fd6dc90b	304	sysbus_mmio_map(s, 0, 0x3001c000);
4a6da670 EI	305	sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
4a6da670 EI	306	sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
fd6dc90b	307	for (i = 0; i < 30; i++) {
067a3ddc	308	irq[i] = qdev_get_gpio_in(dev, i);
fd6dc90b	309	}
067a3ddc PB	310	nmi[0] = qdev_get_gpio_in(dev, 30);
067a3ddc PB	311	nmi[1] = qdev_get_gpio_in(dev, 31);
73cfd29f	312
ba494313	313	etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
10c144e2 EI	314	for (i = 0; i < 10; i++) {
10c144e2 EI	315	/* On ETRAX, odd numbered channels are inputs. */
73cfd29f	316	etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
10c144e2 EI	317	}
	318
	319	/* Add the two ethernet blocks. */
7267c094	320	dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
1da005b3 EI	321	etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
	322	if (nb_nics > 1) {
	323	etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
	324	}
10c144e2 EI	325
10c144e2 EI	326	/* The DMA Connector block is missing, hardwire things for now. */
1da005b3 EI	327	etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
	328	etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
	329	if (nb_nics > 1) {
	330	etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
	331	etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
10c144e2 EI	332	}
	333
	334	/* 2 timers. */
3b1fd90e EI	335	sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
3b1fd90e EI	336	sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
10c144e2 EI	337
10c144e2 EI	338	for (i = 0; i < 4; i++) {
9bca0edb	339	etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hd(i));
10c144e2 EI	340	}
10c144e2 EI	341
5efe843a AF	342	if (kernel_filename) {
	343	li.image_filename = kernel_filename;
	344	li.cmdline = kernel_cmdline;
	345	cris_load_image(cpu, &li);
	346	} else if (!qtest_enabled()) {
77d4f95e EI	347	fprintf(stderr, "Kernel image must be specified\n");
77d4f95e EI	348	exit(1);
10c144e2	349	}
10c144e2 EI	350	}
10c144e2 EI	351
e264d29d	352	static void axisdev88_machine_init(MachineClass *mc)
f80f9ec9	353	{
e264d29d EH	354	mc->desc = "AXIS devboard 88";
	355	mc->init = axisdev88_init;
	356	mc->is_default = 1;
5eab493d	357	mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32");
f80f9ec9 AL	358	}
f80f9ec9 AL	359
e264d29d	360	DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)