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d34cab9f TS |
1 | /* |
2 | * QEMU VMware-SVGA "chipset". | |
3 | * | |
4 | * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
47df5154 | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
83c9f4ca PB |
26 | #include "hw/hw.h" |
27 | #include "hw/loader.h" | |
ac86048b | 28 | #include "trace.h" |
28ecbaee | 29 | #include "ui/console.h" |
2f487a3d | 30 | #include "ui/vnc.h" |
83c9f4ca | 31 | #include "hw/pci/pci.h" |
d34cab9f | 32 | |
ca0508df | 33 | #undef VERBOSE |
d34cab9f TS |
34 | #define HW_RECT_ACCEL |
35 | #define HW_FILL_ACCEL | |
36 | #define HW_MOUSE_ACCEL | |
37 | ||
47b43a1f | 38 | #include "vga_int.h" |
5b9575c8 BZ |
39 | |
40 | /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ | |
d34cab9f TS |
41 | |
42 | struct vmsvga_state_s { | |
4e12cd94 | 43 | VGACommonState vga; |
d34cab9f | 44 | |
d34cab9f | 45 | int invalidated; |
d34cab9f TS |
46 | int enable; |
47 | int config; | |
48 | struct { | |
49 | int id; | |
50 | int x; | |
51 | int y; | |
52 | int on; | |
53 | } cursor; | |
54 | ||
d34cab9f TS |
55 | int index; |
56 | int scratch_size; | |
57 | uint32_t *scratch; | |
58 | int new_width; | |
59 | int new_height; | |
eb2f9b02 | 60 | int new_depth; |
d34cab9f TS |
61 | uint32_t guest; |
62 | uint32_t svgaid; | |
d34cab9f | 63 | int syncing; |
d34cab9f | 64 | |
b1950430 | 65 | MemoryRegion fifo_ram; |
f351d050 DA |
66 | uint8_t *fifo_ptr; |
67 | unsigned int fifo_size; | |
f351d050 | 68 | |
d34cab9f TS |
69 | union { |
70 | uint32_t *fifo; | |
541dc0d4 | 71 | struct QEMU_PACKED { |
d34cab9f TS |
72 | uint32_t min; |
73 | uint32_t max; | |
74 | uint32_t next_cmd; | |
75 | uint32_t stop; | |
76 | /* Add registers here when adding capabilities. */ | |
77 | uint32_t fifo[0]; | |
78 | } *cmd; | |
79 | }; | |
80 | ||
0d793797 | 81 | #define REDRAW_FIFO_LEN 512 |
d34cab9f TS |
82 | struct vmsvga_rect_s { |
83 | int x, y, w, h; | |
84 | } redraw_fifo[REDRAW_FIFO_LEN]; | |
85 | int redraw_fifo_first, redraw_fifo_last; | |
86 | }; | |
87 | ||
39d45987 PC |
88 | #define TYPE_VMWARE_SVGA "vmware-svga" |
89 | ||
90 | #define VMWARE_SVGA(obj) \ | |
91 | OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA) | |
92 | ||
d34cab9f | 93 | struct pci_vmsvga_state_s { |
af21c740 AF |
94 | /*< private >*/ |
95 | PCIDevice parent_obj; | |
96 | /*< public >*/ | |
97 | ||
d34cab9f | 98 | struct vmsvga_state_s chip; |
b1950430 | 99 | MemoryRegion io_bar; |
d34cab9f TS |
100 | }; |
101 | ||
0d793797 BZ |
102 | #define SVGA_MAGIC 0x900000UL |
103 | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) | |
104 | #define SVGA_ID_0 SVGA_MAKE_ID(0) | |
105 | #define SVGA_ID_1 SVGA_MAKE_ID(1) | |
106 | #define SVGA_ID_2 SVGA_MAKE_ID(2) | |
d34cab9f | 107 | |
0d793797 BZ |
108 | #define SVGA_LEGACY_BASE_PORT 0x4560 |
109 | #define SVGA_INDEX_PORT 0x0 | |
110 | #define SVGA_VALUE_PORT 0x1 | |
111 | #define SVGA_BIOS_PORT 0x2 | |
d34cab9f TS |
112 | |
113 | #define SVGA_VERSION_2 | |
114 | ||
115 | #ifdef SVGA_VERSION_2 | |
0d793797 BZ |
116 | # define SVGA_ID SVGA_ID_2 |
117 | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT | |
118 | # define SVGA_IO_MUL 1 | |
119 | # define SVGA_FIFO_SIZE 0x10000 | |
120 | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 | |
d34cab9f | 121 | #else |
0d793797 BZ |
122 | # define SVGA_ID SVGA_ID_1 |
123 | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT | |
124 | # define SVGA_IO_MUL 4 | |
125 | # define SVGA_FIFO_SIZE 0x10000 | |
126 | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA | |
d34cab9f TS |
127 | #endif |
128 | ||
129 | enum { | |
130 | /* ID 0, 1 and 2 registers */ | |
131 | SVGA_REG_ID = 0, | |
132 | SVGA_REG_ENABLE = 1, | |
133 | SVGA_REG_WIDTH = 2, | |
134 | SVGA_REG_HEIGHT = 3, | |
135 | SVGA_REG_MAX_WIDTH = 4, | |
136 | SVGA_REG_MAX_HEIGHT = 5, | |
137 | SVGA_REG_DEPTH = 6, | |
0d793797 | 138 | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
d34cab9f TS |
139 | SVGA_REG_PSEUDOCOLOR = 8, |
140 | SVGA_REG_RED_MASK = 9, | |
141 | SVGA_REG_GREEN_MASK = 10, | |
142 | SVGA_REG_BLUE_MASK = 11, | |
143 | SVGA_REG_BYTES_PER_LINE = 12, | |
144 | SVGA_REG_FB_START = 13, | |
145 | SVGA_REG_FB_OFFSET = 14, | |
146 | SVGA_REG_VRAM_SIZE = 15, | |
147 | SVGA_REG_FB_SIZE = 16, | |
148 | ||
149 | /* ID 1 and 2 registers */ | |
150 | SVGA_REG_CAPABILITIES = 17, | |
0d793797 | 151 | SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
d34cab9f | 152 | SVGA_REG_MEM_SIZE = 19, |
0d793797 BZ |
153 | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
154 | SVGA_REG_SYNC = 21, /* Write to force synchronization */ | |
155 | SVGA_REG_BUSY = 22, /* Read to check if sync is done */ | |
156 | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ | |
157 | SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ | |
158 | SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ | |
159 | SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ | |
160 | SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ | |
161 | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ | |
162 | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ | |
163 | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ | |
164 | SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ | |
165 | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ | |
166 | ||
167 | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ | |
d34cab9f TS |
168 | SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, |
169 | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, | |
170 | }; | |
171 | ||
0d793797 BZ |
172 | #define SVGA_CAP_NONE 0 |
173 | #define SVGA_CAP_RECT_FILL (1 << 0) | |
174 | #define SVGA_CAP_RECT_COPY (1 << 1) | |
175 | #define SVGA_CAP_RECT_PAT_FILL (1 << 2) | |
176 | #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) | |
177 | #define SVGA_CAP_RASTER_OP (1 << 4) | |
178 | #define SVGA_CAP_CURSOR (1 << 5) | |
179 | #define SVGA_CAP_CURSOR_BYPASS (1 << 6) | |
180 | #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) | |
181 | #define SVGA_CAP_8BIT_EMULATION (1 << 8) | |
182 | #define SVGA_CAP_ALPHA_CURSOR (1 << 9) | |
183 | #define SVGA_CAP_GLYPH (1 << 10) | |
184 | #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) | |
185 | #define SVGA_CAP_OFFSCREEN_1 (1 << 12) | |
186 | #define SVGA_CAP_ALPHA_BLEND (1 << 13) | |
187 | #define SVGA_CAP_3D (1 << 14) | |
188 | #define SVGA_CAP_EXTENDED_FIFO (1 << 15) | |
189 | #define SVGA_CAP_MULTIMON (1 << 16) | |
190 | #define SVGA_CAP_PITCHLOCK (1 << 17) | |
d34cab9f TS |
191 | |
192 | /* | |
193 | * FIFO offsets (seen as an array of 32-bit words) | |
194 | */ | |
195 | enum { | |
196 | /* | |
197 | * The original defined FIFO offsets | |
198 | */ | |
199 | SVGA_FIFO_MIN = 0, | |
0d793797 | 200 | SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ |
d34cab9f TS |
201 | SVGA_FIFO_NEXT_CMD, |
202 | SVGA_FIFO_STOP, | |
203 | ||
204 | /* | |
205 | * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO | |
206 | */ | |
207 | SVGA_FIFO_CAPABILITIES = 4, | |
208 | SVGA_FIFO_FLAGS, | |
209 | SVGA_FIFO_FENCE, | |
210 | SVGA_FIFO_3D_HWVERSION, | |
211 | SVGA_FIFO_PITCHLOCK, | |
212 | }; | |
213 | ||
0d793797 BZ |
214 | #define SVGA_FIFO_CAP_NONE 0 |
215 | #define SVGA_FIFO_CAP_FENCE (1 << 0) | |
216 | #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) | |
217 | #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) | |
d34cab9f | 218 | |
0d793797 BZ |
219 | #define SVGA_FIFO_FLAG_NONE 0 |
220 | #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) | |
d34cab9f TS |
221 | |
222 | /* These values can probably be changed arbitrarily. */ | |
0d793797 | 223 | #define SVGA_SCRATCH_SIZE 0x8000 |
2f487a3d | 224 | #define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT) |
0d793797 | 225 | #define SVGA_MAX_HEIGHT 1770 |
d34cab9f TS |
226 | |
227 | #ifdef VERBOSE | |
0d793797 | 228 | # define GUEST_OS_BASE 0x5001 |
d34cab9f | 229 | static const char *vmsvga_guest_id[] = { |
f707cfba AZ |
230 | [0x00] = "Dos", |
231 | [0x01] = "Windows 3.1", | |
232 | [0x02] = "Windows 95", | |
233 | [0x03] = "Windows 98", | |
234 | [0x04] = "Windows ME", | |
235 | [0x05] = "Windows NT", | |
236 | [0x06] = "Windows 2000", | |
237 | [0x07] = "Linux", | |
238 | [0x08] = "OS/2", | |
511d2b14 | 239 | [0x09] = "an unknown OS", |
f707cfba AZ |
240 | [0x0a] = "BSD", |
241 | [0x0b] = "Whistler", | |
511d2b14 BS |
242 | [0x0c] = "an unknown OS", |
243 | [0x0d] = "an unknown OS", | |
244 | [0x0e] = "an unknown OS", | |
245 | [0x0f] = "an unknown OS", | |
246 | [0x10] = "an unknown OS", | |
247 | [0x11] = "an unknown OS", | |
248 | [0x12] = "an unknown OS", | |
249 | [0x13] = "an unknown OS", | |
250 | [0x14] = "an unknown OS", | |
f707cfba | 251 | [0x15] = "Windows 2003", |
d34cab9f TS |
252 | }; |
253 | #endif | |
254 | ||
255 | enum { | |
256 | SVGA_CMD_INVALID_CMD = 0, | |
257 | SVGA_CMD_UPDATE = 1, | |
258 | SVGA_CMD_RECT_FILL = 2, | |
259 | SVGA_CMD_RECT_COPY = 3, | |
260 | SVGA_CMD_DEFINE_BITMAP = 4, | |
261 | SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5, | |
262 | SVGA_CMD_DEFINE_PIXMAP = 6, | |
263 | SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7, | |
264 | SVGA_CMD_RECT_BITMAP_FILL = 8, | |
265 | SVGA_CMD_RECT_PIXMAP_FILL = 9, | |
266 | SVGA_CMD_RECT_BITMAP_COPY = 10, | |
267 | SVGA_CMD_RECT_PIXMAP_COPY = 11, | |
268 | SVGA_CMD_FREE_OBJECT = 12, | |
269 | SVGA_CMD_RECT_ROP_FILL = 13, | |
270 | SVGA_CMD_RECT_ROP_COPY = 14, | |
271 | SVGA_CMD_RECT_ROP_BITMAP_FILL = 15, | |
272 | SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16, | |
273 | SVGA_CMD_RECT_ROP_BITMAP_COPY = 17, | |
274 | SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18, | |
275 | SVGA_CMD_DEFINE_CURSOR = 19, | |
276 | SVGA_CMD_DISPLAY_CURSOR = 20, | |
277 | SVGA_CMD_MOVE_CURSOR = 21, | |
278 | SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, | |
279 | SVGA_CMD_DRAW_GLYPH = 23, | |
280 | SVGA_CMD_DRAW_GLYPH_CLIPPED = 24, | |
281 | SVGA_CMD_UPDATE_VERBOSE = 25, | |
282 | SVGA_CMD_SURFACE_FILL = 26, | |
283 | SVGA_CMD_SURFACE_COPY = 27, | |
284 | SVGA_CMD_SURFACE_ALPHA_BLEND = 28, | |
285 | SVGA_CMD_FRONT_ROP_FILL = 29, | |
286 | SVGA_CMD_FENCE = 30, | |
287 | }; | |
288 | ||
289 | /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */ | |
290 | enum { | |
291 | SVGA_CURSOR_ON_HIDE = 0, | |
292 | SVGA_CURSOR_ON_SHOW = 1, | |
293 | SVGA_CURSOR_ON_REMOVE_FROM_FB = 2, | |
294 | SVGA_CURSOR_ON_RESTORE_TO_FB = 3, | |
295 | }; | |
296 | ||
07258900 GH |
297 | static inline bool vmsvga_verify_rect(DisplaySurface *surface, |
298 | const char *name, | |
299 | int x, int y, int w, int h) | |
300 | { | |
301 | if (x < 0) { | |
302 | fprintf(stderr, "%s: x was < 0 (%d)\n", name, x); | |
303 | return false; | |
304 | } | |
305 | if (x > SVGA_MAX_WIDTH) { | |
306 | fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x); | |
307 | return false; | |
308 | } | |
309 | if (w < 0) { | |
310 | fprintf(stderr, "%s: w was < 0 (%d)\n", name, w); | |
311 | return false; | |
312 | } | |
313 | if (w > SVGA_MAX_WIDTH) { | |
314 | fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w); | |
315 | return false; | |
316 | } | |
317 | if (x + w > surface_width(surface)) { | |
318 | fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n", | |
319 | name, surface_width(surface), x, w); | |
320 | return false; | |
321 | } | |
322 | ||
323 | if (y < 0) { | |
324 | fprintf(stderr, "%s: y was < 0 (%d)\n", name, y); | |
325 | return false; | |
326 | } | |
327 | if (y > SVGA_MAX_HEIGHT) { | |
328 | fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y); | |
329 | return false; | |
330 | } | |
331 | if (h < 0) { | |
332 | fprintf(stderr, "%s: h was < 0 (%d)\n", name, h); | |
333 | return false; | |
334 | } | |
335 | if (h > SVGA_MAX_HEIGHT) { | |
336 | fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h); | |
337 | return false; | |
338 | } | |
339 | if (y + h > surface_height(surface)) { | |
340 | fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n", | |
341 | name, surface_height(surface), y, h); | |
342 | return false; | |
343 | } | |
344 | ||
345 | return true; | |
346 | } | |
347 | ||
d34cab9f | 348 | static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
07258900 | 349 | int x, int y, int w, int h) |
d34cab9f | 350 | { |
c78f7137 | 351 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
a8fbaf96 AZ |
352 | int line; |
353 | int bypl; | |
354 | int width; | |
355 | int start; | |
356 | uint8_t *src; | |
357 | uint8_t *dst; | |
358 | ||
1735fe1e GH |
359 | if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { |
360 | /* go for a fullscreen update as fallback */ | |
8cb6bfb5 | 361 | x = 0; |
8cb6bfb5 | 362 | y = 0; |
1735fe1e GH |
363 | w = surface_width(surface); |
364 | h = surface_height(surface); | |
a8fbaf96 AZ |
365 | } |
366 | ||
c78f7137 GH |
367 | bypl = surface_stride(surface); |
368 | width = surface_bytes_per_pixel(surface) * w; | |
369 | start = surface_bytes_per_pixel(surface) * x + bypl * y; | |
4e12cd94 | 370 | src = s->vga.vram_ptr + start; |
c78f7137 | 371 | dst = surface_data(surface) + start; |
d34cab9f | 372 | |
0d793797 | 373 | for (line = h; line > 0; line--, src += bypl, dst += bypl) { |
d34cab9f | 374 | memcpy(dst, src, width); |
0d793797 | 375 | } |
c78f7137 | 376 | dpy_gfx_update(s->vga.con, x, y, w, h); |
d34cab9f TS |
377 | } |
378 | ||
d34cab9f TS |
379 | static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
380 | int x, int y, int w, int h) | |
381 | { | |
0d793797 BZ |
382 | struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; |
383 | ||
d34cab9f TS |
384 | s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; |
385 | rect->x = x; | |
386 | rect->y = y; | |
387 | rect->w = w; | |
388 | rect->h = h; | |
389 | } | |
d34cab9f TS |
390 | |
391 | static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) | |
392 | { | |
393 | struct vmsvga_rect_s *rect; | |
0d793797 | 394 | |
d34cab9f TS |
395 | if (s->invalidated) { |
396 | s->redraw_fifo_first = s->redraw_fifo_last; | |
397 | return; | |
398 | } | |
399 | /* Overlapping region updates can be optimised out here - if someone | |
400 | * knows a smart algorithm to do that, please share. */ | |
401 | while (s->redraw_fifo_first != s->redraw_fifo_last) { | |
0d793797 | 402 | rect = &s->redraw_fifo[s->redraw_fifo_first++]; |
d34cab9f TS |
403 | s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; |
404 | vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); | |
405 | } | |
406 | } | |
407 | ||
408 | #ifdef HW_RECT_ACCEL | |
61b41b4c | 409 | static inline int vmsvga_copy_rect(struct vmsvga_state_s *s, |
d34cab9f TS |
410 | int x0, int y0, int x1, int y1, int w, int h) |
411 | { | |
c78f7137 | 412 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
4e12cd94 | 413 | uint8_t *vram = s->vga.vram_ptr; |
c78f7137 GH |
414 | int bypl = surface_stride(surface); |
415 | int bypp = surface_bytes_per_pixel(surface); | |
aa32b38c | 416 | int width = bypp * w; |
d34cab9f TS |
417 | int line = h; |
418 | uint8_t *ptr[2]; | |
419 | ||
61b41b4c GH |
420 | if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) { |
421 | return -1; | |
422 | } | |
423 | if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) { | |
424 | return -1; | |
425 | } | |
426 | ||
8d121d49 | 427 | if (y1 > y0) { |
aa32b38c BZ |
428 | ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); |
429 | ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); | |
8d121d49 JK |
430 | for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { |
431 | memmove(ptr[1], ptr[0], width); | |
432 | } | |
433 | } else { | |
aa32b38c BZ |
434 | ptr[0] = vram + bypp * x0 + bypl * y0; |
435 | ptr[1] = vram + bypp * x1 + bypl * y1; | |
8d121d49 JK |
436 | for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { |
437 | memmove(ptr[1], ptr[0], width); | |
d34cab9f TS |
438 | } |
439 | } | |
440 | ||
441 | vmsvga_update_rect_delayed(s, x1, y1, w, h); | |
61b41b4c | 442 | return 0; |
d34cab9f TS |
443 | } |
444 | #endif | |
445 | ||
446 | #ifdef HW_FILL_ACCEL | |
bd9ccd85 | 447 | static inline int vmsvga_fill_rect(struct vmsvga_state_s *s, |
d34cab9f TS |
448 | uint32_t c, int x, int y, int w, int h) |
449 | { | |
c78f7137 GH |
450 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
451 | int bypl = surface_stride(surface); | |
452 | int width = surface_bytes_per_pixel(surface) * w; | |
d34cab9f TS |
453 | int line = h; |
454 | int column; | |
aa32b38c | 455 | uint8_t *fst; |
d34cab9f TS |
456 | uint8_t *dst; |
457 | uint8_t *src; | |
458 | uint8_t col[4]; | |
459 | ||
bd9ccd85 GH |
460 | if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) { |
461 | return -1; | |
462 | } | |
463 | ||
8d121d49 JK |
464 | col[0] = c; |
465 | col[1] = c >> 8; | |
466 | col[2] = c >> 16; | |
467 | col[3] = c >> 24; | |
468 | ||
c78f7137 | 469 | fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y; |
aa32b38c | 470 | |
8d121d49 JK |
471 | if (line--) { |
472 | dst = fst; | |
473 | src = col; | |
474 | for (column = width; column > 0; column--) { | |
475 | *(dst++) = *(src++); | |
c78f7137 | 476 | if (src - col == surface_bytes_per_pixel(surface)) { |
8d121d49 | 477 | src = col; |
d34cab9f TS |
478 | } |
479 | } | |
8d121d49 JK |
480 | dst = fst; |
481 | for (; line > 0; line--) { | |
482 | dst += bypl; | |
483 | memcpy(dst, fst, width); | |
484 | } | |
d34cab9f TS |
485 | } |
486 | ||
487 | vmsvga_update_rect_delayed(s, x, y, w, h); | |
bd9ccd85 | 488 | return 0; |
d34cab9f TS |
489 | } |
490 | #endif | |
491 | ||
492 | struct vmsvga_cursor_definition_s { | |
5829b097 GH |
493 | uint32_t width; |
494 | uint32_t height; | |
d34cab9f | 495 | int id; |
5829b097 | 496 | uint32_t bpp; |
d34cab9f TS |
497 | int hot_x; |
498 | int hot_y; | |
499 | uint32_t mask[1024]; | |
8095cb3e | 500 | uint32_t image[4096]; |
d34cab9f TS |
501 | }; |
502 | ||
0d793797 BZ |
503 | #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
504 | #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) | |
d34cab9f TS |
505 | |
506 | #ifdef HW_MOUSE_ACCEL | |
507 | static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, | |
508 | struct vmsvga_cursor_definition_s *c) | |
509 | { | |
fbe6d7a4 GH |
510 | QEMUCursor *qc; |
511 | int i, pixels; | |
512 | ||
513 | qc = cursor_alloc(c->width, c->height); | |
514 | qc->hot_x = c->hot_x; | |
515 | qc->hot_y = c->hot_y; | |
516 | switch (c->bpp) { | |
517 | case 1: | |
0d793797 BZ |
518 | cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, |
519 | 1, (void *)c->mask); | |
fbe6d7a4 GH |
520 | #ifdef DEBUG |
521 | cursor_print_ascii_art(qc, "vmware/mono"); | |
522 | #endif | |
523 | break; | |
524 | case 32: | |
525 | /* fill alpha channel from mask, set color to zero */ | |
0d793797 BZ |
526 | cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, |
527 | 1, (void *)c->mask); | |
fbe6d7a4 GH |
528 | /* add in rgb values */ |
529 | pixels = c->width * c->height; | |
530 | for (i = 0; i < pixels; i++) { | |
531 | qc->data[i] |= c->image[i] & 0xffffff; | |
532 | } | |
533 | #ifdef DEBUG | |
534 | cursor_print_ascii_art(qc, "vmware/32bit"); | |
535 | #endif | |
536 | break; | |
537 | default: | |
538 | fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", | |
0d793797 | 539 | __func__, c->bpp); |
fbe6d7a4 GH |
540 | cursor_put(qc); |
541 | qc = cursor_builtin_left_ptr(); | |
542 | } | |
d34cab9f | 543 | |
c78f7137 | 544 | dpy_cursor_define(s->vga.con, qc); |
fbe6d7a4 | 545 | cursor_put(qc); |
d34cab9f TS |
546 | } |
547 | #endif | |
548 | ||
0d793797 | 549 | #define CMD(f) le32_to_cpu(s->cmd->f) |
ff9cf2cb | 550 | |
4dedc07f | 551 | static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) |
d34cab9f | 552 | { |
4dedc07f | 553 | int num; |
0d793797 BZ |
554 | |
555 | if (!s->config || !s->enable) { | |
4dedc07f | 556 | return 0; |
0d793797 | 557 | } |
4dedc07f | 558 | num = CMD(next_cmd) - CMD(stop); |
0d793797 | 559 | if (num < 0) { |
4dedc07f | 560 | num += CMD(max) - CMD(min); |
0d793797 | 561 | } |
4dedc07f | 562 | return num >> 2; |
d34cab9f TS |
563 | } |
564 | ||
ff9cf2cb | 565 | static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
d34cab9f | 566 | { |
ff9cf2cb | 567 | uint32_t cmd = s->fifo[CMD(stop) >> 2]; |
0d793797 | 568 | |
ff9cf2cb | 569 | s->cmd->stop = cpu_to_le32(CMD(stop) + 4); |
0d793797 | 570 | if (CMD(stop) >= CMD(max)) { |
d34cab9f | 571 | s->cmd->stop = s->cmd->min; |
0d793797 | 572 | } |
d34cab9f TS |
573 | return cmd; |
574 | } | |
575 | ||
ff9cf2cb AZ |
576 | static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
577 | { | |
578 | return le32_to_cpu(vmsvga_fifo_read_raw(s)); | |
579 | } | |
580 | ||
d34cab9f TS |
581 | static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
582 | { | |
583 | uint32_t cmd, colour; | |
4dedc07f | 584 | int args, len; |
d34cab9f TS |
585 | int x, y, dx, dy, width, height; |
586 | struct vmsvga_cursor_definition_s cursor; | |
4dedc07f AZ |
587 | uint32_t cmd_start; |
588 | ||
589 | len = vmsvga_fifo_length(s); | |
590 | while (len > 0) { | |
591 | /* May need to go back to the start of the command if incomplete */ | |
592 | cmd_start = s->cmd->stop; | |
593 | ||
d34cab9f TS |
594 | switch (cmd = vmsvga_fifo_read(s)) { |
595 | case SVGA_CMD_UPDATE: | |
596 | case SVGA_CMD_UPDATE_VERBOSE: | |
4dedc07f | 597 | len -= 5; |
0d793797 | 598 | if (len < 0) { |
4dedc07f | 599 | goto rewind; |
0d793797 | 600 | } |
4dedc07f | 601 | |
d34cab9f TS |
602 | x = vmsvga_fifo_read(s); |
603 | y = vmsvga_fifo_read(s); | |
604 | width = vmsvga_fifo_read(s); | |
605 | height = vmsvga_fifo_read(s); | |
606 | vmsvga_update_rect_delayed(s, x, y, width, height); | |
607 | break; | |
608 | ||
609 | case SVGA_CMD_RECT_FILL: | |
4dedc07f | 610 | len -= 6; |
0d793797 | 611 | if (len < 0) { |
4dedc07f | 612 | goto rewind; |
0d793797 | 613 | } |
4dedc07f | 614 | |
d34cab9f TS |
615 | colour = vmsvga_fifo_read(s); |
616 | x = vmsvga_fifo_read(s); | |
617 | y = vmsvga_fifo_read(s); | |
618 | width = vmsvga_fifo_read(s); | |
619 | height = vmsvga_fifo_read(s); | |
620 | #ifdef HW_FILL_ACCEL | |
bd9ccd85 GH |
621 | if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) { |
622 | break; | |
623 | } | |
624 | #endif | |
4dedc07f | 625 | args = 0; |
d34cab9f | 626 | goto badcmd; |
d34cab9f TS |
627 | |
628 | case SVGA_CMD_RECT_COPY: | |
4dedc07f | 629 | len -= 7; |
0d793797 | 630 | if (len < 0) { |
4dedc07f | 631 | goto rewind; |
0d793797 | 632 | } |
4dedc07f | 633 | |
d34cab9f TS |
634 | x = vmsvga_fifo_read(s); |
635 | y = vmsvga_fifo_read(s); | |
636 | dx = vmsvga_fifo_read(s); | |
637 | dy = vmsvga_fifo_read(s); | |
638 | width = vmsvga_fifo_read(s); | |
639 | height = vmsvga_fifo_read(s); | |
640 | #ifdef HW_RECT_ACCEL | |
61b41b4c GH |
641 | if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) { |
642 | break; | |
643 | } | |
644 | #endif | |
4dedc07f | 645 | args = 0; |
d34cab9f | 646 | goto badcmd; |
d34cab9f TS |
647 | |
648 | case SVGA_CMD_DEFINE_CURSOR: | |
4dedc07f | 649 | len -= 8; |
0d793797 | 650 | if (len < 0) { |
4dedc07f | 651 | goto rewind; |
0d793797 | 652 | } |
4dedc07f | 653 | |
d34cab9f TS |
654 | cursor.id = vmsvga_fifo_read(s); |
655 | cursor.hot_x = vmsvga_fifo_read(s); | |
656 | cursor.hot_y = vmsvga_fifo_read(s); | |
657 | cursor.width = x = vmsvga_fifo_read(s); | |
658 | cursor.height = y = vmsvga_fifo_read(s); | |
659 | vmsvga_fifo_read(s); | |
660 | cursor.bpp = vmsvga_fifo_read(s); | |
f2d928d4 | 661 | |
4dedc07f | 662 | args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); |
5829b097 GH |
663 | if (cursor.width > 256 || |
664 | cursor.height > 256 || | |
665 | cursor.bpp > 32 || | |
666 | SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || | |
0d793797 | 667 | SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { |
9f810beb | 668 | goto badcmd; |
0d793797 | 669 | } |
4dedc07f AZ |
670 | |
671 | len -= args; | |
0d793797 | 672 | if (len < 0) { |
4dedc07f | 673 | goto rewind; |
0d793797 | 674 | } |
f2d928d4 | 675 | |
0d793797 | 676 | for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { |
ff9cf2cb | 677 | cursor.mask[args] = vmsvga_fifo_read_raw(s); |
0d793797 BZ |
678 | } |
679 | for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { | |
ff9cf2cb | 680 | cursor.image[args] = vmsvga_fifo_read_raw(s); |
0d793797 | 681 | } |
d34cab9f TS |
682 | #ifdef HW_MOUSE_ACCEL |
683 | vmsvga_cursor_define(s, &cursor); | |
684 | break; | |
685 | #else | |
686 | args = 0; | |
687 | goto badcmd; | |
688 | #endif | |
689 | ||
690 | /* | |
691 | * Other commands that we at least know the number of arguments | |
692 | * for so we can avoid FIFO desync if driver uses them illegally. | |
693 | */ | |
694 | case SVGA_CMD_DEFINE_ALPHA_CURSOR: | |
4dedc07f | 695 | len -= 6; |
0d793797 | 696 | if (len < 0) { |
4dedc07f | 697 | goto rewind; |
0d793797 | 698 | } |
d34cab9f TS |
699 | vmsvga_fifo_read(s); |
700 | vmsvga_fifo_read(s); | |
701 | vmsvga_fifo_read(s); | |
702 | x = vmsvga_fifo_read(s); | |
703 | y = vmsvga_fifo_read(s); | |
704 | args = x * y; | |
705 | goto badcmd; | |
706 | case SVGA_CMD_RECT_ROP_FILL: | |
707 | args = 6; | |
708 | goto badcmd; | |
709 | case SVGA_CMD_RECT_ROP_COPY: | |
710 | args = 7; | |
711 | goto badcmd; | |
712 | case SVGA_CMD_DRAW_GLYPH_CLIPPED: | |
4dedc07f | 713 | len -= 4; |
0d793797 | 714 | if (len < 0) { |
4dedc07f | 715 | goto rewind; |
0d793797 | 716 | } |
d34cab9f TS |
717 | vmsvga_fifo_read(s); |
718 | vmsvga_fifo_read(s); | |
719 | args = 7 + (vmsvga_fifo_read(s) >> 2); | |
720 | goto badcmd; | |
721 | case SVGA_CMD_SURFACE_ALPHA_BLEND: | |
722 | args = 12; | |
723 | goto badcmd; | |
724 | ||
725 | /* | |
726 | * Other commands that are not listed as depending on any | |
727 | * CAPABILITIES bits, but are not described in the README either. | |
728 | */ | |
729 | case SVGA_CMD_SURFACE_FILL: | |
730 | case SVGA_CMD_SURFACE_COPY: | |
731 | case SVGA_CMD_FRONT_ROP_FILL: | |
732 | case SVGA_CMD_FENCE: | |
733 | case SVGA_CMD_INVALID_CMD: | |
734 | break; /* Nop */ | |
735 | ||
736 | default: | |
4dedc07f | 737 | args = 0; |
d34cab9f | 738 | badcmd: |
4dedc07f | 739 | len -= args; |
0d793797 | 740 | if (len < 0) { |
4dedc07f | 741 | goto rewind; |
0d793797 BZ |
742 | } |
743 | while (args--) { | |
d34cab9f | 744 | vmsvga_fifo_read(s); |
0d793797 | 745 | } |
d34cab9f | 746 | printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", |
0d793797 | 747 | __func__, cmd); |
d34cab9f | 748 | break; |
4dedc07f AZ |
749 | |
750 | rewind: | |
751 | s->cmd->stop = cmd_start; | |
752 | break; | |
d34cab9f | 753 | } |
4dedc07f | 754 | } |
d34cab9f TS |
755 | |
756 | s->syncing = 0; | |
757 | } | |
758 | ||
759 | static uint32_t vmsvga_index_read(void *opaque, uint32_t address) | |
760 | { | |
467d44b2 | 761 | struct vmsvga_state_s *s = opaque; |
0d793797 | 762 | |
d34cab9f TS |
763 | return s->index; |
764 | } | |
765 | ||
766 | static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) | |
767 | { | |
467d44b2 | 768 | struct vmsvga_state_s *s = opaque; |
0d793797 | 769 | |
d34cab9f TS |
770 | s->index = index; |
771 | } | |
772 | ||
773 | static uint32_t vmsvga_value_read(void *opaque, uint32_t address) | |
774 | { | |
775 | uint32_t caps; | |
467d44b2 | 776 | struct vmsvga_state_s *s = opaque; |
c78f7137 | 777 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
eb2f9b02 | 778 | PixelFormat pf; |
7a6404cd | 779 | uint32_t ret; |
0d793797 | 780 | |
d34cab9f TS |
781 | switch (s->index) { |
782 | case SVGA_REG_ID: | |
7a6404cd GH |
783 | ret = s->svgaid; |
784 | break; | |
d34cab9f TS |
785 | |
786 | case SVGA_REG_ENABLE: | |
7a6404cd GH |
787 | ret = s->enable; |
788 | break; | |
d34cab9f TS |
789 | |
790 | case SVGA_REG_WIDTH: | |
eb2f9b02 | 791 | ret = s->new_width ? s->new_width : surface_width(surface); |
7a6404cd | 792 | break; |
d34cab9f TS |
793 | |
794 | case SVGA_REG_HEIGHT: | |
eb2f9b02 | 795 | ret = s->new_height ? s->new_height : surface_height(surface); |
7a6404cd | 796 | break; |
d34cab9f TS |
797 | |
798 | case SVGA_REG_MAX_WIDTH: | |
7a6404cd GH |
799 | ret = SVGA_MAX_WIDTH; |
800 | break; | |
d34cab9f TS |
801 | |
802 | case SVGA_REG_MAX_HEIGHT: | |
7a6404cd GH |
803 | ret = SVGA_MAX_HEIGHT; |
804 | break; | |
d34cab9f TS |
805 | |
806 | case SVGA_REG_DEPTH: | |
eb2f9b02 | 807 | ret = (s->new_depth == 32) ? 24 : s->new_depth; |
7a6404cd | 808 | break; |
d34cab9f TS |
809 | |
810 | case SVGA_REG_BITS_PER_PIXEL: | |
eb2f9b02 GH |
811 | case SVGA_REG_HOST_BITS_PER_PIXEL: |
812 | ret = s->new_depth; | |
7a6404cd | 813 | break; |
d34cab9f TS |
814 | |
815 | case SVGA_REG_PSEUDOCOLOR: | |
7a6404cd GH |
816 | ret = 0x0; |
817 | break; | |
d34cab9f TS |
818 | |
819 | case SVGA_REG_RED_MASK: | |
eb2f9b02 GH |
820 | pf = qemu_default_pixelformat(s->new_depth); |
821 | ret = pf.rmask; | |
7a6404cd | 822 | break; |
aa32b38c | 823 | |
d34cab9f | 824 | case SVGA_REG_GREEN_MASK: |
eb2f9b02 GH |
825 | pf = qemu_default_pixelformat(s->new_depth); |
826 | ret = pf.gmask; | |
7a6404cd | 827 | break; |
aa32b38c | 828 | |
d34cab9f | 829 | case SVGA_REG_BLUE_MASK: |
eb2f9b02 GH |
830 | pf = qemu_default_pixelformat(s->new_depth); |
831 | ret = pf.bmask; | |
7a6404cd | 832 | break; |
d34cab9f TS |
833 | |
834 | case SVGA_REG_BYTES_PER_LINE: | |
eb2f9b02 GH |
835 | if (s->new_width) { |
836 | ret = (s->new_depth * s->new_width) / 8; | |
837 | } else { | |
838 | ret = surface_stride(surface); | |
839 | } | |
7a6404cd | 840 | break; |
d34cab9f | 841 | |
7b619b9a AK |
842 | case SVGA_REG_FB_START: { |
843 | struct pci_vmsvga_state_s *pci_vmsvga | |
844 | = container_of(s, struct pci_vmsvga_state_s, chip); | |
af21c740 | 845 | ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1); |
7a6404cd | 846 | break; |
7b619b9a | 847 | } |
d34cab9f TS |
848 | |
849 | case SVGA_REG_FB_OFFSET: | |
7a6404cd GH |
850 | ret = 0x0; |
851 | break; | |
d34cab9f TS |
852 | |
853 | case SVGA_REG_VRAM_SIZE: | |
7a6404cd GH |
854 | ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */ |
855 | break; | |
d34cab9f TS |
856 | |
857 | case SVGA_REG_FB_SIZE: | |
7a6404cd GH |
858 | ret = s->vga.vram_size; |
859 | break; | |
d34cab9f TS |
860 | |
861 | case SVGA_REG_CAPABILITIES: | |
862 | caps = SVGA_CAP_NONE; | |
863 | #ifdef HW_RECT_ACCEL | |
864 | caps |= SVGA_CAP_RECT_COPY; | |
865 | #endif | |
866 | #ifdef HW_FILL_ACCEL | |
867 | caps |= SVGA_CAP_RECT_FILL; | |
868 | #endif | |
869 | #ifdef HW_MOUSE_ACCEL | |
c78f7137 | 870 | if (dpy_cursor_define_supported(s->vga.con)) { |
d34cab9f TS |
871 | caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
872 | SVGA_CAP_CURSOR_BYPASS; | |
bf2fde70 | 873 | } |
d34cab9f | 874 | #endif |
7a6404cd GH |
875 | ret = caps; |
876 | break; | |
d34cab9f | 877 | |
b1950430 AK |
878 | case SVGA_REG_MEM_START: { |
879 | struct pci_vmsvga_state_s *pci_vmsvga | |
880 | = container_of(s, struct pci_vmsvga_state_s, chip); | |
af21c740 | 881 | ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2); |
7a6404cd | 882 | break; |
b1950430 | 883 | } |
d34cab9f TS |
884 | |
885 | case SVGA_REG_MEM_SIZE: | |
7a6404cd GH |
886 | ret = s->fifo_size; |
887 | break; | |
d34cab9f TS |
888 | |
889 | case SVGA_REG_CONFIG_DONE: | |
7a6404cd GH |
890 | ret = s->config; |
891 | break; | |
d34cab9f TS |
892 | |
893 | case SVGA_REG_SYNC: | |
894 | case SVGA_REG_BUSY: | |
7a6404cd GH |
895 | ret = s->syncing; |
896 | break; | |
d34cab9f TS |
897 | |
898 | case SVGA_REG_GUEST_ID: | |
7a6404cd GH |
899 | ret = s->guest; |
900 | break; | |
d34cab9f TS |
901 | |
902 | case SVGA_REG_CURSOR_ID: | |
7a6404cd GH |
903 | ret = s->cursor.id; |
904 | break; | |
d34cab9f TS |
905 | |
906 | case SVGA_REG_CURSOR_X: | |
7a6404cd GH |
907 | ret = s->cursor.x; |
908 | break; | |
d34cab9f TS |
909 | |
910 | case SVGA_REG_CURSOR_Y: | |
e2bb4ae7 | 911 | ret = s->cursor.y; |
7a6404cd | 912 | break; |
d34cab9f TS |
913 | |
914 | case SVGA_REG_CURSOR_ON: | |
7a6404cd GH |
915 | ret = s->cursor.on; |
916 | break; | |
d34cab9f | 917 | |
d34cab9f | 918 | case SVGA_REG_SCRATCH_SIZE: |
7a6404cd GH |
919 | ret = s->scratch_size; |
920 | break; | |
d34cab9f TS |
921 | |
922 | case SVGA_REG_MEM_REGS: | |
923 | case SVGA_REG_NUM_DISPLAYS: | |
924 | case SVGA_REG_PITCHLOCK: | |
925 | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: | |
7a6404cd GH |
926 | ret = 0; |
927 | break; | |
d34cab9f TS |
928 | |
929 | default: | |
930 | if (s->index >= SVGA_SCRATCH_BASE && | |
0d793797 | 931 | s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
7a6404cd GH |
932 | ret = s->scratch[s->index - SVGA_SCRATCH_BASE]; |
933 | break; | |
0d793797 BZ |
934 | } |
935 | printf("%s: Bad register %02x\n", __func__, s->index); | |
7a6404cd GH |
936 | ret = 0; |
937 | break; | |
d34cab9f TS |
938 | } |
939 | ||
7a6404cd GH |
940 | if (s->index >= SVGA_SCRATCH_BASE) { |
941 | trace_vmware_scratch_read(s->index, ret); | |
942 | } else if (s->index >= SVGA_PALETTE_BASE) { | |
943 | trace_vmware_palette_read(s->index, ret); | |
944 | } else { | |
945 | trace_vmware_value_read(s->index, ret); | |
946 | } | |
947 | return ret; | |
d34cab9f TS |
948 | } |
949 | ||
950 | static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) | |
951 | { | |
467d44b2 | 952 | struct vmsvga_state_s *s = opaque; |
0d793797 | 953 | |
7a6404cd GH |
954 | if (s->index >= SVGA_SCRATCH_BASE) { |
955 | trace_vmware_scratch_write(s->index, value); | |
956 | } else if (s->index >= SVGA_PALETTE_BASE) { | |
957 | trace_vmware_palette_write(s->index, value); | |
958 | } else { | |
959 | trace_vmware_value_write(s->index, value); | |
960 | } | |
d34cab9f TS |
961 | switch (s->index) { |
962 | case SVGA_REG_ID: | |
0d793797 | 963 | if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { |
d34cab9f | 964 | s->svgaid = value; |
0d793797 | 965 | } |
d34cab9f TS |
966 | break; |
967 | ||
968 | case SVGA_REG_ENABLE: | |
b51d7b2e | 969 | s->enable = !!value; |
d34cab9f | 970 | s->invalidated = 1; |
380cd056 | 971 | s->vga.hw_ops->invalidate(&s->vga); |
b51d7b2e | 972 | if (s->enable && s->config) { |
9f810beb AZ |
973 | vga_dirty_log_stop(&s->vga); |
974 | } else { | |
975 | vga_dirty_log_start(&s->vga); | |
976 | } | |
d34cab9f TS |
977 | break; |
978 | ||
979 | case SVGA_REG_WIDTH: | |
aa32b38c BZ |
980 | if (value <= SVGA_MAX_WIDTH) { |
981 | s->new_width = value; | |
982 | s->invalidated = 1; | |
983 | } else { | |
984 | printf("%s: Bad width: %i\n", __func__, value); | |
985 | } | |
d34cab9f TS |
986 | break; |
987 | ||
988 | case SVGA_REG_HEIGHT: | |
aa32b38c BZ |
989 | if (value <= SVGA_MAX_HEIGHT) { |
990 | s->new_height = value; | |
991 | s->invalidated = 1; | |
992 | } else { | |
993 | printf("%s: Bad height: %i\n", __func__, value); | |
994 | } | |
d34cab9f TS |
995 | break; |
996 | ||
d34cab9f | 997 | case SVGA_REG_BITS_PER_PIXEL: |
eb2f9b02 | 998 | if (value != 32) { |
5b9575c8 | 999 | printf("%s: Bad bits per pixel: %i bits\n", __func__, value); |
d34cab9f | 1000 | s->config = 0; |
eb2f9b02 | 1001 | s->invalidated = 1; |
d34cab9f TS |
1002 | } |
1003 | break; | |
1004 | ||
1005 | case SVGA_REG_CONFIG_DONE: | |
1006 | if (value) { | |
f351d050 | 1007 | s->fifo = (uint32_t *) s->fifo_ptr; |
d34cab9f | 1008 | /* Check range and alignment. */ |
0d793797 | 1009 | if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { |
d34cab9f | 1010 | break; |
0d793797 BZ |
1011 | } |
1012 | if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { | |
d34cab9f | 1013 | break; |
0d793797 BZ |
1014 | } |
1015 | if (CMD(max) > SVGA_FIFO_SIZE) { | |
d34cab9f | 1016 | break; |
0d793797 BZ |
1017 | } |
1018 | if (CMD(max) < CMD(min) + 10 * 1024) { | |
d34cab9f | 1019 | break; |
0d793797 | 1020 | } |
b51d7b2e | 1021 | vga_dirty_log_stop(&s->vga); |
d34cab9f | 1022 | } |
f707cfba | 1023 | s->config = !!value; |
d34cab9f TS |
1024 | break; |
1025 | ||
1026 | case SVGA_REG_SYNC: | |
1027 | s->syncing = 1; | |
1028 | vmsvga_fifo_run(s); /* Or should we just wait for update_display? */ | |
1029 | break; | |
1030 | ||
1031 | case SVGA_REG_GUEST_ID: | |
1032 | s->guest = value; | |
1033 | #ifdef VERBOSE | |
1034 | if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + | |
0d793797 BZ |
1035 | ARRAY_SIZE(vmsvga_guest_id)) { |
1036 | printf("%s: guest runs %s.\n", __func__, | |
1037 | vmsvga_guest_id[value - GUEST_OS_BASE]); | |
1038 | } | |
d34cab9f TS |
1039 | #endif |
1040 | break; | |
1041 | ||
1042 | case SVGA_REG_CURSOR_ID: | |
1043 | s->cursor.id = value; | |
1044 | break; | |
1045 | ||
1046 | case SVGA_REG_CURSOR_X: | |
1047 | s->cursor.x = value; | |
1048 | break; | |
1049 | ||
1050 | case SVGA_REG_CURSOR_Y: | |
1051 | s->cursor.y = value; | |
1052 | break; | |
1053 | ||
1054 | case SVGA_REG_CURSOR_ON: | |
1055 | s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); | |
1056 | s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); | |
1057 | #ifdef HW_MOUSE_ACCEL | |
bf2fde70 | 1058 | if (value <= SVGA_CURSOR_ON_SHOW) { |
c78f7137 | 1059 | dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on); |
bf2fde70 | 1060 | } |
d34cab9f TS |
1061 | #endif |
1062 | break; | |
1063 | ||
5b9575c8 | 1064 | case SVGA_REG_DEPTH: |
d34cab9f TS |
1065 | case SVGA_REG_MEM_REGS: |
1066 | case SVGA_REG_NUM_DISPLAYS: | |
1067 | case SVGA_REG_PITCHLOCK: | |
1068 | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END: | |
1069 | break; | |
1070 | ||
1071 | default: | |
1072 | if (s->index >= SVGA_SCRATCH_BASE && | |
1073 | s->index < SVGA_SCRATCH_BASE + s->scratch_size) { | |
1074 | s->scratch[s->index - SVGA_SCRATCH_BASE] = value; | |
1075 | break; | |
1076 | } | |
0d793797 | 1077 | printf("%s: Bad register %02x\n", __func__, s->index); |
d34cab9f TS |
1078 | } |
1079 | } | |
1080 | ||
1081 | static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) | |
1082 | { | |
0d793797 | 1083 | printf("%s: what are we supposed to return?\n", __func__); |
d34cab9f TS |
1084 | return 0xcafe; |
1085 | } | |
1086 | ||
1087 | static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) | |
1088 | { | |
0d793797 | 1089 | printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); |
d34cab9f TS |
1090 | } |
1091 | ||
aa32b38c | 1092 | static inline void vmsvga_check_size(struct vmsvga_state_s *s) |
d34cab9f | 1093 | { |
c78f7137 GH |
1094 | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
1095 | ||
1096 | if (s->new_width != surface_width(surface) || | |
eb2f9b02 GH |
1097 | s->new_height != surface_height(surface) || |
1098 | s->new_depth != surface_bits_per_pixel(surface)) { | |
1099 | int stride = (s->new_depth * s->new_width) / 8; | |
30f1e661 GH |
1100 | pixman_format_code_t format = |
1101 | qemu_default_pixman_format(s->new_depth, true); | |
eb2f9b02 GH |
1102 | trace_vmware_setmode(s->new_width, s->new_height, s->new_depth); |
1103 | surface = qemu_create_displaysurface_from(s->new_width, s->new_height, | |
30f1e661 GH |
1104 | format, stride, |
1105 | s->vga.vram_ptr); | |
eb2f9b02 | 1106 | dpy_gfx_replace_surface(s->vga.con, surface); |
d34cab9f TS |
1107 | s->invalidated = 1; |
1108 | } | |
1109 | } | |
1110 | ||
1111 | static void vmsvga_update_display(void *opaque) | |
1112 | { | |
467d44b2 | 1113 | struct vmsvga_state_s *s = opaque; |
17866fc8 | 1114 | DisplaySurface *surface; |
b51d7b2e BZ |
1115 | bool dirty = false; |
1116 | ||
d34cab9f | 1117 | if (!s->enable) { |
380cd056 | 1118 | s->vga.hw_ops->gfx_update(&s->vga); |
d34cab9f TS |
1119 | return; |
1120 | } | |
1121 | ||
aa32b38c | 1122 | vmsvga_check_size(s); |
17866fc8 | 1123 | surface = qemu_console_surface(s->vga.con); |
d34cab9f TS |
1124 | |
1125 | vmsvga_fifo_run(s); | |
1126 | vmsvga_update_rect_flush(s); | |
1127 | ||
1128 | /* | |
1129 | * Is it more efficient to look at vram VGA-dirty bits or wait | |
1130 | * for the driver to issue SVGA_CMD_UPDATE? | |
1131 | */ | |
2d1a35be | 1132 | if (memory_region_is_logging(&s->vga.vram, DIRTY_MEMORY_VGA)) { |
b51d7b2e BZ |
1133 | vga_sync_dirty_bitmap(&s->vga); |
1134 | dirty = memory_region_get_dirty(&s->vga.vram, 0, | |
c78f7137 | 1135 | surface_stride(surface) * surface_height(surface), |
b51d7b2e BZ |
1136 | DIRTY_MEMORY_VGA); |
1137 | } | |
1138 | if (s->invalidated || dirty) { | |
d34cab9f | 1139 | s->invalidated = 0; |
c78f7137 GH |
1140 | dpy_gfx_update(s->vga.con, 0, 0, |
1141 | surface_width(surface), surface_height(surface)); | |
b51d7b2e BZ |
1142 | } |
1143 | if (dirty) { | |
1144 | memory_region_reset_dirty(&s->vga.vram, 0, | |
c78f7137 | 1145 | surface_stride(surface) * surface_height(surface), |
b51d7b2e | 1146 | DIRTY_MEMORY_VGA); |
d34cab9f TS |
1147 | } |
1148 | } | |
1149 | ||
8a9501ba | 1150 | static void vmsvga_reset(DeviceState *dev) |
d34cab9f | 1151 | { |
39d45987 | 1152 | struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev); |
8a9501ba JK |
1153 | struct vmsvga_state_s *s = &pci->chip; |
1154 | ||
d34cab9f TS |
1155 | s->index = 0; |
1156 | s->enable = 0; | |
1157 | s->config = 0; | |
d34cab9f | 1158 | s->svgaid = SVGA_ID; |
d34cab9f TS |
1159 | s->cursor.on = 0; |
1160 | s->redraw_fifo_first = 0; | |
1161 | s->redraw_fifo_last = 0; | |
d34cab9f | 1162 | s->syncing = 0; |
b5cc6e32 AL |
1163 | |
1164 | vga_dirty_log_start(&s->vga); | |
d34cab9f TS |
1165 | } |
1166 | ||
1167 | static void vmsvga_invalidate_display(void *opaque) | |
1168 | { | |
467d44b2 | 1169 | struct vmsvga_state_s *s = opaque; |
d34cab9f | 1170 | if (!s->enable) { |
380cd056 | 1171 | s->vga.hw_ops->invalidate(&s->vga); |
d34cab9f TS |
1172 | return; |
1173 | } | |
1174 | ||
1175 | s->invalidated = 1; | |
1176 | } | |
1177 | ||
c227f099 | 1178 | static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
4d3b6f6e | 1179 | { |
467d44b2 | 1180 | struct vmsvga_state_s *s = opaque; |
4d3b6f6e | 1181 | |
380cd056 GH |
1182 | if (s->vga.hw_ops->text_update) { |
1183 | s->vga.hw_ops->text_update(&s->vga, chardata); | |
0d793797 | 1184 | } |
4d3b6f6e AZ |
1185 | } |
1186 | ||
bacbe284 | 1187 | static int vmsvga_post_load(void *opaque, int version_id) |
d34cab9f | 1188 | { |
bacbe284 | 1189 | struct vmsvga_state_s *s = opaque; |
d34cab9f TS |
1190 | |
1191 | s->invalidated = 1; | |
0d793797 | 1192 | if (s->config) { |
f351d050 | 1193 | s->fifo = (uint32_t *) s->fifo_ptr; |
0d793797 | 1194 | } |
d34cab9f TS |
1195 | return 0; |
1196 | } | |
1197 | ||
d05ac8fa | 1198 | static const VMStateDescription vmstate_vmware_vga_internal = { |
bacbe284 JQ |
1199 | .name = "vmware_vga_internal", |
1200 | .version_id = 0, | |
1201 | .minimum_version_id = 0, | |
bacbe284 | 1202 | .post_load = vmsvga_post_load, |
d49805ae | 1203 | .fields = (VMStateField[]) { |
eb2f9b02 | 1204 | VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s), |
bacbe284 JQ |
1205 | VMSTATE_INT32(enable, struct vmsvga_state_s), |
1206 | VMSTATE_INT32(config, struct vmsvga_state_s), | |
1207 | VMSTATE_INT32(cursor.id, struct vmsvga_state_s), | |
1208 | VMSTATE_INT32(cursor.x, struct vmsvga_state_s), | |
1209 | VMSTATE_INT32(cursor.y, struct vmsvga_state_s), | |
1210 | VMSTATE_INT32(cursor.on, struct vmsvga_state_s), | |
1211 | VMSTATE_INT32(index, struct vmsvga_state_s), | |
1212 | VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s, | |
1213 | scratch_size, 0, vmstate_info_uint32, uint32_t), | |
1214 | VMSTATE_INT32(new_width, struct vmsvga_state_s), | |
1215 | VMSTATE_INT32(new_height, struct vmsvga_state_s), | |
1216 | VMSTATE_UINT32(guest, struct vmsvga_state_s), | |
1217 | VMSTATE_UINT32(svgaid, struct vmsvga_state_s), | |
1218 | VMSTATE_INT32(syncing, struct vmsvga_state_s), | |
5b9575c8 | 1219 | VMSTATE_UNUSED(4), /* was fb_size */ |
bacbe284 JQ |
1220 | VMSTATE_END_OF_LIST() |
1221 | } | |
1222 | }; | |
1223 | ||
d05ac8fa | 1224 | static const VMStateDescription vmstate_vmware_vga = { |
bacbe284 JQ |
1225 | .name = "vmware_vga", |
1226 | .version_id = 0, | |
1227 | .minimum_version_id = 0, | |
d49805ae | 1228 | .fields = (VMStateField[]) { |
af21c740 | 1229 | VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s), |
bacbe284 JQ |
1230 | VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, |
1231 | vmstate_vmware_vga_internal, struct vmsvga_state_s), | |
1232 | VMSTATE_END_OF_LIST() | |
1233 | } | |
1234 | }; | |
1235 | ||
380cd056 GH |
1236 | static const GraphicHwOps vmsvga_ops = { |
1237 | .invalidate = vmsvga_invalidate_display, | |
1238 | .gfx_update = vmsvga_update_display, | |
1239 | .text_update = vmsvga_text_update, | |
1240 | }; | |
1241 | ||
aa2beaa1 | 1242 | static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, |
0a039dc7 | 1243 | MemoryRegion *address_space, MemoryRegion *io) |
d34cab9f | 1244 | { |
d34cab9f | 1245 | s->scratch_size = SVGA_SCRATCH_SIZE; |
7267c094 | 1246 | s->scratch = g_malloc(s->scratch_size * 4); |
d34cab9f | 1247 | |
5643706a | 1248 | s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s); |
4445b0a6 | 1249 | |
f351d050 | 1250 | s->fifo_size = SVGA_FIFO_SIZE; |
49946538 | 1251 | memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, |
f8ed85ac | 1252 | &error_fatal); |
c5705a77 | 1253 | vmstate_register_ram_global(&s->fifo_ram); |
b1950430 | 1254 | s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); |
f351d050 | 1255 | |
e2bbfc8e | 1256 | vga_common_init(&s->vga, OBJECT(dev), true); |
712f0cc7 | 1257 | vga_init(&s->vga, OBJECT(dev), address_space, io, true); |
0be71e32 | 1258 | vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); |
eb2f9b02 | 1259 | s->new_depth = 32; |
d34cab9f TS |
1260 | } |
1261 | ||
aa32b38c | 1262 | static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) |
1492a3c4 | 1263 | { |
b1950430 AK |
1264 | struct vmsvga_state_s *s = opaque; |
1265 | ||
1266 | switch (addr) { | |
1267 | case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); | |
1268 | case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); | |
1269 | case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); | |
1270 | default: return -1u; | |
1271 | } | |
1492a3c4 AZ |
1272 | } |
1273 | ||
a8170e5e | 1274 | static void vmsvga_io_write(void *opaque, hwaddr addr, |
b1950430 | 1275 | uint64_t data, unsigned size) |
3016d80b | 1276 | { |
b1950430 | 1277 | struct vmsvga_state_s *s = opaque; |
ee3e41a9 | 1278 | |
b1950430 AK |
1279 | switch (addr) { |
1280 | case SVGA_IO_MUL * SVGA_INDEX_PORT: | |
0ed8b6f6 BS |
1281 | vmsvga_index_write(s, addr, data); |
1282 | break; | |
b1950430 | 1283 | case SVGA_IO_MUL * SVGA_VALUE_PORT: |
0ed8b6f6 BS |
1284 | vmsvga_value_write(s, addr, data); |
1285 | break; | |
b1950430 | 1286 | case SVGA_IO_MUL * SVGA_BIOS_PORT: |
0ed8b6f6 BS |
1287 | vmsvga_bios_write(s, addr, data); |
1288 | break; | |
b1950430 | 1289 | } |
3016d80b AZ |
1290 | } |
1291 | ||
b1950430 AK |
1292 | static const MemoryRegionOps vmsvga_io_ops = { |
1293 | .read = vmsvga_io_read, | |
1294 | .write = vmsvga_io_write, | |
1295 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1296 | .valid = { | |
1297 | .min_access_size = 4, | |
1298 | .max_access_size = 4, | |
04e8cd50 JK |
1299 | .unaligned = true, |
1300 | }, | |
1301 | .impl = { | |
1302 | .unaligned = true, | |
b1950430 AK |
1303 | }, |
1304 | }; | |
f351d050 | 1305 | |
9af21dbe | 1306 | static void pci_vmsvga_realize(PCIDevice *dev, Error **errp) |
d34cab9f | 1307 | { |
39d45987 | 1308 | struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev); |
b1950430 | 1309 | |
af21c740 AF |
1310 | dev->config[PCI_CACHE_LINE_SIZE] = 0x08; |
1311 | dev->config[PCI_LATENCY_TIMER] = 0x40; | |
1312 | dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */ | |
d34cab9f | 1313 | |
2c9b15ca | 1314 | memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip, |
b1950430 | 1315 | "vmsvga-io", 0x10); |
bd8f2f5d | 1316 | memory_region_set_flush_coalesced(&s->io_bar); |
af21c740 | 1317 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); |
f351d050 | 1318 | |
aa2beaa1 GH |
1319 | vmsvga_init(DEVICE(dev), &s->chip, |
1320 | pci_address_space(dev), pci_address_space_io(dev)); | |
d34cab9f | 1321 | |
af21c740 | 1322 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, |
aa32b38c | 1323 | &s->chip.vga.vram); |
af21c740 | 1324 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, |
e824b2cc | 1325 | &s->chip.fifo_ram); |
b1950430 | 1326 | |
281a26b1 GH |
1327 | if (!dev->rom_bar) { |
1328 | /* compatibility with pc-0.13 and older */ | |
83118327 | 1329 | vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev)); |
281a26b1 | 1330 | } |
d34cab9f | 1331 | } |
a414c306 | 1332 | |
4a1e244e GH |
1333 | static Property vga_vmware_properties[] = { |
1334 | DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s, | |
9e56edcf | 1335 | chip.vga.vram_size_mb, 16), |
4a1e244e GH |
1336 | DEFINE_PROP_END_OF_LIST(), |
1337 | }; | |
1338 | ||
40021f08 AL |
1339 | static void vmsvga_class_init(ObjectClass *klass, void *data) |
1340 | { | |
39bffca2 | 1341 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1342 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1343 | ||
9af21dbe | 1344 | k->realize = pci_vmsvga_realize; |
40021f08 AL |
1345 | k->romfile = "vgabios-vmware.bin"; |
1346 | k->vendor_id = PCI_VENDOR_ID_VMWARE; | |
1347 | k->device_id = SVGA_PCI_DEVICE_ID; | |
1348 | k->class_id = PCI_CLASS_DISPLAY_VGA; | |
1349 | k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; | |
1350 | k->subsystem_id = SVGA_PCI_DEVICE_ID; | |
39bffca2 AL |
1351 | dc->reset = vmsvga_reset; |
1352 | dc->vmsd = &vmstate_vmware_vga; | |
4a1e244e | 1353 | dc->props = vga_vmware_properties; |
2897ae02 | 1354 | dc->hotpluggable = false; |
125ee0ed | 1355 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
40021f08 AL |
1356 | } |
1357 | ||
8c43a6f0 | 1358 | static const TypeInfo vmsvga_info = { |
39d45987 | 1359 | .name = TYPE_VMWARE_SVGA, |
39bffca2 AL |
1360 | .parent = TYPE_PCI_DEVICE, |
1361 | .instance_size = sizeof(struct pci_vmsvga_state_s), | |
1362 | .class_init = vmsvga_class_init, | |
a414c306 GH |
1363 | }; |
1364 | ||
83f7d43a | 1365 | static void vmsvga_register_types(void) |
a414c306 | 1366 | { |
39bffca2 | 1367 | type_register_static(&vmsvga_info); |
a414c306 | 1368 | } |
83f7d43a AF |
1369 | |
1370 | type_init(vmsvga_register_types) |