[thirdparty/qemu.git] / hw / dma / bcm2835_dma.c

/*
 * Raspberry Pi emulation (c) 2012 Gregory Estrade
 * This code is licensed under the GNU GPLv2 and later.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/dma/bcm2835_dma.h"

/* DMA CS Control and Status bits */
#define BCM2708_DMA_ACTIVE      (1 << 0)
#define BCM2708_DMA_END         (1 << 1) /* GE */
#define BCM2708_DMA_INT         (1 << 2)
#define BCM2708_DMA_ISPAUSED    (1 << 4)  /* Pause requested or not active */
#define BCM2708_DMA_ISHELD      (1 << 5)  /* Is held by DREQ flow control */
#define BCM2708_DMA_ERR         (1 << 8)
#define BCM2708_DMA_ABORT       (1 << 30) /* stop current CB, go to next, WO */
#define BCM2708_DMA_RESET       (1 << 31) /* WO, self clearing */

/* DMA control block "info" field bits */
#define BCM2708_DMA_INT_EN      (1 << 0)
#define BCM2708_DMA_TDMODE      (1 << 1)
#define BCM2708_DMA_WAIT_RESP   (1 << 3)
#define BCM2708_DMA_D_INC       (1 << 4)
#define BCM2708_DMA_D_WIDTH     (1 << 5)
#define BCM2708_DMA_D_DREQ      (1 << 6)
#define BCM2708_DMA_D_IGNORE    (1 << 7)
#define BCM2708_DMA_S_INC       (1 << 8)
#define BCM2708_DMA_S_WIDTH     (1 << 9)
#define BCM2708_DMA_S_DREQ      (1 << 10)
#define BCM2708_DMA_S_IGNORE    (1 << 11)

/* Register offsets */
#define BCM2708_DMA_CS          0x00 /* Control and Status */
#define BCM2708_DMA_ADDR        0x04 /* Control block address */
/* the current control block appears in the following registers - read only */
#define BCM2708_DMA_INFO        0x08
#define BCM2708_DMA_SOURCE_AD   0x0c
#define BCM2708_DMA_DEST_AD     0x10
#define BCM2708_DMA_TXFR_LEN    0x14
#define BCM2708_DMA_STRIDE      0x18
#define BCM2708_DMA_NEXTCB      0x1C
#define BCM2708_DMA_DEBUG       0x20

#define BCM2708_DMA_INT_STATUS  0xfe0 /* Interrupt status of each channel */
#define BCM2708_DMA_ENABLE      0xff0 /* Global enable bits for each channel */

#define BCM2708_DMA_CS_RW_MASK  0x30ff0001 /* All RW bits in DMA_CS */

static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
{
    BCM2835DMAChan *ch = &s->chan[c];
    uint32_t data, xlen, ylen;
    int16_t dst_stride, src_stride;

    if (!(s->enable & (1 << c))) {
        return;
    }

    while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
        /* CB fetch */
        ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad);
        ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4);
        ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8);
        ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12);
        ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
        ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);

        if (ch->ti & BCM2708_DMA_TDMODE) {
            /* 2D transfer mode */
            ylen = (ch->txfr_len >> 16) & 0x3fff;
            xlen = ch->txfr_len & 0xffff;
            dst_stride = ch->stride >> 16;
            src_stride = ch->stride & 0xffff;
        } else {
            ylen = 1;
            xlen = ch->txfr_len;
            dst_stride = 0;
            src_stride = 0;
        }

        while (ylen != 0) {
            /* Normal transfer mode */
            while (xlen != 0) {
                if (ch->ti & BCM2708_DMA_S_IGNORE) {
                    /* Ignore reads */
                    data = 0;
                } else {
                    data = ldl_le_phys(&s->dma_as, ch->source_ad);
                }
                if (ch->ti & BCM2708_DMA_S_INC) {
                    ch->source_ad += 4;
                }

                if (ch->ti & BCM2708_DMA_D_IGNORE) {
                    /* Ignore writes */
                } else {
                    stl_le_phys(&s->dma_as, ch->dest_ad, data);
                }
                if (ch->ti & BCM2708_DMA_D_INC) {
                    ch->dest_ad += 4;
                }

                /* update remaining transfer length */
                xlen -= 4;
                if (ch->ti & BCM2708_DMA_TDMODE) {
                    ch->txfr_len = (ylen << 16) | xlen;
                } else {
                    ch->txfr_len = xlen;
                }
            }

            if (--ylen != 0) {
                ch->source_ad += src_stride;
                ch->dest_ad += dst_stride;
            }
        }
        ch->cs |= BCM2708_DMA_END;
        if (ch->ti & BCM2708_DMA_INT_EN) {
            ch->cs |= BCM2708_DMA_INT;
            s->int_status |= (1 << c);
            qemu_set_irq(ch->irq, 1);
        }

        /* Process next CB */
        ch->conblk_ad = ch->nextconbk;
    }

    ch->cs &= ~BCM2708_DMA_ACTIVE;
    ch->cs |= BCM2708_DMA_ISPAUSED;
}

static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch)
{
    ch->cs = 0;
    ch->conblk_ad = 0;
}

static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
                                 unsigned size, unsigned c)
{
    BCM2835DMAChan *ch;
    uint32_t res = 0;

    assert(size == 4);
    assert(c < BCM2835_DMA_NCHANS);

    ch = &s->chan[c];

    switch (offset) {
    case BCM2708_DMA_CS:
        res = ch->cs;
        break;
    case BCM2708_DMA_ADDR:
        res = ch->conblk_ad;
        break;
    case BCM2708_DMA_INFO:
        res = ch->ti;
        break;
    case BCM2708_DMA_SOURCE_AD:
        res = ch->source_ad;
        break;
    case BCM2708_DMA_DEST_AD:
        res = ch->dest_ad;
        break;
    case BCM2708_DMA_TXFR_LEN:
        res = ch->txfr_len;
        break;
    case BCM2708_DMA_STRIDE:
        res = ch->stride;
        break;
    case BCM2708_DMA_NEXTCB:
        res = ch->nextconbk;
        break;
    case BCM2708_DMA_DEBUG:
        res = ch->debug;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
                      __func__, offset);
        break;
    }
    return res;
}

static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
                              uint64_t value, unsigned size, unsigned c)
{
    BCM2835DMAChan *ch;
    uint32_t oldcs;

    assert(size == 4);
    assert(c < BCM2835_DMA_NCHANS);

    ch = &s->chan[c];

    switch (offset) {
    case BCM2708_DMA_CS:
        oldcs = ch->cs;
        if (value & BCM2708_DMA_RESET) {
            bcm2835_dma_chan_reset(ch);
        }
        if (value & BCM2708_DMA_ABORT) {
            /* abort is a no-op, since we always run to completion */
        }
        if (value & BCM2708_DMA_END) {
            ch->cs &= ~BCM2708_DMA_END;
        }
        if (value & BCM2708_DMA_INT) {
            ch->cs &= ~BCM2708_DMA_INT;
            s->int_status &= ~(1 << c);
            qemu_set_irq(ch->irq, 0);
        }
        ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
        ch->cs |= (value & BCM2708_DMA_CS_RW_MASK);
        if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
            bcm2835_dma_update(s, c);
        }
        break;
    case BCM2708_DMA_ADDR:
        ch->conblk_ad = value;
        break;
    case BCM2708_DMA_DEBUG:
        ch->debug = value;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
                      __func__, offset);
        break;
    }
}

static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
{
    BCM2835DMAState *s = opaque;

    if (offset < 0xf00) {
        return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
    } else {
        switch (offset) {
        case BCM2708_DMA_INT_STATUS:
            return s->int_status;
        case BCM2708_DMA_ENABLE:
            return s->enable;
        default:
            qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
                          __func__, offset);
            return 0;
        }
    }
}

static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
{
    return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
}

static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
                               unsigned size)
{
    BCM2835DMAState *s = opaque;

    if (offset < 0xf00) {
        bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
    } else {
        switch (offset) {
        case BCM2708_DMA_INT_STATUS:
            break;
        case BCM2708_DMA_ENABLE:
            s->enable = (value & 0xffff);
            break;
        default:
            qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
                          __func__, offset);
        }
    }

}

static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
                                unsigned size)
{
    bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
}

static const MemoryRegionOps bcm2835_dma0_ops = {
    .read = bcm2835_dma0_read,
    .write = bcm2835_dma0_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
};

static const MemoryRegionOps bcm2835_dma15_ops = {
    .read = bcm2835_dma15_read,
    .write = bcm2835_dma15_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
};

static const VMStateDescription vmstate_bcm2835_dma_chan = {
    .name = TYPE_BCM2835_DMA "-chan",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cs, BCM2835DMAChan),
        VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
        VMSTATE_UINT32(ti, BCM2835DMAChan),
        VMSTATE_UINT32(source_ad, BCM2835DMAChan),
        VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
        VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
        VMSTATE_UINT32(stride, BCM2835DMAChan),
        VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
        VMSTATE_UINT32(debug, BCM2835DMAChan),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_bcm2835_dma = {
    .name = TYPE_BCM2835_DMA,
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
                             vmstate_bcm2835_dma_chan, BCM2835DMAChan),
        VMSTATE_UINT32(int_status, BCM2835DMAState),
        VMSTATE_UINT32(enable, BCM2835DMAState),
        VMSTATE_END_OF_LIST()
    }
};

static void bcm2835_dma_init(Object *obj)
{
    BCM2835DMAState *s = BCM2835_DMA(obj);
    int n;

    /* DMA channels 0-14 occupy a contiguous block of IO memory, along
     * with the global enable and interrupt status bits. Channel 15
     * has the same register map, but is mapped at a discontiguous
     * address in a separate IO block.
     */
    memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
                          TYPE_BCM2835_DMA, 0x1000);
    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);

    memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
                          TYPE_BCM2835_DMA "-chan15", 0x100);
    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);

    for (n = 0; n < 16; n++) {
        sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
    }
}

static void bcm2835_dma_reset(DeviceState *dev)
{
    BCM2835DMAState *s = BCM2835_DMA(dev);
    int n;

    s->enable = 0xffff;
    s->int_status = 0;
    for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
        bcm2835_dma_chan_reset(&s->chan[n]);
    }
}

static void bcm2835_dma_realize(DeviceState *dev, Error **errp)
{
    BCM2835DMAState *s = BCM2835_DMA(dev);
    Error *err = NULL;
    Object *obj;

    obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
    if (obj == NULL) {
        error_setg(errp, "%s: required dma-mr link not found: %s",
                   __func__, error_get_pretty(err));
        return;
    }

    s->dma_mr = MEMORY_REGION(obj);
    address_space_init(&s->dma_as, s->dma_mr, NULL);

    bcm2835_dma_reset(dev);
}

static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = bcm2835_dma_realize;
    dc->reset = bcm2835_dma_reset;
    dc->vmsd = &vmstate_bcm2835_dma;
}

static TypeInfo bcm2835_dma_info = {
    .name          = TYPE_BCM2835_DMA,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(BCM2835DMAState),
    .class_init    = bcm2835_dma_class_init,
    .instance_init = bcm2835_dma_init,
};

static void bcm2835_dma_register_types(void)
{
    type_register_static(&bcm2835_dma_info);
}

type_init(bcm2835_dma_register_types)
Commit	Line	Data
6717f587 GE	1	/*
	2	* Raspberry Pi emulation (c) 2012 Gregory Estrade
	3	* This code is licensed under the GNU GPLv2 and later.
	4	*/
	5
	6	#include "qemu/osdep.h"
da34e65c	7	#include "qapi/error.h"
6717f587 GE	8	#include "hw/dma/bcm2835_dma.h"
	9
	10	/* DMA CS Control and Status bits */
	11	#define BCM2708_DMA_ACTIVE (1 << 0)
	12	#define BCM2708_DMA_END (1 << 1) /* GE */
	13	#define BCM2708_DMA_INT (1 << 2)
	14	#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
	15	#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
	16	#define BCM2708_DMA_ERR (1 << 8)
	17	#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
	18	#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
	19
	20	/* DMA control block "info" field bits */
	21	#define BCM2708_DMA_INT_EN (1 << 0)
	22	#define BCM2708_DMA_TDMODE (1 << 1)
	23	#define BCM2708_DMA_WAIT_RESP (1 << 3)
	24	#define BCM2708_DMA_D_INC (1 << 4)
	25	#define BCM2708_DMA_D_WIDTH (1 << 5)
	26	#define BCM2708_DMA_D_DREQ (1 << 6)
	27	#define BCM2708_DMA_D_IGNORE (1 << 7)
	28	#define BCM2708_DMA_S_INC (1 << 8)
	29	#define BCM2708_DMA_S_WIDTH (1 << 9)
	30	#define BCM2708_DMA_S_DREQ (1 << 10)
	31	#define BCM2708_DMA_S_IGNORE (1 << 11)
	32
	33	/* Register offsets */
	34	#define BCM2708_DMA_CS 0x00 /* Control and Status */
	35	#define BCM2708_DMA_ADDR 0x04 /* Control block address */
	36	/* the current control block appears in the following registers - read only */
	37	#define BCM2708_DMA_INFO 0x08
	38	#define BCM2708_DMA_SOURCE_AD 0x0c
	39	#define BCM2708_DMA_DEST_AD 0x10
	40	#define BCM2708_DMA_TXFR_LEN 0x14
	41	#define BCM2708_DMA_STRIDE 0x18
	42	#define BCM2708_DMA_NEXTCB 0x1C
	43	#define BCM2708_DMA_DEBUG 0x20
	44
	45	#define BCM2708_DMA_INT_STATUS 0xfe0 /* Interrupt status of each channel */
	46	#define BCM2708_DMA_ENABLE 0xff0 /* Global enable bits for each channel */
	47
	48	#define BCM2708_DMA_CS_RW_MASK 0x30ff0001 /* All RW bits in DMA_CS */
	49
	50	static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
	51	{
	52	BCM2835DMAChan *ch = &s->chan[c];
	53	uint32_t data, xlen, ylen;
	54	int16_t dst_stride, src_stride;
	55
	56	if (!(s->enable & (1 << c))) {
	57	return;
	58	}
	59
	60	while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
	61	/* CB fetch */
	62	ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad);
	63	ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4);
	64	ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8);
	65	ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12);
	66	ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
	67	ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);
	68
	69	if (ch->ti & BCM2708_DMA_TDMODE) {
	70	/* 2D transfer mode */
	71	ylen = (ch->txfr_len >> 16) & 0x3fff;
72	xlen = ch->txfr_len & 0xffff;
73	dst_stride = ch->stride >> 16;
74	src_stride = ch->stride & 0xffff;
75	} else {
76	ylen = 1;
77	xlen = ch->txfr_len;
78	dst_stride = 0;
79	src_stride = 0;
80	}
81
82	while (ylen != 0) {
83	/* Normal transfer mode */
84	while (xlen != 0) {
85	if (ch->ti & BCM2708_DMA_S_IGNORE) {
86	/* Ignore reads */
87	data = 0;
88	} else {
89	data = ldl_le_phys(&s->dma_as, ch->source_ad);
90	}
91	if (ch->ti & BCM2708_DMA_S_INC) {
92	ch->source_ad += 4;
93	}
94
95	if (ch->ti & BCM2708_DMA_D_IGNORE) {
96	/* Ignore writes */
97	} else {
98	stl_le_phys(&s->dma_as, ch->dest_ad, data);
99	}
100	if (ch->ti & BCM2708_DMA_D_INC) {
101	ch->dest_ad += 4;
102	}
103
104	/* update remaining transfer length */
105	xlen -= 4;
106	if (ch->ti & BCM2708_DMA_TDMODE) {
107	ch->txfr_len = (ylen << 16) \| xlen;
108	} else {
109	ch->txfr_len = xlen;
110	}
111	}
112
113	if (--ylen != 0) {
114	ch->source_ad += src_stride;
115	ch->dest_ad += dst_stride;
116	}
117	}
118	ch->cs \|= BCM2708_DMA_END;
119	if (ch->ti & BCM2708_DMA_INT_EN) {
120	ch->cs \|= BCM2708_DMA_INT;
121	s->int_status \|= (1 << c);
122	qemu_set_irq(ch->irq, 1);
123	}
124
125	/* Process next CB */
126	ch->conblk_ad = ch->nextconbk;
127	}
128
129	ch->cs &= ~BCM2708_DMA_ACTIVE;
130	ch->cs \|= BCM2708_DMA_ISPAUSED;
131	}
132
133	static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch)
134	{
135	ch->cs = 0;
136	ch->conblk_ad = 0;
137	}
138
139	static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
140	unsigned size, unsigned c)
141	{
142	BCM2835DMAChan *ch;
143	uint32_t res = 0;
144
145	assert(size == 4);
146	assert(c < BCM2835_DMA_NCHANS);
147
148	ch = &s->chan[c];
149
150	switch (offset) {
151	case BCM2708_DMA_CS:
152	res = ch->cs;
153	break;
154	case BCM2708_DMA_ADDR:
155	res = ch->conblk_ad;
156	break;
157	case BCM2708_DMA_INFO:
158	res = ch->ti;
159	break;
160	case BCM2708_DMA_SOURCE_AD:
161	res = ch->source_ad;
162	break;
163	case BCM2708_DMA_DEST_AD:
164	res = ch->dest_ad;
165	break;
166	case BCM2708_DMA_TXFR_LEN:
167	res = ch->txfr_len;
168	break;
169	case BCM2708_DMA_STRIDE:
170	res = ch->stride;
171	break;
172	case BCM2708_DMA_NEXTCB:
173	res = ch->nextconbk;
174	break;
175	case BCM2708_DMA_DEBUG:
176	res = ch->debug;
177	break;
178	default:
179	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
180	__func__, offset);
181	break;
182	}
183	return res;
184	}
185
186	static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
187	uint64_t value, unsigned size, unsigned c)
188	{
189	BCM2835DMAChan *ch;
190	uint32_t oldcs;
191
192	assert(size == 4);
193	assert(c < BCM2835_DMA_NCHANS);
194
195	ch = &s->chan[c];
196
197	switch (offset) {
198	case BCM2708_DMA_CS:
199	oldcs = ch->cs;
200	if (value & BCM2708_DMA_RESET) {
201	bcm2835_dma_chan_reset(ch);
202	}
203	if (value & BCM2708_DMA_ABORT) {
204	/* abort is a no-op, since we always run to completion */
205	}
206	if (value & BCM2708_DMA_END) {
207	ch->cs &= ~BCM2708_DMA_END;
208	}
209	if (value & BCM2708_DMA_INT) {
210	ch->cs &= ~BCM2708_DMA_INT;
211	s->int_status &= ~(1 << c);
212	qemu_set_irq(ch->irq, 0);
213	}
214	ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
215	ch->cs \|= (value & BCM2708_DMA_CS_RW_MASK);
216	if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
217	bcm2835_dma_update(s, c);
218	}
219	break;
220	case BCM2708_DMA_ADDR:
221	ch->conblk_ad = value;
222	break;
223	case BCM2708_DMA_DEBUG:
224	ch->debug = value;
225	break;
226	default:
227	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
228	__func__, offset);
229	break;
230	}
231	}
232
233	static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
234	{
235	BCM2835DMAState *s = opaque;
236
237	if (offset < 0xf00) {
238	return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
239	} else {
240	switch (offset) {
241	case BCM2708_DMA_INT_STATUS:
242	return s->int_status;
243	case BCM2708_DMA_ENABLE:
244	return s->enable;
245	default:
246	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
247	__func__, offset);
248	return 0;
249	}
250	}
251	}
252
253	static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
254	{
255	return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
256	}
257
258	static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
259	unsigned size)
260	{
261	BCM2835DMAState *s = opaque;
262
263	if (offset < 0xf00) {
264	bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
265	} else {
266	switch (offset) {
267	case BCM2708_DMA_INT_STATUS:
268	break;
269	case BCM2708_DMA_ENABLE:
270	s->enable = (value & 0xffff);
271	break;
272	default:
273	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
274	__func__, offset);
275	}
276	}
277
278	}
279
280	static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
281	unsigned size)
282	{
283	bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
284	}
285
286	static const MemoryRegionOps bcm2835_dma0_ops = {
287	.read = bcm2835_dma0_read,
288	.write = bcm2835_dma0_write,
289	.endianness = DEVICE_NATIVE_ENDIAN,
290	.valid.min_access_size = 4,
291	.valid.max_access_size = 4,
292	};
293
294	static const MemoryRegionOps bcm2835_dma15_ops = {
295	.read = bcm2835_dma15_read,
296	.write = bcm2835_dma15_write,
297	.endianness = DEVICE_NATIVE_ENDIAN,
298	.valid.min_access_size = 4,
299	.valid.max_access_size = 4,
300	};
301
302	static const VMStateDescription vmstate_bcm2835_dma_chan = {
303	.name = TYPE_BCM2835_DMA "-chan",
304	.version_id = 1,
305	.minimum_version_id = 1,
306	.fields = (VMStateField[]) {
307	VMSTATE_UINT32(cs, BCM2835DMAChan),
308	VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
309	VMSTATE_UINT32(ti, BCM2835DMAChan),
310	VMSTATE_UINT32(source_ad, BCM2835DMAChan),
311	VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
312	VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
313	VMSTATE_UINT32(stride, BCM2835DMAChan),
314	VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
315	VMSTATE_UINT32(debug, BCM2835DMAChan),
316	VMSTATE_END_OF_LIST()
317	}
318	};
319
320	static const VMStateDescription vmstate_bcm2835_dma = {
321	.name = TYPE_BCM2835_DMA,
322	.version_id = 1,
323	.minimum_version_id = 1,
324	.fields = (VMStateField[]) {
325	VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
326	vmstate_bcm2835_dma_chan, BCM2835DMAChan),
327	VMSTATE_UINT32(int_status, BCM2835DMAState),
328	VMSTATE_UINT32(enable, BCM2835DMAState),
329	VMSTATE_END_OF_LIST()
330	}
331	};
332
333	static void bcm2835_dma_init(Object *obj)
334	{
335	BCM2835DMAState *s = BCM2835_DMA(obj);
336	int n;
337
338	/* DMA channels 0-14 occupy a contiguous block of IO memory, along
339	* with the global enable and interrupt status bits. Channel 15
340	* has the same register map, but is mapped at a discontiguous
341	* address in a separate IO block.
342	*/
343	memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
344	TYPE_BCM2835_DMA, 0x1000);
345	sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);
346
347	memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
348	TYPE_BCM2835_DMA "-chan15", 0x100);
349	sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);
350
351	for (n = 0; n < 16; n++) {
352	sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
353	}
354	}
355
356	static void bcm2835_dma_reset(DeviceState *dev)
357	{
358	BCM2835DMAState *s = BCM2835_DMA(dev);
359	int n;
360
361	s->enable = 0xffff;
362	s->int_status = 0;
363	for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
364	bcm2835_dma_chan_reset(&s->chan[n]);
365	}
366	}
367
368	static void bcm2835_dma_realize(DeviceState dev, Error *errp)
369	{
370	BCM2835DMAState *s = BCM2835_DMA(dev);
371	Error *err = NULL;
372	Object *obj;
373
374	obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
375	if (obj == NULL) {
376	error_setg(errp, "%s: required dma-mr link not found: %s",
377	__func__, error_get_pretty(err));
378	return;
379	}
380
381	s->dma_mr = MEMORY_REGION(obj);
382	address_space_init(&s->dma_as, s->dma_mr, NULL);
383
384	bcm2835_dma_reset(dev);
385	}
386
387	static void bcm2835_dma_class_init(ObjectClass klass, void data)
388	{
389	DeviceClass *dc = DEVICE_CLASS(klass);
390
391	dc->realize = bcm2835_dma_realize;
392	dc->reset = bcm2835_dma_reset;
393	dc->vmsd = &vmstate_bcm2835_dma;
394	}
395
396	static TypeInfo bcm2835_dma_info = {
397	.name = TYPE_BCM2835_DMA,
398	.parent = TYPE_SYS_BUS_DEVICE,
399	.instance_size = sizeof(BCM2835DMAState),
400	.class_init = bcm2835_dma_class_init,
401	.instance_init = bcm2835_dma_init,
402	};
403
404	static void bcm2835_dma_register_types(void)
405	{
406	type_register_static(&bcm2835_dma_info);
407	}
408
409	type_init(bcm2835_dma_register_types)