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1ea34899 GX |
1 | /* |
2 | * DMA device simulation in PKUnity SoC | |
3 | * | |
4 | * Copyright (C) 2010-2012 Guan Xuetao | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation, or any later version. | |
9 | * See the COPYING file in the top-level directory. | |
10 | */ | |
0b8fa32f | 11 | |
5af98cc5 | 12 | #include "qemu/osdep.h" |
83c9f4ca PB |
13 | #include "hw/hw.h" |
14 | #include "hw/sysbus.h" | |
1ea34899 GX |
15 | |
16 | #undef DEBUG_PUV3 | |
0d09e41a | 17 | #include "hw/unicore32/puv3.h" |
0b8fa32f | 18 | #include "qemu/module.h" |
1ea34899 GX |
19 | |
20 | #define PUV3_DMA_CH_NR (6) | |
21 | #define PUV3_DMA_CH_MASK (0xff) | |
22 | #define PUV3_DMA_CH(offset) ((offset) >> 8) | |
23 | ||
6df7cdee AF |
24 | #define TYPE_PUV3_DMA "puv3_dma" |
25 | #define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA) | |
26 | ||
27 | typedef struct PUV3DMAState { | |
28 | SysBusDevice parent_obj; | |
29 | ||
1ea34899 GX |
30 | MemoryRegion iomem; |
31 | uint32_t reg_CFG[PUV3_DMA_CH_NR]; | |
32 | } PUV3DMAState; | |
33 | ||
a8170e5e | 34 | static uint64_t puv3_dma_read(void *opaque, hwaddr offset, |
1ea34899 GX |
35 | unsigned size) |
36 | { | |
37 | PUV3DMAState *s = opaque; | |
38 | uint32_t ret = 0; | |
39 | ||
40 | assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR); | |
41 | ||
42 | switch (offset & PUV3_DMA_CH_MASK) { | |
43 | case 0x10: | |
44 | ret = s->reg_CFG[PUV3_DMA_CH(offset)]; | |
45 | break; | |
46 | default: | |
47 | DPRINTF("Bad offset 0x%x\n", offset); | |
48 | } | |
49 | DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); | |
50 | ||
51 | return ret; | |
52 | } | |
53 | ||
a8170e5e | 54 | static void puv3_dma_write(void *opaque, hwaddr offset, |
1ea34899 GX |
55 | uint64_t value, unsigned size) |
56 | { | |
57 | PUV3DMAState *s = opaque; | |
58 | ||
59 | assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR); | |
60 | ||
61 | switch (offset & PUV3_DMA_CH_MASK) { | |
62 | case 0x10: | |
63 | s->reg_CFG[PUV3_DMA_CH(offset)] = value; | |
64 | break; | |
65 | default: | |
66 | DPRINTF("Bad offset 0x%x\n", offset); | |
67 | } | |
68 | DPRINTF("offset 0x%x, value 0x%x\n", offset, value); | |
69 | } | |
70 | ||
71 | static const MemoryRegionOps puv3_dma_ops = { | |
72 | .read = puv3_dma_read, | |
73 | .write = puv3_dma_write, | |
74 | .impl = { | |
75 | .min_access_size = 4, | |
76 | .max_access_size = 4, | |
77 | }, | |
78 | .endianness = DEVICE_NATIVE_ENDIAN, | |
79 | }; | |
80 | ||
8ba7f726 | 81 | static void puv3_dma_realize(DeviceState *dev, Error **errp) |
1ea34899 | 82 | { |
6df7cdee | 83 | PUV3DMAState *s = PUV3_DMA(dev); |
1ea34899 GX |
84 | int i; |
85 | ||
86 | for (i = 0; i < PUV3_DMA_CH_NR; i++) { | |
87 | s->reg_CFG[i] = 0x0; | |
88 | } | |
89 | ||
3eadad55 | 90 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma", |
1ea34899 | 91 | PUV3_REGS_OFFSET); |
8ba7f726 | 92 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); |
1ea34899 GX |
93 | } |
94 | ||
95 | static void puv3_dma_class_init(ObjectClass *klass, void *data) | |
96 | { | |
8ba7f726 | 97 | DeviceClass *dc = DEVICE_CLASS(klass); |
1ea34899 | 98 | |
8ba7f726 | 99 | dc->realize = puv3_dma_realize; |
1ea34899 GX |
100 | } |
101 | ||
102 | static const TypeInfo puv3_dma_info = { | |
6df7cdee | 103 | .name = TYPE_PUV3_DMA, |
1ea34899 GX |
104 | .parent = TYPE_SYS_BUS_DEVICE, |
105 | .instance_size = sizeof(PUV3DMAState), | |
106 | .class_init = puv3_dma_class_init, | |
107 | }; | |
108 | ||
109 | static void puv3_dma_register_type(void) | |
110 | { | |
111 | type_register_static(&puv3_dma_info); | |
112 | } | |
113 | ||
114 | type_init(puv3_dma_register_type) |