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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
d471bf3e | 26 | #include "qemu/units.h" |
549e984e | 27 | #include "hw/i386/x86.h" |
0d09e41a PB |
28 | #include "hw/i386/pc.h" |
29 | #include "hw/char/serial.h" | |
bb3d5ea8 | 30 | #include "hw/char/parallel.h" |
0d09e41a | 31 | #include "hw/i386/apic.h" |
54a40293 | 32 | #include "hw/i386/topology.h" |
87abaa5d | 33 | #include "hw/i386/fw_cfg.h" |
54a40293 | 34 | #include "sysemu/cpus.h" |
0d09e41a | 35 | #include "hw/block/fdc.h" |
83c9f4ca PB |
36 | #include "hw/ide.h" |
37 | #include "hw/pci/pci.h" | |
2118196b | 38 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
39 | #include "hw/nvram/fw_cfg.h" |
40 | #include "hw/timer/hpet.h" | |
a2eb5c0c | 41 | #include "hw/firmware/smbios.h" |
83c9f4ca | 42 | #include "hw/loader.h" |
ca20cf32 | 43 | #include "elf.h" |
d6454270 | 44 | #include "migration/vmstate.h" |
47b43a1f | 45 | #include "multiboot.h" |
bcdb9064 | 46 | #include "hw/rtc/mc146818rtc.h" |
852c27e2 | 47 | #include "hw/intc/i8259.h" |
55f613ac | 48 | #include "hw/dma/i8257.h" |
0d09e41a | 49 | #include "hw/timer/i8254.h" |
47973a2d | 50 | #include "hw/input/i8042.h" |
64552b6b | 51 | #include "hw/irq.h" |
0d09e41a | 52 | #include "hw/audio/pcspk.h" |
83c9f4ca PB |
53 | #include "hw/pci/msi.h" |
54 | #include "hw/sysbus.h" | |
9c17d615 | 55 | #include "sysemu/sysemu.h" |
14a48c1d | 56 | #include "sysemu/tcg.h" |
e35704ba | 57 | #include "sysemu/numa.h" |
9c17d615 | 58 | #include "sysemu/kvm.h" |
b1c12027 | 59 | #include "sysemu/qtest.h" |
71e8a915 | 60 | #include "sysemu/reset.h" |
54d31236 | 61 | #include "sysemu/runstate.h" |
1d31f66b | 62 | #include "kvm_i386.h" |
0d09e41a | 63 | #include "hw/xen/xen.h" |
ab969087 | 64 | #include "hw/xen/start_info.h" |
a19cbfb3 | 65 | #include "ui/qemu-spice.h" |
022c62cb PB |
66 | #include "exec/memory.h" |
67 | #include "exec/address-spaces.h" | |
9c17d615 | 68 | #include "sysemu/arch_init.h" |
1de7afc9 | 69 | #include "qemu/bitmap.h" |
0c764a9d | 70 | #include "qemu/config-file.h" |
d49b6836 | 71 | #include "qemu/error-report.h" |
922a01a0 | 72 | #include "qemu/option.h" |
133ef074 | 73 | #include "qemu/cutils.h" |
0445259b | 74 | #include "hw/acpi/acpi.h" |
5ff020b7 | 75 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 76 | #include "hw/boards.h" |
72c194f7 | 77 | #include "acpi-build.h" |
95bee274 | 78 | #include "hw/mem/pc-dimm.h" |
4b997690 | 79 | #include "hw/mem/nvdimm.h" |
e688df6b | 80 | #include "qapi/error.h" |
9af23989 | 81 | #include "qapi/qapi-visit-common.h" |
bf1e8939 | 82 | #include "qapi/visitor.h" |
2e5b09fd | 83 | #include "hw/core/cpu.h" |
a310e653 | 84 | #include "hw/usb.h" |
60c5e104 | 85 | #include "hw/i386/intel_iommu.h" |
489983d6 | 86 | #include "hw/net/ne2000-isa.h" |
06e0259a | 87 | #include "standard-headers/asm-x86/bootparam.h" |
a0a49813 DH |
88 | #include "hw/virtio/virtio-pmem-pci.h" |
89 | #include "hw/mem/memory-device.h" | |
6f479566 LX |
90 | #include "sysemu/replay.h" |
91 | #include "qapi/qmp/qerror.h" | |
97fd1ea8 | 92 | #include "config-devices.h" |
d6d059ca | 93 | #include "e820_memory_layout.h" |
149c50ca | 94 | #include "fw_cfg.h" |
4ca8dabd | 95 | #include "trace.h" |
471fd342 | 96 | |
f404220e IM |
97 | GlobalProperty pc_compat_4_2[] = { |
98 | { "mch", "smbase-smram", "off" }, | |
99 | }; | |
3eb74d20 CH |
100 | const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); |
101 | ||
9aec2e52 CH |
102 | GlobalProperty pc_compat_4_1[] = {}; |
103 | const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); | |
104 | ||
9bf2650b CH |
105 | GlobalProperty pc_compat_4_0[] = {}; |
106 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
107 | ||
abd93cc7 | 108 | GlobalProperty pc_compat_3_1[] = { |
6c36bddf | 109 | { "intel-iommu", "dma-drain", "off" }, |
483c6ad4 BP |
110 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
111 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
9fe8b7be VK |
112 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, |
113 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
483c6ad4 | 114 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, |
9fe8b7be VK |
115 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, |
116 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
117 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
118 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
119 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
120 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
ecb85fe4 PB |
121 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, |
122 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
123 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
124 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
125 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
126 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
127 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
b0a19803 | 128 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, |
f24c3a79 | 129 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, |
abd93cc7 MAL |
130 | }; |
131 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
132 | ||
ddb3235d | 133 | GlobalProperty pc_compat_3_0[] = { |
6c36bddf EH |
134 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, |
135 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
136 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
ddb3235d MAL |
137 | }; |
138 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
139 | ||
0d47310b | 140 | GlobalProperty pc_compat_2_12[] = { |
6c36bddf EH |
141 | { TYPE_X86_CPU, "legacy-cache", "on" }, |
142 | { TYPE_X86_CPU, "topoext", "off" }, | |
143 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
144 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
0d47310b MAL |
145 | }; |
146 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
147 | ||
43df70a9 | 148 | GlobalProperty pc_compat_2_11[] = { |
6c36bddf EH |
149 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, |
150 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
43df70a9 MAL |
151 | }; |
152 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
153 | ||
503224f4 | 154 | GlobalProperty pc_compat_2_10[] = { |
6c36bddf EH |
155 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, |
156 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
157 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
503224f4 MAL |
158 | }; |
159 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
160 | ||
3e803152 | 161 | GlobalProperty pc_compat_2_9[] = { |
6c36bddf | 162 | { "mch", "extended-tseg-mbytes", "0" }, |
3e803152 MAL |
163 | }; |
164 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
165 | ||
edc24ccd | 166 | GlobalProperty pc_compat_2_8[] = { |
6c36bddf EH |
167 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, |
168 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
169 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
170 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
171 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
edc24ccd MAL |
172 | }; |
173 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
174 | ||
5a995064 | 175 | GlobalProperty pc_compat_2_7[] = { |
6c36bddf EH |
176 | { TYPE_X86_CPU, "l3-cache", "off" }, |
177 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
178 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
179 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
180 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
181 | { "isa-pcspk", "migrate", "off" }, | |
5a995064 MAL |
182 | }; |
183 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
184 | ||
ff8f261f | 185 | GlobalProperty pc_compat_2_6[] = { |
6c36bddf EH |
186 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, |
187 | { "vmxnet3", "romfile", "" }, | |
188 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
189 | { "apic-common", "legacy-instance-id", "on", } | |
ff8f261f MAL |
190 | }; |
191 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
192 | ||
fe759610 MAL |
193 | GlobalProperty pc_compat_2_5[] = {}; |
194 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
195 | ||
2f99b9c2 MAL |
196 | GlobalProperty pc_compat_2_4[] = { |
197 | PC_CPU_MODEL_IDS("2.4.0") | |
6c36bddf EH |
198 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, |
199 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
200 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
201 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
202 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
203 | { TYPE_X86_CPU, "check", "off" }, | |
204 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
205 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
206 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
207 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
208 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
209 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
210 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
211 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
2f99b9c2 MAL |
212 | }; |
213 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
214 | ||
8995dd90 MAL |
215 | GlobalProperty pc_compat_2_3[] = { |
216 | PC_CPU_MODEL_IDS("2.3.0") | |
6c36bddf EH |
217 | { TYPE_X86_CPU, "arat", "off" }, |
218 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
219 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
220 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
221 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
222 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
223 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
224 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
225 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
226 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
227 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
228 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
229 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
230 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
231 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
232 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
233 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
234 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
235 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
236 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
8995dd90 MAL |
237 | }; |
238 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
239 | ||
1c30044e MAL |
240 | GlobalProperty pc_compat_2_2[] = { |
241 | PC_CPU_MODEL_IDS("2.2.0") | |
6c36bddf EH |
242 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, |
243 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
244 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
245 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
246 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
247 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
248 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
249 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
250 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
251 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
252 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
253 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
254 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
255 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
256 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
257 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
258 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
259 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
1c30044e MAL |
260 | }; |
261 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
262 | ||
c4fc5695 MAL |
263 | GlobalProperty pc_compat_2_1[] = { |
264 | PC_CPU_MODEL_IDS("2.1.0") | |
6c36bddf EH |
265 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, |
266 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
c4fc5695 MAL |
267 | }; |
268 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
269 | ||
a310e653 MAL |
270 | GlobalProperty pc_compat_2_0[] = { |
271 | PC_CPU_MODEL_IDS("2.0.0") | |
6c36bddf EH |
272 | { "virtio-scsi-pci", "any_layout", "off" }, |
273 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
274 | { "apic", "version", "0x11" }, | |
275 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
276 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
277 | { "pci-serial", "prog_if", "0" }, | |
278 | { "pci-serial-2x", "prog_if", "0" }, | |
279 | { "pci-serial-4x", "prog_if", "0" }, | |
280 | { "virtio-net-pci", "guest_announce", "off" }, | |
281 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
282 | { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, | |
283 | { "ioh3420", COMPAT_PROP_PCP, "off" }, | |
a310e653 MAL |
284 | }; |
285 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
286 | ||
287 | GlobalProperty pc_compat_1_7[] = { | |
288 | PC_CPU_MODEL_IDS("1.7.0") | |
6c36bddf EH |
289 | { TYPE_USB_DEVICE, "msos-desc", "no" }, |
290 | { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, | |
291 | { "hpet", HPET_INTCAP, "4" }, | |
a310e653 MAL |
292 | }; |
293 | const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); | |
294 | ||
295 | GlobalProperty pc_compat_1_6[] = { | |
296 | PC_CPU_MODEL_IDS("1.6.0") | |
6c36bddf EH |
297 | { "e1000", "mitigation", "off" }, |
298 | { "qemu64-" TYPE_X86_CPU, "model", "2" }, | |
299 | { "qemu32-" TYPE_X86_CPU, "model", "3" }, | |
300 | { "i440FX-pcihost", "short_root_bus", "1" }, | |
301 | { "q35-pcihost", "short_root_bus", "1" }, | |
a310e653 MAL |
302 | }; |
303 | const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); | |
304 | ||
305 | GlobalProperty pc_compat_1_5[] = { | |
306 | PC_CPU_MODEL_IDS("1.5.0") | |
6c36bddf EH |
307 | { "Conroe-" TYPE_X86_CPU, "model", "2" }, |
308 | { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, | |
309 | { "Penryn-" TYPE_X86_CPU, "model", "2" }, | |
310 | { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, | |
311 | { "Nehalem-" TYPE_X86_CPU, "model", "2" }, | |
312 | { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, | |
313 | { "virtio-net-pci", "any_layout", "off" }, | |
314 | { TYPE_X86_CPU, "pmu", "on" }, | |
315 | { "i440FX-pcihost", "short_root_bus", "0" }, | |
316 | { "q35-pcihost", "short_root_bus", "0" }, | |
a310e653 MAL |
317 | }; |
318 | const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); | |
319 | ||
320 | GlobalProperty pc_compat_1_4[] = { | |
321 | PC_CPU_MODEL_IDS("1.4.0") | |
6c36bddf EH |
322 | { "scsi-hd", "discard_granularity", "0" }, |
323 | { "scsi-cd", "discard_granularity", "0" }, | |
324 | { "scsi-disk", "discard_granularity", "0" }, | |
325 | { "ide-hd", "discard_granularity", "0" }, | |
326 | { "ide-cd", "discard_granularity", "0" }, | |
327 | { "ide-drive", "discard_granularity", "0" }, | |
328 | { "virtio-blk-pci", "discard_granularity", "0" }, | |
329 | /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ | |
330 | { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, | |
331 | { "virtio-net-pci", "ctrl_guest_offloads", "off" }, | |
332 | { "e1000", "romfile", "pxe-e1000.rom" }, | |
333 | { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, | |
334 | { "pcnet", "romfile", "pxe-pcnet.rom" }, | |
335 | { "rtl8139", "romfile", "pxe-rtl8139.rom" }, | |
336 | { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, | |
337 | { "486-" TYPE_X86_CPU, "model", "0" }, | |
338 | { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, | |
339 | { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, | |
a310e653 MAL |
340 | }; |
341 | const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); | |
342 | ||
417258f1 PMD |
343 | GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) |
344 | { | |
345 | GSIState *s; | |
346 | ||
347 | s = g_new0(GSIState, 1); | |
348 | if (kvm_ioapic_in_kernel()) { | |
349 | kvm_pc_setup_irq_routing(pci_enabled); | |
417258f1 | 350 | } |
64c033ba | 351 | *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); |
417258f1 PMD |
352 | |
353 | return s; | |
354 | } | |
355 | ||
258711c6 JG |
356 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
357 | unsigned size) | |
80cabfad FB |
358 | { |
359 | } | |
360 | ||
c02e1eac JG |
361 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
362 | { | |
a6fc23e5 | 363 | return 0xffffffffffffffffULL; |
c02e1eac JG |
364 | } |
365 | ||
f929aad6 | 366 | /* MSDOS compatibility mode FPU exception support */ |
258711c6 JG |
367 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
368 | unsigned size) | |
f929aad6 | 369 | { |
6f529b75 | 370 | if (tcg_enabled()) { |
bf13bfab | 371 | cpu_set_ignne(); |
6f529b75 | 372 | } |
f929aad6 FB |
373 | } |
374 | ||
c02e1eac JG |
375 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
376 | { | |
a6fc23e5 | 377 | return 0xffffffffffffffffULL; |
c02e1eac JG |
378 | } |
379 | ||
b0a21b53 FB |
380 | /* PC cmos mappings */ |
381 | ||
80cabfad FB |
382 | #define REG_EQUIPMENT_BYTE 0x14 |
383 | ||
bda05509 | 384 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
385 | { |
386 | int val; | |
387 | ||
388 | switch (fd0) { | |
2da44dd0 | 389 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
390 | /* 1.44 Mb 3"5 drive */ |
391 | val = 4; | |
392 | break; | |
2da44dd0 | 393 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
394 | /* 2.88 Mb 3"5 drive */ |
395 | val = 5; | |
396 | break; | |
2da44dd0 | 397 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
398 | /* 1.2 Mb 5"5 drive */ |
399 | val = 2; | |
400 | break; | |
2da44dd0 | 401 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
402 | default: |
403 | val = 0; | |
404 | break; | |
405 | } | |
406 | return val; | |
407 | } | |
408 | ||
9139046c MA |
409 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
410 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 411 | { |
ba6c2377 FB |
412 | rtc_set_memory(s, type_ofs, 47); |
413 | rtc_set_memory(s, info_ofs, cylinders); | |
414 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
415 | rtc_set_memory(s, info_ofs + 2, heads); | |
416 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
417 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
418 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
419 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
420 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
421 | rtc_set_memory(s, info_ofs + 8, sectors); | |
422 | } | |
423 | ||
6ac0e82d AZ |
424 | /* convert boot_device letter to something recognizable by the bios */ |
425 | static int boot_device2nibble(char boot_device) | |
426 | { | |
427 | switch(boot_device) { | |
428 | case 'a': | |
429 | case 'b': | |
430 | return 0x01; /* floppy boot */ | |
431 | case 'c': | |
432 | return 0x02; /* hard drive boot */ | |
433 | case 'd': | |
434 | return 0x03; /* CD-ROM boot */ | |
435 | case 'n': | |
436 | return 0x04; /* Network boot */ | |
437 | } | |
438 | return 0; | |
439 | } | |
440 | ||
ddcd5531 | 441 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
442 | { |
443 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
444 | int nbds, bds[3] = { 0, }; |
445 | int i; | |
446 | ||
447 | nbds = strlen(boot_device); | |
448 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
449 | error_setg(errp, "Too many boot devices for PC"); |
450 | return; | |
0ecdffbb AJ |
451 | } |
452 | for (i = 0; i < nbds; i++) { | |
453 | bds[i] = boot_device2nibble(boot_device[i]); | |
454 | if (bds[i] == 0) { | |
ddcd5531 GA |
455 | error_setg(errp, "Invalid boot device for PC: '%c'", |
456 | boot_device[i]); | |
457 | return; | |
0ecdffbb AJ |
458 | } |
459 | } | |
460 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 461 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
462 | } |
463 | ||
ddcd5531 | 464 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 465 | { |
ddcd5531 | 466 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
467 | } |
468 | ||
7444ca4e LE |
469 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
470 | { | |
471 | int val, nb, i; | |
2da44dd0 JS |
472 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
473 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
474 | |
475 | /* floppy type */ | |
476 | if (floppy) { | |
477 | for (i = 0; i < 2; i++) { | |
478 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
479 | } | |
480 | } | |
481 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
482 | cmos_get_fd_drive_type(fd_type[1]); | |
483 | rtc_set_memory(rtc_state, 0x10, val); | |
484 | ||
485 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
486 | nb = 0; | |
2da44dd0 | 487 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
488 | nb++; |
489 | } | |
2da44dd0 | 490 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
491 | nb++; |
492 | } | |
493 | switch (nb) { | |
494 | case 0: | |
495 | break; | |
496 | case 1: | |
497 | val |= 0x01; /* 1 drive, ready for boot */ | |
498 | break; | |
499 | case 2: | |
500 | val |= 0x41; /* 2 drives, ready for boot */ | |
501 | break; | |
502 | } | |
503 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
504 | } | |
505 | ||
c0897e0c MA |
506 | typedef struct pc_cmos_init_late_arg { |
507 | ISADevice *rtc_state; | |
9139046c | 508 | BusState *idebus[2]; |
c0897e0c MA |
509 | } pc_cmos_init_late_arg; |
510 | ||
b86f4613 LE |
511 | typedef struct check_fdc_state { |
512 | ISADevice *floppy; | |
513 | bool multiple; | |
514 | } CheckFdcState; | |
515 | ||
516 | static int check_fdc(Object *obj, void *opaque) | |
517 | { | |
518 | CheckFdcState *state = opaque; | |
519 | Object *fdc; | |
520 | uint32_t iobase; | |
521 | Error *local_err = NULL; | |
522 | ||
523 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
524 | if (!fdc) { | |
525 | return 0; | |
526 | } | |
527 | ||
1ea1572a | 528 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
529 | if (local_err || iobase != 0x3f0) { |
530 | error_free(local_err); | |
531 | return 0; | |
532 | } | |
533 | ||
534 | if (state->floppy) { | |
535 | state->multiple = true; | |
536 | } else { | |
537 | state->floppy = ISA_DEVICE(obj); | |
538 | } | |
539 | return 0; | |
540 | } | |
541 | ||
542 | static const char * const fdc_container_path[] = { | |
543 | "/unattached", "/peripheral", "/peripheral-anon" | |
544 | }; | |
545 | ||
424e4a87 RK |
546 | /* |
547 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
548 | * and ACPI objects. | |
549 | */ | |
550 | ISADevice *pc_find_fdc0(void) | |
551 | { | |
552 | int i; | |
553 | Object *container; | |
554 | CheckFdcState state = { 0 }; | |
555 | ||
556 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
557 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
558 | object_child_foreach(container, check_fdc, &state); | |
559 | } | |
560 | ||
561 | if (state.multiple) { | |
3dc6f869 AF |
562 | warn_report("multiple floppy disk controllers with " |
563 | "iobase=0x3f0 have been found"); | |
433672b0 | 564 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 565 | "your intent"); |
424e4a87 RK |
566 | } |
567 | ||
568 | return state.floppy; | |
569 | } | |
570 | ||
c0897e0c MA |
571 | static void pc_cmos_init_late(void *opaque) |
572 | { | |
573 | pc_cmos_init_late_arg *arg = opaque; | |
574 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
575 | int16_t cylinders; |
576 | int8_t heads, sectors; | |
c0897e0c | 577 | int val; |
2adc99b2 | 578 | int i, trans; |
c0897e0c | 579 | |
9139046c | 580 | val = 0; |
272f0428 CP |
581 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
582 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
583 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
584 | val |= 0xf0; | |
585 | } | |
272f0428 CP |
586 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
587 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
588 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
589 | val |= 0x0f; | |
590 | } | |
591 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
592 | |
593 | val = 0; | |
594 | for (i = 0; i < 4; i++) { | |
9139046c MA |
595 | /* NOTE: ide_get_geometry() returns the physical |
596 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
597 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
598 | geometry can be different if a translation is done. */ | |
272f0428 CP |
599 | if (arg->idebus[i / 2] && |
600 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 601 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
602 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
603 | assert((trans & ~3) == 0); | |
604 | val |= trans << (i * 2); | |
c0897e0c MA |
605 | } |
606 | } | |
607 | rtc_set_memory(s, 0x39, val); | |
608 | ||
424e4a87 | 609 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 610 | |
c0897e0c MA |
611 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
612 | } | |
613 | ||
23d30407 | 614 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 615 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 616 | ISADevice *s) |
80cabfad | 617 | { |
7444ca4e | 618 | int val; |
c0897e0c | 619 | static pc_cmos_init_late_arg arg; |
f0bb276b | 620 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b0a21b53 | 621 | |
b0a21b53 | 622 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
623 | |
624 | /* memory size */ | |
e89001f7 | 625 | /* base memory (first MiB) */ |
f0bb276b | 626 | val = MIN(x86ms->below_4g_mem_size / KiB, 640); |
333190eb FB |
627 | rtc_set_memory(s, 0x15, val); |
628 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 629 | /* extended memory (next 64MiB) */ |
f0bb276b PB |
630 | if (x86ms->below_4g_mem_size > 1 * MiB) { |
631 | val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; | |
e89001f7 MA |
632 | } else { |
633 | val = 0; | |
634 | } | |
80cabfad FB |
635 | if (val > 65535) |
636 | val = 65535; | |
b0a21b53 FB |
637 | rtc_set_memory(s, 0x17, val); |
638 | rtc_set_memory(s, 0x18, val >> 8); | |
639 | rtc_set_memory(s, 0x30, val); | |
640 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 641 | /* memory between 16MiB and 4GiB */ |
f0bb276b PB |
642 | if (x86ms->below_4g_mem_size > 16 * MiB) { |
643 | val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
e89001f7 | 644 | } else { |
9da98861 | 645 | val = 0; |
e89001f7 | 646 | } |
80cabfad FB |
647 | if (val > 65535) |
648 | val = 65535; | |
b0a21b53 FB |
649 | rtc_set_memory(s, 0x34, val); |
650 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 651 | /* memory above 4GiB */ |
f0bb276b | 652 | val = x86ms->above_4g_mem_size / 65536; |
e89001f7 MA |
653 | rtc_set_memory(s, 0x5b, val); |
654 | rtc_set_memory(s, 0x5c, val >> 8); | |
655 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 656 | |
23d30407 | 657 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 658 | TYPE_ISA_DEVICE, |
f0bb276b | 659 | (Object **)&x86ms->rtc, |
2d996150 | 660 | object_property_allow_set_link, |
265b578c | 661 | OBJ_PROP_LINK_STRONG, &error_abort); |
23d30407 | 662 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 663 | "rtc_state", &error_abort); |
298e01b6 | 664 | |
007b0657 | 665 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 666 | |
b0a21b53 | 667 | val = 0; |
b0a21b53 FB |
668 | val |= 0x02; /* FPU is there */ |
669 | val |= 0x04; /* PS/2 mouse installed */ | |
670 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
671 | ||
b86f4613 | 672 | /* hard drives and FDC */ |
c0897e0c | 673 | arg.rtc_state = s; |
9139046c MA |
674 | arg.idebus[0] = idebus0; |
675 | arg.idebus[1] = idebus1; | |
c0897e0c | 676 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
677 | } |
678 | ||
956a3e6b | 679 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 680 | { |
cc36a7a2 | 681 | X86CPU *cpu = opaque; |
e1a23744 | 682 | |
956a3e6b | 683 | /* XXX: send to all CPUs ? */ |
4b78a802 | 684 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 685 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
686 | } |
687 | ||
b41a2cd1 FB |
688 | #define NE2000_NB_MAX 6 |
689 | ||
675d6f82 BS |
690 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
691 | 0x280, 0x380 }; | |
692 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 693 | |
48a18b3c | 694 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
695 | { |
696 | static int nb_ne2k = 0; | |
697 | ||
698 | if (nb_ne2k == NE2000_NB_MAX) | |
699 | return; | |
48a18b3c | 700 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 701 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
702 | nb_ne2k++; |
703 | } | |
704 | ||
845773ab | 705 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 706 | { |
c3affe56 | 707 | X86CPU *cpu = opaque; |
53b67b30 BS |
708 | |
709 | if (level) { | |
c3affe56 | 710 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
711 | } |
712 | } | |
713 | ||
6f479566 LX |
714 | /* |
715 | * This function is very similar to smp_parse() | |
716 | * in hw/core/machine.c but includes CPU die support. | |
717 | */ | |
718 | void pc_smp_parse(MachineState *ms, QemuOpts *opts) | |
719 | { | |
f0bb276b | 720 | X86MachineState *x86ms = X86_MACHINE(ms); |
1b458422 | 721 | |
6f479566 LX |
722 | if (opts) { |
723 | unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); | |
724 | unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); | |
1b458422 | 725 | unsigned dies = qemu_opt_get_number(opts, "dies", 1); |
6f479566 LX |
726 | unsigned cores = qemu_opt_get_number(opts, "cores", 0); |
727 | unsigned threads = qemu_opt_get_number(opts, "threads", 0); | |
728 | ||
729 | /* compute missing values, prefer sockets over cores over threads */ | |
730 | if (cpus == 0 || sockets == 0) { | |
731 | cores = cores > 0 ? cores : 1; | |
732 | threads = threads > 0 ? threads : 1; | |
733 | if (cpus == 0) { | |
734 | sockets = sockets > 0 ? sockets : 1; | |
1b458422 | 735 | cpus = cores * threads * dies * sockets; |
6f479566 LX |
736 | } else { |
737 | ms->smp.max_cpus = | |
738 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
1b458422 | 739 | sockets = ms->smp.max_cpus / (cores * threads * dies); |
6f479566 LX |
740 | } |
741 | } else if (cores == 0) { | |
742 | threads = threads > 0 ? threads : 1; | |
1b458422 | 743 | cores = cpus / (sockets * dies * threads); |
6f479566 LX |
744 | cores = cores > 0 ? cores : 1; |
745 | } else if (threads == 0) { | |
1b458422 | 746 | threads = cpus / (cores * dies * sockets); |
6f479566 | 747 | threads = threads > 0 ? threads : 1; |
1b458422 | 748 | } else if (sockets * dies * cores * threads < cpus) { |
6f479566 | 749 | error_report("cpu topology: " |
1b458422 | 750 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " |
6f479566 | 751 | "smp_cpus (%u)", |
1b458422 | 752 | sockets, dies, cores, threads, cpus); |
6f479566 LX |
753 | exit(1); |
754 | } | |
755 | ||
756 | ms->smp.max_cpus = | |
757 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
758 | ||
759 | if (ms->smp.max_cpus < cpus) { | |
760 | error_report("maxcpus must be equal to or greater than smp"); | |
761 | exit(1); | |
762 | } | |
763 | ||
1b458422 | 764 | if (sockets * dies * cores * threads > ms->smp.max_cpus) { |
6f479566 | 765 | error_report("cpu topology: " |
1b458422 | 766 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " |
6f479566 | 767 | "maxcpus (%u)", |
1b458422 | 768 | sockets, dies, cores, threads, |
6f479566 LX |
769 | ms->smp.max_cpus); |
770 | exit(1); | |
771 | } | |
772 | ||
1b458422 | 773 | if (sockets * dies * cores * threads != ms->smp.max_cpus) { |
6f479566 | 774 | warn_report("Invalid CPU topology deprecated: " |
1b458422 | 775 | "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " |
6f479566 | 776 | "!= maxcpus (%u)", |
1b458422 | 777 | sockets, dies, cores, threads, |
6f479566 LX |
778 | ms->smp.max_cpus); |
779 | } | |
780 | ||
781 | ms->smp.cpus = cpus; | |
782 | ms->smp.cores = cores; | |
783 | ms->smp.threads = threads; | |
f0bb276b | 784 | x86ms->smp_dies = dies; |
6f479566 LX |
785 | } |
786 | ||
787 | if (ms->smp.cpus > 1) { | |
788 | Error *blocker = NULL; | |
789 | error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); | |
790 | replay_add_blocker(blocker); | |
791 | } | |
792 | } | |
793 | ||
a0628599 | 794 | void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) |
c649983b | 795 | { |
703a548a SL |
796 | X86MachineState *x86ms = X86_MACHINE(ms); |
797 | int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); | |
0e3bd562 | 798 | Error *local_err = NULL; |
c649983b | 799 | |
8de433cb IM |
800 | if (id < 0) { |
801 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
802 | return; | |
803 | } | |
804 | ||
5ff020b7 EH |
805 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
806 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
807 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
808 | id, apic_id); | |
809 | return; | |
810 | } | |
811 | ||
703a548a SL |
812 | |
813 | x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); | |
0e3bd562 AF |
814 | if (local_err) { |
815 | error_propagate(errp, local_err); | |
816 | return; | |
817 | } | |
c649983b IM |
818 | } |
819 | ||
e3cadac0 IM |
820 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) |
821 | { | |
822 | if (cpus_count > 0xff) { | |
823 | /* If the number of CPUs can't be represented in 8 bits, the | |
824 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
825 | * to make old BIOSes fail more predictably. | |
826 | */ | |
827 | rtc_set_memory(rtc, 0x5f, 0); | |
828 | } else { | |
829 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
830 | } | |
831 | } | |
832 | ||
3459a625 | 833 | static |
9ebeed0c | 834 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 835 | { |
9ebeed0c EH |
836 | PCMachineState *pcms = container_of(notifier, |
837 | PCMachineState, machine_done); | |
f0bb276b | 838 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9ebeed0c | 839 | PCIBus *bus = pcms->bus; |
2118196b | 840 | |
ba157b69 | 841 | /* set the number of CPUs */ |
f0bb276b | 842 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
ba157b69 | 843 | |
2118196b MA |
844 | if (bus) { |
845 | int extra_hosts = 0; | |
846 | ||
847 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
848 | /* look for expander root buses */ | |
849 | if (pci_bus_is_root(bus)) { | |
850 | extra_hosts++; | |
851 | } | |
852 | } | |
f0bb276b | 853 | if (extra_hosts && x86ms->fw_cfg) { |
2118196b MA |
854 | uint64_t *val = g_malloc(sizeof(*val)); |
855 | *val = cpu_to_le64(extra_hosts); | |
f0bb276b | 856 | fw_cfg_add_file(x86ms->fw_cfg, |
2118196b MA |
857 | "etc/extra-pci-roots", val, sizeof(*val)); |
858 | } | |
859 | } | |
860 | ||
bb292f5a | 861 | acpi_setup(); |
f0bb276b PB |
862 | if (x86ms->fw_cfg) { |
863 | fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); | |
864 | fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); | |
e3cadac0 | 865 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
f0bb276b | 866 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
6d42eefa | 867 | } |
60c5e104 | 868 | |
f0bb276b | 869 | if (x86ms->apic_id_limit > 255 && !xen_enabled()) { |
60c5e104 IM |
870 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); |
871 | ||
a924b3d8 | 872 | if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || |
60c5e104 IM |
873 | iommu->intr_eim != ON_OFF_AUTO_ON) { |
874 | error_report("current -smp configuration requires " | |
875 | "Extended Interrupt Mode enabled. " | |
876 | "You can add an IOMMU using: " | |
877 | "-device intel-iommu,intremap=on,eim=on"); | |
878 | exit(EXIT_FAILURE); | |
879 | } | |
880 | } | |
3459a625 MT |
881 | } |
882 | ||
e4e8ba04 | 883 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 884 | { |
1f3aba37 | 885 | int i; |
aa570207 | 886 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 887 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b20c9bd5 | 888 | |
f0bb276b | 889 | x86ms->apic_xrupt_override = kvm_allows_irq0_override(); |
aa570207 | 890 | pcms->numa_nodes = ms->numa_state->num_nodes; |
dd4c2f01 EH |
891 | pcms->node_mem = g_malloc0(pcms->numa_nodes * |
892 | sizeof *pcms->node_mem); | |
aa570207 | 893 | for (i = 0; i < ms->numa_state->num_nodes; i++) { |
7e721e7b | 894 | pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; |
8c85901e WG |
895 | } |
896 | ||
9ebeed0c EH |
897 | pcms->machine_done.notify = pc_machine_done; |
898 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
899 | } |
900 | ||
83d08f26 MT |
901 | /* setup pci memory address space mapping into system address space */ |
902 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
903 | MemoryRegion *pci_address_space) | |
39848901 | 904 | { |
83d08f26 MT |
905 | /* Set to lower priority than RAM */ |
906 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
907 | pci_address_space, -1); | |
39848901 IM |
908 | } |
909 | ||
7bc35e0f | 910 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
911 | { |
912 | int i; | |
913 | FWCfgState *fw_cfg; | |
703a548a | 914 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 915 | X86MachineState *x86ms = X86_MACHINE(pcms); |
b33a5bbf | 916 | |
df1f79fd | 917 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 918 | |
305ae888 | 919 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
f0bb276b | 920 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); |
b33a5bbf CL |
921 | rom_set_fw(fw_cfg); |
922 | ||
703a548a SL |
923 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
924 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
b33a5bbf CL |
925 | for (i = 0; i < nb_option_roms; i++) { |
926 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 927 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
1fb0d709 | 928 | !strcmp(option_rom[i].name, "pvh.bin") || |
b33a5bbf CL |
929 | !strcmp(option_rom[i].name, "multiboot.bin")); |
930 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
931 | } | |
f0bb276b | 932 | x86ms->fw_cfg = fw_cfg; |
b33a5bbf CL |
933 | } |
934 | ||
5934e216 EH |
935 | void pc_memory_init(PCMachineState *pcms, |
936 | MemoryRegion *system_memory, | |
937 | MemoryRegion *rom_memory, | |
938 | MemoryRegion **ram_memory) | |
80cabfad | 939 | { |
cbc5b5f3 | 940 | int linux_boot, i; |
bd457782 | 941 | MemoryRegion *option_rom_mr; |
00cb2a99 | 942 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 943 | FWCfgState *fw_cfg; |
62b160c0 | 944 | MachineState *machine = MACHINE(pcms); |
264b4857 | 945 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
16a9e8a5 | 946 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f0bb276b | 947 | X86MachineState *x86ms = X86_MACHINE(pcms); |
d592d303 | 948 | |
f0bb276b PB |
949 | assert(machine->ram_size == x86ms->below_4g_mem_size + |
950 | x86ms->above_4g_mem_size); | |
9521d42b PB |
951 | |
952 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 953 | |
bd457782 IM |
954 | /* |
955 | * Split single memory region and use aliases to address portions of it, | |
956 | * done for backwards compatibility with older qemus. | |
00cb2a99 | 957 | */ |
bd457782 | 958 | *ram_memory = machine->ram; |
7267c094 | 959 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
bd457782 | 960 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, |
f0bb276b | 961 | 0, x86ms->below_4g_mem_size); |
00cb2a99 | 962 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
f0bb276b PB |
963 | e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); |
964 | if (x86ms->above_4g_mem_size > 0) { | |
7267c094 | 965 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
bd457782 IM |
966 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", |
967 | machine->ram, | |
f0bb276b PB |
968 | x86ms->below_4g_mem_size, |
969 | x86ms->above_4g_mem_size); | |
00cb2a99 AK |
970 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
971 | ram_above_4g); | |
f0bb276b | 972 | e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); |
bbe80adf | 973 | } |
82b36dc3 | 974 | |
bb292f5a | 975 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 976 | (machine->ram_slots || |
9521d42b | 977 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
978 | |
979 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
980 | mc->name); | |
981 | exit(EXIT_FAILURE); | |
982 | } | |
983 | ||
b0c14ec4 DH |
984 | /* always allocate the device memory information */ |
985 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
986 | ||
f2ffbe2b | 987 | /* initialize device memory address space */ |
bb292f5a | 988 | if (pcmc->has_reserved_memory && |
9521d42b | 989 | (machine->ram_size < machine->maxram_size)) { |
f2ffbe2b | 990 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
619d11e4 | 991 | |
a0cc8856 IM |
992 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
993 | error_report("unsupported amount of memory slots: %"PRIu64, | |
994 | machine->ram_slots); | |
995 | exit(EXIT_FAILURE); | |
996 | } | |
997 | ||
f2c38522 PK |
998 | if (QEMU_ALIGN_UP(machine->maxram_size, |
999 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1000 | error_report("maximum memory size must by aligned to multiple of " | |
1001 | "%d bytes", TARGET_PAGE_SIZE); | |
1002 | exit(EXIT_FAILURE); | |
1003 | } | |
1004 | ||
b0c14ec4 | 1005 | machine->device_memory->base = |
f0bb276b | 1006 | ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); |
619d11e4 | 1007 | |
16a9e8a5 | 1008 | if (pcmc->enforce_aligned_dimm) { |
f2ffbe2b | 1009 | /* size device region assuming 1G page max alignment per slot */ |
d471bf3e | 1010 | device_mem_size += (1 * GiB) * machine->ram_slots; |
085f8e88 IM |
1011 | } |
1012 | ||
f2ffbe2b DH |
1013 | if ((machine->device_memory->base + device_mem_size) < |
1014 | device_mem_size) { | |
619d11e4 IM |
1015 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, |
1016 | machine->maxram_size); | |
1017 | exit(EXIT_FAILURE); | |
1018 | } | |
1019 | ||
b0c14ec4 | 1020 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), |
f2ffbe2b | 1021 | "device-memory", device_mem_size); |
b0c14ec4 DH |
1022 | memory_region_add_subregion(system_memory, machine->device_memory->base, |
1023 | &machine->device_memory->mr); | |
619d11e4 | 1024 | } |
cbc5b5f3 JJ |
1025 | |
1026 | /* Initialize PC system firmware */ | |
5e640a9e | 1027 | pc_system_firmware_init(pcms, rom_memory); |
00cb2a99 | 1028 | |
7267c094 | 1029 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 1030 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1031 | &error_fatal); |
208fa0e4 IM |
1032 | if (pcmc->pci_enabled) { |
1033 | memory_region_set_readonly(option_rom_mr, true); | |
1034 | } | |
4463aee6 | 1035 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1036 | PC_ROM_MIN_VGA, |
1037 | option_rom_mr, | |
1038 | 1); | |
f753ff16 | 1039 | |
bd802bd9 | 1040 | fw_cfg = fw_cfg_arch_create(machine, |
f0bb276b | 1041 | x86ms->boot_cpus, x86ms->apic_id_limit); |
c886fc4c | 1042 | |
8832cb80 | 1043 | rom_set_fw(fw_cfg); |
1d108d97 | 1044 | |
b0c14ec4 | 1045 | if (pcmc->has_reserved_memory && machine->device_memory->base) { |
de268e13 | 1046 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 | 1047 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
b0c14ec4 | 1048 | uint64_t res_mem_end = machine->device_memory->base; |
2f8b5008 IM |
1049 | |
1050 | if (!pcmc->broken_reserved_end) { | |
b0c14ec4 | 1051 | res_mem_end += memory_region_size(&machine->device_memory->mr); |
2f8b5008 | 1052 | } |
d471bf3e | 1053 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); |
de268e13 IM |
1054 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1055 | } | |
1056 | ||
f753ff16 | 1057 | if (linux_boot) { |
703a548a SL |
1058 | x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, |
1059 | pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); | |
f753ff16 PB |
1060 | } |
1061 | ||
1062 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1063 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1064 | } |
f0bb276b | 1065 | x86ms->fw_cfg = fw_cfg; |
cb135f59 PX |
1066 | |
1067 | /* Init default IOAPIC address space */ | |
f0bb276b | 1068 | x86ms->ioapic_as = &address_space_memory; |
091c466e SK |
1069 | |
1070 | /* Init ACPI memory hotplug IO base address */ | |
1071 | pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; | |
3d53f5c3 IY |
1072 | } |
1073 | ||
9fa99d25 MA |
1074 | /* |
1075 | * The 64bit pci hole starts after "above 4G RAM" and | |
1076 | * potentially the space reserved for memory hotplug. | |
1077 | */ | |
1078 | uint64_t pc_pci_hole64_start(void) | |
1079 | { | |
1080 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1081 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
b0c14ec4 | 1082 | MachineState *ms = MACHINE(pcms); |
f0bb276b | 1083 | X86MachineState *x86ms = X86_MACHINE(pcms); |
9fa99d25 MA |
1084 | uint64_t hole64_start = 0; |
1085 | ||
b0c14ec4 DH |
1086 | if (pcmc->has_reserved_memory && ms->device_memory->base) { |
1087 | hole64_start = ms->device_memory->base; | |
9fa99d25 | 1088 | if (!pcmc->broken_reserved_end) { |
b0c14ec4 | 1089 | hole64_start += memory_region_size(&ms->device_memory->mr); |
9fa99d25 MA |
1090 | } |
1091 | } else { | |
f0bb276b | 1092 | hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; |
9fa99d25 MA |
1093 | } |
1094 | ||
d471bf3e | 1095 | return ROUND_UP(hole64_start, 1 * GiB); |
9fa99d25 MA |
1096 | } |
1097 | ||
48a18b3c | 1098 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1099 | { |
ad6d45fa AL |
1100 | DeviceState *dev = NULL; |
1101 | ||
bab47d9a | 1102 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1103 | if (pci_bus) { |
1104 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1105 | dev = pcidev ? &pcidev->qdev : NULL; | |
1106 | } else if (isa_bus) { | |
1107 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1108 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1109 | } |
bab47d9a | 1110 | rom_reset_order_override(); |
ad6d45fa | 1111 | return dev; |
765d7908 IY |
1112 | } |
1113 | ||
258711c6 JG |
1114 | static const MemoryRegionOps ioport80_io_ops = { |
1115 | .write = ioport80_write, | |
c02e1eac | 1116 | .read = ioport80_read, |
258711c6 JG |
1117 | .endianness = DEVICE_NATIVE_ENDIAN, |
1118 | .impl = { | |
1119 | .min_access_size = 1, | |
1120 | .max_access_size = 1, | |
1121 | }, | |
1122 | }; | |
1123 | ||
1124 | static const MemoryRegionOps ioportF0_io_ops = { | |
1125 | .write = ioportF0_write, | |
c02e1eac | 1126 | .read = ioportF0_read, |
258711c6 JG |
1127 | .endianness = DEVICE_NATIVE_ENDIAN, |
1128 | .impl = { | |
1129 | .min_access_size = 1, | |
1130 | .max_access_size = 1, | |
1131 | }, | |
1132 | }; | |
1133 | ||
ac64273c PMD |
1134 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) |
1135 | { | |
1136 | int i; | |
1137 | DriveInfo *fd[MAX_FD]; | |
1138 | qemu_irq *a20_line; | |
1139 | ISADevice *i8042, *port92, *vmmouse; | |
1140 | ||
def337ff | 1141 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
ac64273c PMD |
1142 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
1143 | ||
1144 | for (i = 0; i < MAX_FD; i++) { | |
1145 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1146 | create_fdctrl |= !!fd[i]; | |
1147 | } | |
1148 | if (create_fdctrl) { | |
1149 | fdctrl_init_isa(isa_bus, fd); | |
1150 | } | |
1151 | ||
1152 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1153 | if (!no_vmport) { | |
1154 | vmport_init(isa_bus); | |
1155 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1156 | } else { | |
1157 | vmmouse = NULL; | |
1158 | } | |
1159 | if (vmmouse) { | |
0fe4bb32 MAL |
1160 | object_property_set_link(OBJECT(vmmouse), OBJECT(i8042), |
1161 | "i8042", &error_abort); | |
1162 | qdev_init_nofail(DEVICE(vmmouse)); | |
ac64273c | 1163 | } |
9e5213c8 | 1164 | port92 = isa_create_simple(isa_bus, TYPE_PORT92); |
ac64273c PMD |
1165 | |
1166 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1167 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1820b70e PMD |
1168 | qdev_connect_gpio_out_named(DEVICE(port92), |
1169 | PORT92_A20_LINE, 0, a20_line[1]); | |
ac64273c PMD |
1170 | g_free(a20_line); |
1171 | } | |
1172 | ||
48a18b3c | 1173 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1174 | ISADevice **rtc_state, |
fd53c87c | 1175 | bool create_fdctrl, |
7a10ef51 | 1176 | bool no_vmport, |
feddd2fd | 1177 | bool has_pit, |
3a87d009 | 1178 | uint32_t hpet_irqs) |
ffe513da IY |
1179 | { |
1180 | int i; | |
ce967e2f JK |
1181 | DeviceState *hpet = NULL; |
1182 | int pit_isa_irq = 0; | |
1183 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1184 | qemu_irq rtc_irq = NULL; |
ac64273c | 1185 | ISADevice *pit = NULL; |
258711c6 JG |
1186 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1187 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1188 | |
2c9b15ca | 1189 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1190 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1191 | |
2c9b15ca | 1192 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1193 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1194 | |
5d17c0d2 JK |
1195 | /* |
1196 | * Check if an HPET shall be created. | |
1197 | * | |
1198 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1199 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1200 | */ | |
1201 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
51116102 | 1202 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1203 | if (hpet) { |
7a10ef51 LPF |
1204 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1205 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1206 | * IRQ8 and IRQ2. | |
1207 | */ | |
5d7fb0f2 | 1208 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
7a10ef51 LPF |
1209 | HPET_INTCAP, NULL); |
1210 | if (!compat) { | |
1211 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1212 | } | |
1213 | qdev_init_nofail(hpet); | |
1214 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1215 | ||
b881fbe9 | 1216 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1217 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1218 | } |
ce967e2f JK |
1219 | pit_isa_irq = -1; |
1220 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1221 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1222 | } |
ffe513da | 1223 | } |
6c646a11 | 1224 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1225 | |
1226 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1227 | ||
feddd2fd | 1228 | if (!xen_enabled() && has_pit) { |
15eafc2e | 1229 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1230 | pit = kvm_pit_init(isa_bus, 0x40); |
1231 | } else { | |
acf695ec | 1232 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1233 | } |
1234 | if (hpet) { | |
1235 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1236 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1237 | } |
1238 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1239 | } |
ffe513da | 1240 | |
55f613ac | 1241 | i8257_dma_init(isa_bus, 0); |
ffe513da | 1242 | |
ac64273c PMD |
1243 | /* Super I/O */ |
1244 | pc_superio_init(isa_bus, create_fdctrl, no_vmport); | |
ffe513da IY |
1245 | } |
1246 | ||
4b9c264b | 1247 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) |
9011a1a7 IY |
1248 | { |
1249 | int i; | |
1250 | ||
bab47d9a | 1251 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1252 | for (i = 0; i < nb_nics; i++) { |
1253 | NICInfo *nd = &nd_table[i]; | |
4b9c264b | 1254 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; |
9011a1a7 | 1255 | |
4b9c264b | 1256 | if (g_str_equal(model, "ne2k_isa")) { |
9011a1a7 IY |
1257 | pc_init_ne2k_isa(isa_bus, nd); |
1258 | } else { | |
4b9c264b | 1259 | pci_nic_init_nofail(nd, pci_bus, model, NULL); |
9011a1a7 IY |
1260 | } |
1261 | } | |
bab47d9a | 1262 | rom_reset_order_override(); |
9011a1a7 IY |
1263 | } |
1264 | ||
4501d317 PMD |
1265 | void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) |
1266 | { | |
1267 | qemu_irq *i8259; | |
1268 | ||
1269 | if (kvm_pic_in_kernel()) { | |
1270 | i8259 = kvm_i8259_init(isa_bus); | |
1271 | } else if (xen_enabled()) { | |
1272 | i8259 = xen_interrupt_controller_init(); | |
1273 | } else { | |
89a289c7 | 1274 | i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); |
4501d317 PMD |
1275 | } |
1276 | ||
1277 | for (size_t i = 0; i < ISA_NUM_IRQS; i++) { | |
1278 | i8259_irqs[i] = i8259[i]; | |
1279 | } | |
1280 | ||
1281 | g_free(i8259); | |
1282 | } | |
1283 | ||
d468115b DH |
1284 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
1285 | Error **errp) | |
1286 | { | |
1287 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
b0e62443 | 1288 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
f6a0d06b | 1289 | const MachineState *ms = MACHINE(hotplug_dev); |
d468115b | 1290 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
b0e62443 | 1291 | const uint64_t legacy_align = TARGET_PAGE_SIZE; |
ae909496 | 1292 | Error *local_err = NULL; |
d468115b DH |
1293 | |
1294 | /* | |
1295 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1296 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1297 | * addition to cover this case. | |
1298 | */ | |
1299 | if (!pcms->acpi_dev || !acpi_enabled) { | |
1300 | error_setg(errp, | |
1301 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
1302 | return; | |
1303 | } | |
1304 | ||
f6a0d06b | 1305 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
d468115b DH |
1306 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); |
1307 | return; | |
1308 | } | |
8f1ffe5b | 1309 | |
ae909496 TH |
1310 | hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); |
1311 | if (local_err) { | |
1312 | error_propagate(errp, local_err); | |
1313 | return; | |
1314 | } | |
1315 | ||
fd3416f5 | 1316 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), |
b0e62443 | 1317 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); |
d468115b DH |
1318 | } |
1319 | ||
bb6e2f7a DH |
1320 | static void pc_memory_plug(HotplugHandler *hotplug_dev, |
1321 | DeviceState *dev, Error **errp) | |
95bee274 IM |
1322 | { |
1323 | Error *local_err = NULL; | |
1324 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f6a0d06b | 1325 | MachineState *ms = MACHINE(hotplug_dev); |
7f3cf2d6 | 1326 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1327 | |
fd3416f5 | 1328 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); |
43bbb49e | 1329 | if (local_err) { |
b8865591 IM |
1330 | goto out; |
1331 | } | |
1332 | ||
7f3cf2d6 | 1333 | if (is_nvdimm) { |
f6a0d06b | 1334 | nvdimm_plug(ms->nvdimms_state); |
c7f8d0f3 XG |
1335 | } |
1336 | ||
473ac567 | 1337 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1338 | out: |
1339 | error_propagate(errp, local_err); | |
1340 | } | |
1341 | ||
bb6e2f7a DH |
1342 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, |
1343 | DeviceState *dev, Error **errp) | |
64fec58e | 1344 | { |
64fec58e TC |
1345 | Error *local_err = NULL; |
1346 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1347 | ||
8cd91ace HZ |
1348 | /* |
1349 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1350 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1351 | * addition to cover this case. | |
1352 | */ | |
1353 | if (!pcms->acpi_dev || !acpi_enabled) { | |
64fec58e | 1354 | error_setg(&local_err, |
8cd91ace | 1355 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
64fec58e TC |
1356 | goto out; |
1357 | } | |
1358 | ||
b097cc52 XG |
1359 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1360 | error_setg(&local_err, | |
1361 | "nvdimm device hot unplug is not supported yet."); | |
1362 | goto out; | |
1363 | } | |
1364 | ||
473ac567 DH |
1365 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1366 | &local_err); | |
64fec58e TC |
1367 | out: |
1368 | error_propagate(errp, local_err); | |
1369 | } | |
1370 | ||
bb6e2f7a DH |
1371 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, |
1372 | DeviceState *dev, Error **errp) | |
f7d3e29d TC |
1373 | { |
1374 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f7d3e29d TC |
1375 | Error *local_err = NULL; |
1376 | ||
473ac567 | 1377 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
f7d3e29d TC |
1378 | if (local_err) { |
1379 | goto out; | |
1380 | } | |
1381 | ||
fd3416f5 | 1382 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); |
07578b0a | 1383 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
f7d3e29d TC |
1384 | out: |
1385 | error_propagate(errp, local_err); | |
1386 | } | |
1387 | ||
3811ef14 IM |
1388 | static int pc_apic_cmp(const void *a, const void *b) |
1389 | { | |
1390 | CPUArchId *apic_a = (CPUArchId *)a; | |
1391 | CPUArchId *apic_b = (CPUArchId *)b; | |
1392 | ||
1393 | return apic_a->arch_id - apic_b->arch_id; | |
1394 | } | |
1395 | ||
7baef5cf | 1396 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
38690a1c | 1397 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no |
b12227af | 1398 | * entry corresponding to CPU's apic_id returns NULL. |
7baef5cf | 1399 | */ |
1ea69c0e | 1400 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
7baef5cf | 1401 | { |
7baef5cf IM |
1402 | CPUArchId apic_id, *found_cpu; |
1403 | ||
1ea69c0e | 1404 | apic_id.arch_id = id; |
38690a1c IM |
1405 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, |
1406 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
7baef5cf IM |
1407 | pc_apic_cmp); |
1408 | if (found_cpu && idx) { | |
38690a1c | 1409 | *idx = found_cpu - ms->possible_cpus->cpus; |
7baef5cf IM |
1410 | } |
1411 | return found_cpu; | |
1412 | } | |
1413 | ||
5279569e GZ |
1414 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1415 | DeviceState *dev, Error **errp) | |
1416 | { | |
7baef5cf | 1417 | CPUArchId *found_cpu; |
5279569e | 1418 | Error *local_err = NULL; |
1ea69c0e | 1419 | X86CPU *cpu = X86_CPU(dev); |
5279569e | 1420 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1421 | X86MachineState *x86ms = X86_MACHINE(pcms); |
5279569e | 1422 | |
a44a49db | 1423 | if (pcms->acpi_dev) { |
473ac567 | 1424 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
a44a49db IM |
1425 | if (local_err) { |
1426 | goto out; | |
1427 | } | |
5279569e GZ |
1428 | } |
1429 | ||
e3cadac0 | 1430 | /* increment the number of CPUs */ |
f0bb276b PB |
1431 | x86ms->boot_cpus++; |
1432 | if (x86ms->rtc) { | |
1433 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); | |
26ef65be | 1434 | } |
f0bb276b PB |
1435 | if (x86ms->fw_cfg) { |
1436 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
2d996150 GZ |
1437 | } |
1438 | ||
1ea69c0e | 1439 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8aba3842 | 1440 | found_cpu->cpu = OBJECT(dev); |
5279569e GZ |
1441 | out: |
1442 | error_propagate(errp, local_err); | |
1443 | } | |
8872c25a IM |
1444 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1445 | DeviceState *dev, Error **errp) | |
1446 | { | |
73360e27 | 1447 | int idx = -1; |
8872c25a | 1448 | Error *local_err = NULL; |
1ea69c0e | 1449 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1450 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1451 | ||
75ba2ddb IM |
1452 | if (!pcms->acpi_dev) { |
1453 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
1454 | goto out; | |
1455 | } | |
1456 | ||
1ea69c0e | 1457 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
73360e27 IM |
1458 | assert(idx != -1); |
1459 | if (idx == 0) { | |
1460 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1461 | goto out; | |
1462 | } | |
1463 | ||
473ac567 DH |
1464 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, |
1465 | &local_err); | |
8872c25a IM |
1466 | if (local_err) { |
1467 | goto out; | |
1468 | } | |
1469 | ||
1470 | out: | |
1471 | error_propagate(errp, local_err); | |
1472 | ||
1473 | } | |
1474 | ||
1475 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1476 | DeviceState *dev, Error **errp) | |
1477 | { | |
8fe6374e | 1478 | CPUArchId *found_cpu; |
8872c25a | 1479 | Error *local_err = NULL; |
1ea69c0e | 1480 | X86CPU *cpu = X86_CPU(dev); |
8872c25a | 1481 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1482 | X86MachineState *x86ms = X86_MACHINE(pcms); |
8872c25a | 1483 | |
473ac567 | 1484 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); |
8872c25a IM |
1485 | if (local_err) { |
1486 | goto out; | |
1487 | } | |
1488 | ||
1ea69c0e | 1489 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8fe6374e | 1490 | found_cpu->cpu = NULL; |
07578b0a | 1491 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
8872c25a | 1492 | |
e3cadac0 | 1493 | /* decrement the number of CPUs */ |
f0bb276b | 1494 | x86ms->boot_cpus--; |
e3cadac0 | 1495 | /* Update the number of CPUs in CMOS */ |
f0bb276b PB |
1496 | rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); |
1497 | fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); | |
8872c25a IM |
1498 | out: |
1499 | error_propagate(errp, local_err); | |
1500 | } | |
5279569e | 1501 | |
4ec60c76 IM |
1502 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
1503 | DeviceState *dev, Error **errp) | |
1504 | { | |
1505 | int idx; | |
a15d2728 | 1506 | CPUState *cs; |
e8f7b83e | 1507 | CPUArchId *cpu_slot; |
dcf08bc6 | 1508 | X86CPUTopoIDs topo_ids; |
4ec60c76 | 1509 | X86CPU *cpu = X86_CPU(dev); |
cabea7dc | 1510 | CPUX86State *env = &cpu->env; |
6970c5ff | 1511 | MachineState *ms = MACHINE(hotplug_dev); |
4ec60c76 | 1512 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
f0bb276b | 1513 | X86MachineState *x86ms = X86_MACHINE(pcms); |
0e11fc69 LX |
1514 | unsigned int smp_cores = ms->smp.cores; |
1515 | unsigned int smp_threads = ms->smp.threads; | |
4ec60c76 | 1516 | |
6970c5ff IM |
1517 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { |
1518 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
1519 | ms->cpu_type); | |
1520 | return; | |
1521 | } | |
1522 | ||
f0bb276b | 1523 | env->nr_dies = x86ms->smp_dies; |
cabea7dc | 1524 | |
c26ae610 LX |
1525 | /* |
1526 | * If APIC ID is not set, | |
1527 | * set it based on socket/die/core/thread properties. | |
1528 | */ | |
e8f7b83e | 1529 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { |
c26ae610 | 1530 | int max_socket = (ms->smp.max_cpus - 1) / |
f0bb276b | 1531 | smp_threads / smp_cores / x86ms->smp_dies; |
e8f7b83e | 1532 | |
fea374e7 EH |
1533 | /* |
1534 | * die-id was optional in QEMU 4.0 and older, so keep it optional | |
1535 | * if there's only one die per socket. | |
1536 | */ | |
f0bb276b | 1537 | if (cpu->die_id < 0 && x86ms->smp_dies == 1) { |
fea374e7 EH |
1538 | cpu->die_id = 0; |
1539 | } | |
1540 | ||
e8f7b83e IM |
1541 | if (cpu->socket_id < 0) { |
1542 | error_setg(errp, "CPU socket-id is not set"); | |
1543 | return; | |
1544 | } else if (cpu->socket_id > max_socket) { | |
1545 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1546 | cpu->socket_id, max_socket); | |
1547 | return; | |
23d9cff4 EH |
1548 | } |
1549 | if (cpu->die_id < 0) { | |
1550 | error_setg(errp, "CPU die-id is not set"); | |
1551 | return; | |
f0bb276b | 1552 | } else if (cpu->die_id > x86ms->smp_dies - 1) { |
176d2cda | 1553 | error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", |
f0bb276b | 1554 | cpu->die_id, x86ms->smp_dies - 1); |
176d2cda | 1555 | return; |
e8f7b83e IM |
1556 | } |
1557 | if (cpu->core_id < 0) { | |
1558 | error_setg(errp, "CPU core-id is not set"); | |
1559 | return; | |
1560 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1561 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1562 | cpu->core_id, smp_cores - 1); | |
1563 | return; | |
1564 | } | |
1565 | if (cpu->thread_id < 0) { | |
1566 | error_setg(errp, "CPU thread-id is not set"); | |
1567 | return; | |
1568 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1569 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1570 | cpu->thread_id, smp_threads - 1); | |
1571 | return; | |
1572 | } | |
1573 | ||
dcf08bc6 BM |
1574 | topo_ids.pkg_id = cpu->socket_id; |
1575 | topo_ids.die_id = cpu->die_id; | |
1576 | topo_ids.core_id = cpu->core_id; | |
1577 | topo_ids.smt_id = cpu->thread_id; | |
f0bb276b | 1578 | cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores, |
dcf08bc6 | 1579 | smp_threads, &topo_ids); |
e8f7b83e IM |
1580 | } |
1581 | ||
1ea69c0e | 1582 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
4ec60c76 | 1583 | if (!cpu_slot) { |
38690a1c IM |
1584 | MachineState *ms = MACHINE(pcms); |
1585 | ||
f0bb276b | 1586 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
dcf08bc6 | 1587 | smp_cores, smp_threads, &topo_ids); |
d65af288 LX |
1588 | error_setg(errp, |
1589 | "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" | |
1590 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
dcf08bc6 | 1591 | topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, |
d65af288 | 1592 | cpu->apic_id, ms->possible_cpus->len - 1); |
4ec60c76 IM |
1593 | return; |
1594 | } | |
1595 | ||
1596 | if (cpu_slot->cpu) { | |
1597 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1598 | idx, cpu->apic_id); | |
1599 | return; | |
1600 | } | |
d89c2b8b IM |
1601 | |
1602 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
c5514d0e | 1603 | * so that machine_query_hotpluggable_cpus would show correct values |
d89c2b8b IM |
1604 | */ |
1605 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1606 | * once -smp refactoring is complete and there will be CPU private | |
1607 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
f0bb276b | 1608 | x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, |
dcf08bc6 BM |
1609 | smp_cores, smp_threads, &topo_ids); |
1610 | if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { | |
d89c2b8b | 1611 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" |
dcf08bc6 BM |
1612 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, |
1613 | topo_ids.pkg_id); | |
d89c2b8b IM |
1614 | return; |
1615 | } | |
dcf08bc6 | 1616 | cpu->socket_id = topo_ids.pkg_id; |
d89c2b8b | 1617 | |
dcf08bc6 | 1618 | if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { |
176d2cda | 1619 | error_setg(errp, "property die-id: %u doesn't match set apic-id:" |
dcf08bc6 | 1620 | " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); |
176d2cda LX |
1621 | return; |
1622 | } | |
dcf08bc6 | 1623 | cpu->die_id = topo_ids.die_id; |
176d2cda | 1624 | |
dcf08bc6 | 1625 | if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { |
d89c2b8b | 1626 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" |
dcf08bc6 BM |
1627 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, |
1628 | topo_ids.core_id); | |
d89c2b8b IM |
1629 | return; |
1630 | } | |
dcf08bc6 | 1631 | cpu->core_id = topo_ids.core_id; |
d89c2b8b | 1632 | |
dcf08bc6 | 1633 | if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { |
d89c2b8b | 1634 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" |
dcf08bc6 BM |
1635 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, |
1636 | topo_ids.smt_id); | |
d89c2b8b IM |
1637 | return; |
1638 | } | |
dcf08bc6 | 1639 | cpu->thread_id = topo_ids.smt_id; |
a15d2728 | 1640 | |
2d384d7c VK |
1641 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && |
1642 | !kvm_hv_vpindex_settable()) { | |
e9688fab RK |
1643 | error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); |
1644 | return; | |
1645 | } | |
1646 | ||
a15d2728 IM |
1647 | cs = CPU(cpu); |
1648 | cs->cpu_index = idx; | |
93b2a8cb | 1649 | |
a0ceb640 | 1650 | numa_cpu_pre_plug(cpu_slot, dev, errp); |
4ec60c76 IM |
1651 | } |
1652 | ||
a0a49813 DH |
1653 | static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, |
1654 | DeviceState *dev, Error **errp) | |
1655 | { | |
1656 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1657 | Error *local_err = NULL; | |
1658 | ||
1659 | if (!hotplug_dev2) { | |
1660 | /* | |
1661 | * Without a bus hotplug handler, we cannot control the plug/unplug | |
1662 | * order. This should never be the case on x86, however better add | |
1663 | * a safety net. | |
1664 | */ | |
1665 | error_setg(errp, "virtio-pmem-pci not supported on this bus."); | |
1666 | return; | |
1667 | } | |
1668 | /* | |
1669 | * First, see if we can plug this memory device at all. If that | |
1670 | * succeeds, branch of to the actual hotplug handler. | |
1671 | */ | |
1672 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
1673 | &local_err); | |
1674 | if (!local_err) { | |
1675 | hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); | |
1676 | } | |
1677 | error_propagate(errp, local_err); | |
1678 | } | |
1679 | ||
1680 | static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, | |
1681 | DeviceState *dev, Error **errp) | |
1682 | { | |
1683 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
1684 | Error *local_err = NULL; | |
1685 | ||
1686 | /* | |
1687 | * Plug the memory device first and then branch off to the actual | |
1688 | * hotplug handler. If that one fails, we can easily undo the memory | |
1689 | * device bits. | |
1690 | */ | |
1691 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1692 | hotplug_handler_plug(hotplug_dev2, dev, &local_err); | |
1693 | if (local_err) { | |
1694 | memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
1695 | } | |
1696 | error_propagate(errp, local_err); | |
1697 | } | |
1698 | ||
1699 | static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, | |
1700 | DeviceState *dev, Error **errp) | |
1701 | { | |
1702 | /* We don't support virtio pmem hot unplug */ | |
1703 | error_setg(errp, "virtio pmem device unplug not supported."); | |
1704 | } | |
1705 | ||
1706 | static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, | |
1707 | DeviceState *dev, Error **errp) | |
1708 | { | |
1709 | /* We don't support virtio pmem hot unplug */ | |
1710 | } | |
1711 | ||
4ec60c76 IM |
1712 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
1713 | DeviceState *dev, Error **errp) | |
1714 | { | |
d468115b DH |
1715 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
1716 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
1717 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
4ec60c76 | 1718 | pc_cpu_pre_plug(hotplug_dev, dev, errp); |
a0a49813 DH |
1719 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1720 | pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); | |
4ec60c76 IM |
1721 | } |
1722 | } | |
1723 | ||
95bee274 IM |
1724 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
1725 | DeviceState *dev, Error **errp) | |
1726 | { | |
1727 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
bb6e2f7a | 1728 | pc_memory_plug(hotplug_dev, dev, errp); |
5279569e GZ |
1729 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1730 | pc_cpu_plug(hotplug_dev, dev, errp); | |
a0a49813 DH |
1731 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1732 | pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
1733 | } |
1734 | } | |
1735 | ||
d9c5c5b8 TC |
1736 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
1737 | DeviceState *dev, Error **errp) | |
1738 | { | |
64fec58e | 1739 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1740 | pc_memory_unplug_request(hotplug_dev, dev, errp); |
8872c25a IM |
1741 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1742 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1743 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1744 | pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); | |
64fec58e TC |
1745 | } else { |
1746 | error_setg(errp, "acpi: device unplug request for not supported device" | |
1747 | " type: %s", object_get_typename(OBJECT(dev))); | |
1748 | } | |
d9c5c5b8 TC |
1749 | } |
1750 | ||
232391c1 TC |
1751 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
1752 | DeviceState *dev, Error **errp) | |
1753 | { | |
f7d3e29d | 1754 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 1755 | pc_memory_unplug(hotplug_dev, dev, errp); |
8872c25a IM |
1756 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
1757 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
a0a49813 DH |
1758 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { |
1759 | pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); | |
f7d3e29d TC |
1760 | } else { |
1761 | error_setg(errp, "acpi: device unplug for not supported device" | |
1762 | " type: %s", object_get_typename(OBJECT(dev))); | |
1763 | } | |
232391c1 TC |
1764 | } |
1765 | ||
285816d7 | 1766 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, |
95bee274 IM |
1767 | DeviceState *dev) |
1768 | { | |
5279569e | 1769 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
a0a49813 DH |
1770 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || |
1771 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
95bee274 IM |
1772 | return HOTPLUG_HANDLER(machine); |
1773 | } | |
1774 | ||
38aefb57 | 1775 | return NULL; |
95bee274 IM |
1776 | } |
1777 | ||
bf1e8939 | 1778 | static void |
f2ffbe2b DH |
1779 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, |
1780 | const char *name, void *opaque, | |
1781 | Error **errp) | |
bf1e8939 | 1782 | { |
b0c14ec4 | 1783 | MachineState *ms = MACHINE(obj); |
fc3b77e2 IM |
1784 | int64_t value = 0; |
1785 | ||
1786 | if (ms->device_memory) { | |
1787 | value = memory_region_size(&ms->device_memory->mr); | |
1788 | } | |
bf1e8939 | 1789 | |
51e72bc1 | 1790 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
1791 | } |
1792 | ||
d7bce999 EB |
1793 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
1794 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1795 | { |
1796 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 1797 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 1798 | |
51e72bc1 | 1799 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
1800 | } |
1801 | ||
d7bce999 EB |
1802 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
1803 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
1804 | { |
1805 | PCMachineState *pcms = PC_MACHINE(obj); | |
1806 | ||
51e72bc1 | 1807 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
1808 | } |
1809 | ||
be232eb0 CP |
1810 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
1811 | { | |
1812 | PCMachineState *pcms = PC_MACHINE(obj); | |
1813 | ||
f5878b03 | 1814 | return pcms->smbus_enabled; |
be232eb0 CP |
1815 | } |
1816 | ||
1817 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
1818 | { | |
1819 | PCMachineState *pcms = PC_MACHINE(obj); | |
1820 | ||
f5878b03 | 1821 | pcms->smbus_enabled = value; |
be232eb0 CP |
1822 | } |
1823 | ||
272f0428 CP |
1824 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
1825 | { | |
1826 | PCMachineState *pcms = PC_MACHINE(obj); | |
1827 | ||
f5878b03 | 1828 | return pcms->sata_enabled; |
272f0428 CP |
1829 | } |
1830 | ||
1831 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
1832 | { | |
1833 | PCMachineState *pcms = PC_MACHINE(obj); | |
1834 | ||
f5878b03 | 1835 | pcms->sata_enabled = value; |
272f0428 CP |
1836 | } |
1837 | ||
feddd2fd CP |
1838 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
1839 | { | |
1840 | PCMachineState *pcms = PC_MACHINE(obj); | |
1841 | ||
f5878b03 | 1842 | return pcms->pit_enabled; |
feddd2fd CP |
1843 | } |
1844 | ||
1845 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
1846 | { | |
1847 | PCMachineState *pcms = PC_MACHINE(obj); | |
1848 | ||
f5878b03 | 1849 | pcms->pit_enabled = value; |
feddd2fd CP |
1850 | } |
1851 | ||
bf1e8939 IM |
1852 | static void pc_machine_initfn(Object *obj) |
1853 | { | |
c87b1520 DS |
1854 | PCMachineState *pcms = PC_MACHINE(obj); |
1855 | ||
97fd1ea8 | 1856 | #ifdef CONFIG_VMPORT |
d1048bef | 1857 | pcms->vmport = ON_OFF_AUTO_AUTO; |
97fd1ea8 JM |
1858 | #else |
1859 | pcms->vmport = ON_OFF_AUTO_OFF; | |
1860 | #endif /* CONFIG_VMPORT */ | |
021746c1 WL |
1861 | /* acpi build is enabled by default if machine supports it */ |
1862 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
f5878b03 CM |
1863 | pcms->smbus_enabled = true; |
1864 | pcms->sata_enabled = true; | |
1865 | pcms->pit_enabled = true; | |
ebc29e1b MA |
1866 | |
1867 | pc_system_flash_create(pcms); | |
bf1e8939 IM |
1868 | } |
1869 | ||
a0628599 | 1870 | static void pc_machine_reset(MachineState *machine) |
ae50c55a ZG |
1871 | { |
1872 | CPUState *cs; | |
1873 | X86CPU *cpu; | |
1874 | ||
1875 | qemu_devices_reset(); | |
1876 | ||
1877 | /* Reset APIC after devices have been reset to cancel | |
1878 | * any changes that qemu_devices_reset() might have done. | |
1879 | */ | |
1880 | CPU_FOREACH(cs) { | |
1881 | cpu = X86_CPU(cs); | |
1882 | ||
1883 | if (cpu->apic_state) { | |
f703a04c | 1884 | device_legacy_reset(cpu->apic_state); |
ae50c55a ZG |
1885 | } |
1886 | } | |
1887 | } | |
1888 | ||
c508bd12 NP |
1889 | static void pc_machine_wakeup(MachineState *machine) |
1890 | { | |
1891 | cpu_synchronize_all_states(); | |
1892 | pc_machine_reset(machine); | |
1893 | cpu_synchronize_all_post_reset(); | |
1894 | } | |
1895 | ||
c6cbc29d PX |
1896 | static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) |
1897 | { | |
1898 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
1899 | IntelIOMMUState *intel_iommu; | |
1900 | ||
1901 | if (iommu && | |
1902 | object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && | |
1903 | object_dynamic_cast((Object *)dev, "vfio-pci")) { | |
1904 | intel_iommu = INTEL_IOMMU_DEVICE(iommu); | |
1905 | if (!intel_iommu->caching_mode) { | |
1906 | error_setg(errp, "Device assignment is not allowed without " | |
1907 | "enabling caching-mode=on for Intel IOMMU."); | |
1908 | return false; | |
1909 | } | |
1910 | } | |
1911 | ||
1912 | return true; | |
1913 | } | |
1914 | ||
95bee274 IM |
1915 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
1916 | { | |
1917 | MachineClass *mc = MACHINE_CLASS(oc); | |
1918 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
1919 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1920 | ||
7102fa70 EH |
1921 | pcmc->pci_enabled = true; |
1922 | pcmc->has_acpi_build = true; | |
1923 | pcmc->rsdp_in_ram = true; | |
1924 | pcmc->smbios_defaults = true; | |
1925 | pcmc->smbios_uuid_encoded = true; | |
1926 | pcmc->gigabyte_align = true; | |
1927 | pcmc->has_reserved_memory = true; | |
1928 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 1929 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
1930 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
1931 | * to be used at the moment, 32K should be enough for a while. */ | |
1932 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
98e753a6 | 1933 | pcmc->linuxboot_dma_enabled = true; |
fda672b5 | 1934 | pcmc->pvh_enabled = true; |
debbdc00 | 1935 | assert(!mc->get_hotplug_handler); |
285816d7 | 1936 | mc->get_hotplug_handler = pc_get_hotplug_handler; |
c6cbc29d | 1937 | mc->hotplug_allowed = pc_hotplug_allowed; |
81ef68e4 SL |
1938 | mc->cpu_index_to_instance_props = x86_cpu_index_to_props; |
1939 | mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; | |
1940 | mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; | |
7b8be49d | 1941 | mc->auto_enable_numa_with_memhp = true; |
c5514d0e | 1942 | mc->has_hotpluggable_cpus = true; |
41742767 | 1943 | mc->default_boot_order = "cad"; |
4458fb3a | 1944 | mc->hot_add_cpu = pc_hot_add_cpu; |
6f479566 | 1945 | mc->smp_parse = pc_smp_parse; |
2059839b | 1946 | mc->block_default_type = IF_IDE; |
4458fb3a | 1947 | mc->max_cpus = 255; |
ae50c55a | 1948 | mc->reset = pc_machine_reset; |
c508bd12 | 1949 | mc->wakeup = pc_machine_wakeup; |
4ec60c76 | 1950 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 1951 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 1952 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 1953 | hc->unplug = pc_machine_device_unplug_cb; |
311ca98d | 1954 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
f6a0d06b | 1955 | mc->nvdimm_supported = true; |
cd5ff833 | 1956 | mc->numa_mem_supported = true; |
bd457782 | 1957 | mc->default_ram_id = "pc.ram"; |
0efc257d | 1958 | |
f2ffbe2b DH |
1959 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", |
1960 | pc_machine_get_device_memory_region_size, NULL, | |
0efc257d EH |
1961 | NULL, NULL, &error_abort); |
1962 | ||
0efc257d EH |
1963 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", |
1964 | pc_machine_get_vmport, pc_machine_set_vmport, | |
1965 | NULL, NULL, &error_abort); | |
1966 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
1967 | "Enable vmport (pc & q35)", &error_abort); | |
1968 | ||
be232eb0 CP |
1969 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, |
1970 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
272f0428 CP |
1971 | |
1972 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
1973 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
feddd2fd CP |
1974 | |
1975 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
1976 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
95bee274 IM |
1977 | } |
1978 | ||
d5747cac IM |
1979 | static const TypeInfo pc_machine_info = { |
1980 | .name = TYPE_PC_MACHINE, | |
f0bb276b | 1981 | .parent = TYPE_X86_MACHINE, |
d5747cac IM |
1982 | .abstract = true, |
1983 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 1984 | .instance_init = pc_machine_initfn, |
d5747cac | 1985 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
1986 | .class_init = pc_machine_class_init, |
1987 | .interfaces = (InterfaceInfo[]) { | |
1988 | { TYPE_HOTPLUG_HANDLER }, | |
1989 | { } | |
1990 | }, | |
d5747cac IM |
1991 | }; |
1992 | ||
1993 | static void pc_machine_register_types(void) | |
1994 | { | |
1995 | type_register_static(&pc_machine_info); | |
1996 | } | |
1997 | ||
1998 | type_init(pc_machine_register_types) |