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5fafdf24 | 1 | /* |
9ee6e8bb | 2 | * ARM Generic/Distributed Interrupt Controller |
e69954b9 | 3 | * |
9ee6e8bb | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
e69954b9 PB |
8 | */ |
9 | ||
9ee6e8bb | 10 | /* This file contains implementation code for the RealView EB interrupt |
0d256bdc PM |
11 | * controller, MPCore distributed interrupt controller and ARMv7-M |
12 | * Nested Vectored Interrupt Controller. | |
13 | * It is compiled in two ways: | |
14 | * (1) as a standalone file to produce a sysbus device which is a GIC | |
15 | * that can be used on the realview board and as one of the builtin | |
16 | * private peripherals for the ARM MP CPUs (11MPCore, A9, etc) | |
17 | * (2) by being directly #included into armv7m_nvic.c to produce the | |
18 | * armv7m_nvic device. | |
19 | */ | |
e69954b9 | 20 | |
8ef94f0b | 21 | #include "qemu/osdep.h" |
83c9f4ca | 22 | #include "hw/sysbus.h" |
47b43a1f | 23 | #include "gic_internal.h" |
da34e65c | 24 | #include "qapi/error.h" |
dfc08079 | 25 | #include "qom/cpu.h" |
03dd024f | 26 | #include "qemu/log.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
2531088f | 28 | #include "trace.h" |
5d721b78 | 29 | #include "sysemu/kvm.h" |
386e2955 | 30 | |
68bf93ce | 31 | /* #define DEBUG_GIC */ |
e69954b9 PB |
32 | |
33 | #ifdef DEBUG_GIC | |
68bf93ce | 34 | #define DEBUG_GIC_GATE 1 |
e69954b9 | 35 | #else |
68bf93ce | 36 | #define DEBUG_GIC_GATE 0 |
e69954b9 PB |
37 | #endif |
38 | ||
68bf93ce AB |
39 | #define DPRINTF(fmt, ...) do { \ |
40 | if (DEBUG_GIC_GATE) { \ | |
41 | fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ | |
42 | } \ | |
43 | } while (0) | |
44 | ||
3355c360 AF |
45 | static const uint8_t gic_id_11mpcore[] = { |
46 | 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
47 | }; | |
48 | ||
49 | static const uint8_t gic_id_gicv1[] = { | |
50 | 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
51 | }; | |
52 | ||
53 | static const uint8_t gic_id_gicv2[] = { | |
54 | 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
2a29ddee PM |
55 | }; |
56 | ||
fae15286 | 57 | static inline int gic_get_current_cpu(GICState *s) |
926c4aff | 58 | { |
926c4aff | 59 | if (s->num_cpu > 1) { |
4917cf44 | 60 | return current_cpu->cpu_index; |
926c4aff | 61 | } |
926c4aff PM |
62 | return 0; |
63 | } | |
64 | ||
4a37e0e4 LM |
65 | static inline int gic_get_current_vcpu(GICState *s) |
66 | { | |
67 | return gic_get_current_cpu(s) + GIC_NCPU; | |
68 | } | |
69 | ||
c27a5ba9 FA |
70 | /* Return true if this GIC config has interrupt groups, which is |
71 | * true if we're a GICv2, or a GICv1 with the security extensions. | |
72 | */ | |
73 | static inline bool gic_has_groups(GICState *s) | |
74 | { | |
75 | return s->revision == 2 || s->security_extn; | |
76 | } | |
77 | ||
3dd0471b LM |
78 | static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) |
79 | { | |
80 | return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; | |
81 | } | |
82 | ||
cbe1282b LM |
83 | static inline void gic_get_best_irq(GICState *s, int cpu, |
84 | int *best_irq, int *best_prio, int *group) | |
85 | { | |
86 | int irq; | |
87 | int cm = 1 << cpu; | |
88 | ||
89 | *best_irq = 1023; | |
90 | *best_prio = 0x100; | |
91 | ||
92 | for (irq = 0; irq < s->num_irq; irq++) { | |
93 | if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && | |
94 | (!GIC_DIST_TEST_ACTIVE(irq, cm)) && | |
95 | (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { | |
96 | if (GIC_DIST_GET_PRIORITY(irq, cpu) < *best_prio) { | |
97 | *best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); | |
98 | *best_irq = irq; | |
99 | } | |
100 | } | |
101 | } | |
102 | ||
103 | if (*best_irq < 1023) { | |
104 | *group = GIC_DIST_TEST_GROUP(*best_irq, cm); | |
105 | } | |
106 | } | |
107 | ||
108 | static inline void gic_get_best_virq(GICState *s, int cpu, | |
109 | int *best_irq, int *best_prio, int *group) | |
110 | { | |
111 | int lr_idx = 0; | |
112 | ||
113 | *best_irq = 1023; | |
114 | *best_prio = 0x100; | |
115 | ||
116 | for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { | |
117 | uint32_t lr_entry = s->h_lr[lr_idx][cpu]; | |
118 | int state = GICH_LR_STATE(lr_entry); | |
119 | ||
120 | if (state == GICH_LR_STATE_PENDING) { | |
121 | int prio = GICH_LR_PRIORITY(lr_entry); | |
122 | ||
123 | if (prio < *best_prio) { | |
124 | *best_prio = prio; | |
125 | *best_irq = GICH_LR_VIRT_ID(lr_entry); | |
126 | *group = GICH_LR_GROUP(lr_entry); | |
127 | } | |
128 | } | |
129 | } | |
130 | } | |
131 | ||
132 | /* Return true if IRQ signaling is enabled for the given cpu and at least one | |
133 | * of the given groups: | |
134 | * - in the non-virt case, the distributor must be enabled for one of the | |
135 | * given groups | |
136 | * - in the virt case, the virtual interface must be enabled. | |
137 | * - in all cases, the (v)CPU interface must be enabled for one of the given | |
138 | * groups. | |
139 | */ | |
140 | static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt, | |
141 | int group_mask) | |
142 | { | |
143 | if (!virt && !(s->ctlr & group_mask)) { | |
144 | return false; | |
145 | } | |
146 | ||
147 | if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) { | |
148 | return false; | |
149 | } | |
150 | ||
151 | if (!(s->cpu_ctlr[cpu] & group_mask)) { | |
152 | return false; | |
153 | } | |
154 | ||
155 | return true; | |
156 | } | |
157 | ||
e69954b9 PB |
158 | /* TODO: Many places that call this routine could be optimized. */ |
159 | /* Update interrupt status after enabled or pending bits have been changed. */ | |
cbe1282b | 160 | static inline void gic_update_internal(GICState *s, bool virt) |
e69954b9 PB |
161 | { |
162 | int best_irq; | |
163 | int best_prio; | |
dadbb58f | 164 | int irq_level, fiq_level; |
cbe1282b LM |
165 | int cpu, cpu_iface; |
166 | int group = 0; | |
167 | qemu_irq *irq_lines = virt ? s->parent_virq : s->parent_irq; | |
168 | qemu_irq *fiq_lines = virt ? s->parent_vfiq : s->parent_fiq; | |
9ee6e8bb | 169 | |
b95690c9 | 170 | for (cpu = 0; cpu < s->num_cpu; cpu++) { |
cbe1282b LM |
171 | cpu_iface = virt ? (cpu + GIC_NCPU) : cpu; |
172 | ||
173 | s->current_pending[cpu_iface] = 1023; | |
174 | if (!gic_irq_signaling_enabled(s, cpu, virt, | |
175 | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) { | |
176 | qemu_irq_lower(irq_lines[cpu]); | |
177 | qemu_irq_lower(fiq_lines[cpu]); | |
235069a3 | 178 | continue; |
9ee6e8bb | 179 | } |
cbe1282b LM |
180 | |
181 | if (virt) { | |
182 | gic_get_best_virq(s, cpu, &best_irq, &best_prio, &group); | |
183 | } else { | |
184 | gic_get_best_irq(s, cpu, &best_irq, &best_prio, &group); | |
e69954b9 | 185 | } |
dadbb58f | 186 | |
2531088f | 187 | if (best_irq != 1023) { |
067a2b9c LM |
188 | trace_gic_update_bestirq(virt ? "vcpu" : "cpu", cpu, |
189 | best_irq, best_prio, | |
190 | s->priority_mask[cpu_iface], | |
191 | s->running_priority[cpu_iface]); | |
2531088f HB |
192 | } |
193 | ||
dadbb58f PM |
194 | irq_level = fiq_level = 0; |
195 | ||
cbe1282b LM |
196 | if (best_prio < s->priority_mask[cpu_iface]) { |
197 | s->current_pending[cpu_iface] = best_irq; | |
198 | if (best_prio < s->running_priority[cpu_iface]) { | |
199 | if (gic_irq_signaling_enabled(s, cpu, virt, 1 << group)) { | |
200 | if (group == 0 && | |
201 | s->cpu_ctlr[cpu_iface] & GICC_CTLR_FIQ_EN) { | |
dadbb58f | 202 | DPRINTF("Raised pending FIQ %d (cpu %d)\n", |
cbe1282b | 203 | best_irq, cpu_iface); |
dadbb58f | 204 | fiq_level = 1; |
cbe1282b LM |
205 | trace_gic_update_set_irq(cpu, virt ? "vfiq" : "fiq", |
206 | fiq_level); | |
dadbb58f PM |
207 | } else { |
208 | DPRINTF("Raised pending IRQ %d (cpu %d)\n", | |
cbe1282b | 209 | best_irq, cpu_iface); |
dadbb58f | 210 | irq_level = 1; |
cbe1282b LM |
211 | trace_gic_update_set_irq(cpu, virt ? "virq" : "irq", |
212 | irq_level); | |
dadbb58f PM |
213 | } |
214 | } | |
9ee6e8bb | 215 | } |
e69954b9 | 216 | } |
dadbb58f | 217 | |
cbe1282b LM |
218 | qemu_set_irq(irq_lines[cpu], irq_level); |
219 | qemu_set_irq(fiq_lines[cpu], fiq_level); | |
e69954b9 PB |
220 | } |
221 | } | |
222 | ||
cbe1282b LM |
223 | static void gic_update(GICState *s) |
224 | { | |
225 | gic_update_internal(s, false); | |
226 | } | |
227 | ||
527d296f LM |
228 | /* Return true if this LR is empty, i.e. the corresponding bit |
229 | * in ELRSR is set. | |
230 | */ | |
231 | static inline bool gic_lr_entry_is_free(uint32_t entry) | |
232 | { | |
233 | return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID) | |
234 | && (GICH_LR_HW(entry) || !GICH_LR_EOI(entry)); | |
235 | } | |
236 | ||
237 | /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the | |
238 | * corrsponding bit in EISR is set. | |
239 | */ | |
240 | static inline bool gic_lr_entry_is_eoi(uint32_t entry) | |
241 | { | |
242 | return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID) | |
243 | && !GICH_LR_HW(entry) && GICH_LR_EOI(entry); | |
244 | } | |
245 | ||
50e57926 LM |
246 | static inline void gic_extract_lr_info(GICState *s, int cpu, |
247 | int *num_eoi, int *num_valid, int *num_pending) | |
248 | { | |
249 | int lr_idx; | |
250 | ||
251 | *num_eoi = 0; | |
252 | *num_valid = 0; | |
253 | *num_pending = 0; | |
254 | ||
255 | for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { | |
256 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; | |
257 | ||
258 | if (gic_lr_entry_is_eoi(*entry)) { | |
259 | (*num_eoi)++; | |
260 | } | |
261 | ||
262 | if (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID) { | |
263 | (*num_valid)++; | |
264 | } | |
265 | ||
266 | if (GICH_LR_STATE(*entry) == GICH_LR_STATE_PENDING) { | |
267 | (*num_pending)++; | |
268 | } | |
269 | } | |
270 | } | |
271 | ||
272 | static void gic_compute_misr(GICState *s, int cpu) | |
273 | { | |
274 | uint32_t value = 0; | |
275 | int vcpu = cpu + GIC_NCPU; | |
276 | ||
277 | int num_eoi, num_valid, num_pending; | |
278 | ||
279 | gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending); | |
280 | ||
281 | /* EOI */ | |
282 | if (num_eoi) { | |
283 | value |= R_GICH_MISR_EOI_MASK; | |
284 | } | |
285 | ||
286 | /* U: true if only 0 or 1 LR entry is valid */ | |
287 | if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { | |
288 | value |= R_GICH_MISR_U_MASK; | |
289 | } | |
290 | ||
291 | /* LRENP: EOICount is not 0 */ | |
292 | if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && | |
293 | ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) { | |
294 | value |= R_GICH_MISR_LRENP_MASK; | |
295 | } | |
296 | ||
297 | /* NP: no pending interrupts */ | |
298 | if ((s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK) && (num_pending == 0)) { | |
299 | value |= R_GICH_MISR_NP_MASK; | |
300 | } | |
301 | ||
302 | /* VGrp0E: group0 virq signaling enabled */ | |
303 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && | |
304 | (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { | |
305 | value |= R_GICH_MISR_VGrp0E_MASK; | |
306 | } | |
307 | ||
308 | /* VGrp0D: group0 virq signaling disabled */ | |
309 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && | |
310 | !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { | |
311 | value |= R_GICH_MISR_VGrp0D_MASK; | |
312 | } | |
313 | ||
314 | /* VGrp1E: group1 virq signaling enabled */ | |
315 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && | |
316 | (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { | |
317 | value |= R_GICH_MISR_VGrp1E_MASK; | |
318 | } | |
319 | ||
320 | /* VGrp1D: group1 virq signaling disabled */ | |
321 | if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && | |
322 | !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { | |
323 | value |= R_GICH_MISR_VGrp1D_MASK; | |
324 | } | |
325 | ||
326 | s->h_misr[cpu] = value; | |
327 | } | |
328 | ||
329 | static void gic_update_maintenance(GICState *s) | |
330 | { | |
331 | int cpu = 0; | |
332 | int maint_level; | |
333 | ||
334 | for (cpu = 0; cpu < s->num_cpu; cpu++) { | |
335 | gic_compute_misr(s, cpu); | |
336 | maint_level = (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[cpu]; | |
337 | ||
067a2b9c | 338 | trace_gic_update_maintenance_irq(cpu, maint_level); |
50e57926 LM |
339 | qemu_set_irq(s->maintenance_irq[cpu], maint_level); |
340 | } | |
341 | } | |
342 | ||
cbe1282b LM |
343 | static void gic_update_virt(GICState *s) |
344 | { | |
345 | gic_update_internal(s, true); | |
50e57926 | 346 | gic_update_maintenance(s); |
cbe1282b LM |
347 | } |
348 | ||
8d999995 CD |
349 | static void gic_set_irq_11mpcore(GICState *s, int irq, int level, |
350 | int cm, int target) | |
351 | { | |
352 | if (level) { | |
67ce697a LM |
353 | GIC_DIST_SET_LEVEL(irq, cm); |
354 | if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { | |
8d999995 | 355 | DPRINTF("Set %d pending mask %x\n", irq, target); |
67ce697a | 356 | GIC_DIST_SET_PENDING(irq, target); |
8d999995 CD |
357 | } |
358 | } else { | |
67ce697a | 359 | GIC_DIST_CLEAR_LEVEL(irq, cm); |
8d999995 CD |
360 | } |
361 | } | |
362 | ||
363 | static void gic_set_irq_generic(GICState *s, int irq, int level, | |
364 | int cm, int target) | |
365 | { | |
366 | if (level) { | |
67ce697a | 367 | GIC_DIST_SET_LEVEL(irq, cm); |
8d999995 | 368 | DPRINTF("Set %d pending mask %x\n", irq, target); |
67ce697a LM |
369 | if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { |
370 | GIC_DIST_SET_PENDING(irq, target); | |
8d999995 CD |
371 | } |
372 | } else { | |
67ce697a | 373 | GIC_DIST_CLEAR_LEVEL(irq, cm); |
8d999995 CD |
374 | } |
375 | } | |
376 | ||
9ee6e8bb | 377 | /* Process a change in an external IRQ input. */ |
e69954b9 PB |
378 | static void gic_set_irq(void *opaque, int irq, int level) |
379 | { | |
544d1afa PM |
380 | /* Meaning of the 'irq' parameter: |
381 | * [0..N-1] : external interrupts | |
382 | * [N..N+31] : PPI (internal) interrupts for CPU 0 | |
383 | * [N+32..N+63] : PPI (internal interrupts for CPU 1 | |
384 | * ... | |
385 | */ | |
fae15286 | 386 | GICState *s = (GICState *)opaque; |
544d1afa PM |
387 | int cm, target; |
388 | if (irq < (s->num_irq - GIC_INTERNAL)) { | |
389 | /* The first external input line is internal interrupt 32. */ | |
390 | cm = ALL_CPU_MASK; | |
391 | irq += GIC_INTERNAL; | |
67ce697a | 392 | target = GIC_DIST_TARGET(irq); |
544d1afa PM |
393 | } else { |
394 | int cpu; | |
395 | irq -= (s->num_irq - GIC_INTERNAL); | |
396 | cpu = irq / GIC_INTERNAL; | |
397 | irq %= GIC_INTERNAL; | |
398 | cm = 1 << cpu; | |
399 | target = cm; | |
400 | } | |
401 | ||
40d22500 CD |
402 | assert(irq >= GIC_NR_SGIS); |
403 | ||
67ce697a | 404 | if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { |
e69954b9 | 405 | return; |
544d1afa | 406 | } |
e69954b9 | 407 | |
3bc4b52c | 408 | if (s->revision == REV_11MPCORE) { |
8d999995 | 409 | gic_set_irq_11mpcore(s, irq, level, cm, target); |
e69954b9 | 410 | } else { |
8d999995 | 411 | gic_set_irq_generic(s, irq, level, cm, target); |
e69954b9 | 412 | } |
2531088f | 413 | trace_gic_set_irq(irq, level, cm, target); |
8d999995 | 414 | |
e69954b9 PB |
415 | gic_update(s); |
416 | } | |
417 | ||
7c0fa108 FA |
418 | static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, |
419 | MemTxAttrs attrs) | |
420 | { | |
421 | uint16_t pending_irq = s->current_pending[cpu]; | |
422 | ||
423 | if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { | |
86b350f0 LM |
424 | int group = gic_test_group(s, pending_irq, cpu); |
425 | ||
7c0fa108 FA |
426 | /* On a GIC without the security extensions, reading this register |
427 | * behaves in the same way as a secure access to a GIC with them. | |
428 | */ | |
3dd0471b | 429 | bool secure = !gic_cpu_ns_access(s, cpu, attrs); |
7c0fa108 FA |
430 | |
431 | if (group == 0 && !secure) { | |
432 | /* Group0 interrupts hidden from Non-secure access */ | |
433 | return 1023; | |
434 | } | |
435 | if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { | |
436 | /* Group1 interrupts only seen by Secure access if | |
437 | * AckCtl bit set. | |
438 | */ | |
439 | return 1022; | |
440 | } | |
441 | } | |
442 | return pending_irq; | |
443 | } | |
444 | ||
df92cfa6 PM |
445 | static int gic_get_group_priority(GICState *s, int cpu, int irq) |
446 | { | |
447 | /* Return the group priority of the specified interrupt | |
448 | * (which is the top bits of its priority, with the number | |
449 | * of bits masked determined by the applicable binary point register). | |
450 | */ | |
451 | int bpr; | |
452 | uint32_t mask; | |
453 | ||
454 | if (gic_has_groups(s) && | |
455 | !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && | |
86b350f0 | 456 | gic_test_group(s, irq, cpu)) { |
fc05a6f2 LM |
457 | bpr = s->abpr[cpu] - 1; |
458 | assert(bpr >= 0); | |
df92cfa6 PM |
459 | } else { |
460 | bpr = s->bpr[cpu]; | |
461 | } | |
462 | ||
463 | /* a BPR of 0 means the group priority bits are [7:1]; | |
464 | * a BPR of 1 means they are [7:2], and so on down to | |
465 | * a BPR of 7 meaning no group priority bits at all. | |
466 | */ | |
467 | mask = ~0U << ((bpr & 7) + 1); | |
468 | ||
86b350f0 | 469 | return gic_get_priority(s, irq, cpu) & mask; |
df92cfa6 PM |
470 | } |
471 | ||
72889c8a | 472 | static void gic_activate_irq(GICState *s, int cpu, int irq) |
e69954b9 | 473 | { |
72889c8a PM |
474 | /* Set the appropriate Active Priority Register bit for this IRQ, |
475 | * and update the running priority. | |
476 | */ | |
477 | int prio = gic_get_group_priority(s, cpu, irq); | |
a1d7b8d8 LM |
478 | int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; |
479 | int preemption_level = prio >> (min_bpr + 1); | |
72889c8a PM |
480 | int regno = preemption_level / 32; |
481 | int bitno = preemption_level % 32; | |
a1d7b8d8 | 482 | uint32_t *papr = NULL; |
72889c8a | 483 | |
a1d7b8d8 LM |
484 | if (gic_is_vcpu(cpu)) { |
485 | assert(regno == 0); | |
486 | papr = &s->h_apr[gic_get_vcpu_real_id(cpu)]; | |
487 | } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { | |
488 | papr = &s->nsapr[regno][cpu]; | |
9ee6e8bb | 489 | } else { |
a1d7b8d8 | 490 | papr = &s->apr[regno][cpu]; |
9ee6e8bb | 491 | } |
72889c8a | 492 | |
a1d7b8d8 LM |
493 | *papr |= (1 << bitno); |
494 | ||
72889c8a | 495 | s->running_priority[cpu] = prio; |
86b350f0 | 496 | gic_set_active(s, irq, cpu); |
72889c8a PM |
497 | } |
498 | ||
499 | static int gic_get_prio_from_apr_bits(GICState *s, int cpu) | |
500 | { | |
501 | /* Recalculate the current running priority for this CPU based | |
502 | * on the set bits in the Active Priority Registers. | |
503 | */ | |
504 | int i; | |
a1d7b8d8 LM |
505 | |
506 | if (gic_is_vcpu(cpu)) { | |
507 | uint32_t apr = s->h_apr[gic_get_vcpu_real_id(cpu)]; | |
508 | if (apr) { | |
509 | return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1); | |
510 | } else { | |
511 | return 0x100; | |
512 | } | |
513 | } | |
514 | ||
72889c8a PM |
515 | for (i = 0; i < GIC_NR_APRS; i++) { |
516 | uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu]; | |
517 | if (!apr) { | |
518 | continue; | |
519 | } | |
520 | return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); | |
521 | } | |
522 | return 0x100; | |
523 | } | |
524 | ||
525 | static void gic_drop_prio(GICState *s, int cpu, int group) | |
526 | { | |
527 | /* Drop the priority of the currently active interrupt in the | |
528 | * specified group. | |
529 | * | |
530 | * Note that we can guarantee (because of the requirement to nest | |
531 | * GICC_IAR reads [which activate an interrupt and raise priority] | |
532 | * with GICC_EOIR writes [which drop the priority for the interrupt]) | |
533 | * that the interrupt we're being called for is the highest priority | |
534 | * active interrupt, meaning that it has the lowest set bit in the | |
535 | * APR registers. | |
536 | * | |
537 | * If the guest does not honour the ordering constraints then the | |
538 | * behaviour of the GIC is UNPREDICTABLE, which for us means that | |
539 | * the values of the APR registers might become incorrect and the | |
540 | * running priority will be wrong, so interrupts that should preempt | |
541 | * might not do so, and interrupts that should not preempt might do so. | |
542 | */ | |
a1d7b8d8 LM |
543 | if (gic_is_vcpu(cpu)) { |
544 | int rcpu = gic_get_vcpu_real_id(cpu); | |
72889c8a | 545 | |
a1d7b8d8 LM |
546 | if (s->h_apr[rcpu]) { |
547 | /* Clear lowest set bit */ | |
548 | s->h_apr[rcpu] &= s->h_apr[rcpu] - 1; | |
549 | } | |
550 | } else { | |
551 | int i; | |
552 | ||
553 | for (i = 0; i < GIC_NR_APRS; i++) { | |
554 | uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; | |
555 | if (!*papr) { | |
556 | continue; | |
557 | } | |
558 | /* Clear lowest set bit */ | |
559 | *papr &= *papr - 1; | |
560 | break; | |
72889c8a | 561 | } |
72889c8a PM |
562 | } |
563 | ||
564 | s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu); | |
e69954b9 PB |
565 | } |
566 | ||
439badd6 LM |
567 | static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu) |
568 | { | |
569 | int src; | |
570 | uint32_t ret; | |
571 | ||
572 | if (!gic_is_vcpu(cpu)) { | |
573 | /* Lookup the source CPU for the SGI and clear this in the | |
574 | * sgi_pending map. Return the src and clear the overall pending | |
575 | * state on this CPU if the SGI is not pending from any CPUs. | |
576 | */ | |
577 | assert(s->sgi_pending[irq][cpu] != 0); | |
578 | src = ctz32(s->sgi_pending[irq][cpu]); | |
579 | s->sgi_pending[irq][cpu] &= ~(1 << src); | |
580 | if (s->sgi_pending[irq][cpu] == 0) { | |
581 | gic_clear_pending(s, irq, cpu); | |
582 | } | |
583 | ret = irq | ((src & 0x7) << 10); | |
584 | } else { | |
585 | uint32_t *lr_entry = gic_get_lr_entry(s, irq, cpu); | |
586 | src = GICH_LR_CPUID(*lr_entry); | |
587 | ||
588 | gic_clear_pending(s, irq, cpu); | |
589 | ret = irq | (src << 10); | |
590 | } | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
c5619bf9 | 595 | uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) |
e69954b9 | 596 | { |
439badd6 | 597 | int ret, irq; |
c5619bf9 FA |
598 | |
599 | /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately | |
600 | * for the case where this GIC supports grouping and the pending interrupt | |
601 | * is in the wrong group. | |
602 | */ | |
a8f15a27 | 603 | irq = gic_get_current_pending_irq(s, cpu, attrs); |
067a2b9c LM |
604 | trace_gic_acknowledge_irq(gic_is_vcpu(cpu) ? "vcpu" : "cpu", |
605 | gic_get_vcpu_real_id(cpu), irq); | |
c5619bf9 FA |
606 | |
607 | if (irq >= GIC_MAXIRQ) { | |
608 | DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); | |
609 | return irq; | |
610 | } | |
611 | ||
86b350f0 | 612 | if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) { |
c5619bf9 | 613 | DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); |
e69954b9 PB |
614 | return 1023; |
615 | } | |
40d22500 | 616 | |
439badd6 LM |
617 | gic_activate_irq(s, cpu, irq); |
618 | ||
7c14b3ac | 619 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
620 | /* Clear pending flags for both level and edge triggered interrupts. |
621 | * Level triggered IRQs will be reasserted once they become inactive. | |
622 | */ | |
86b350f0 | 623 | gic_clear_pending(s, irq, cpu); |
40d22500 CD |
624 | ret = irq; |
625 | } else { | |
626 | if (irq < GIC_NR_SGIS) { | |
439badd6 | 627 | ret = gic_clear_pending_sgi(s, irq, cpu); |
40d22500 | 628 | } else { |
86b350f0 | 629 | gic_clear_pending(s, irq, cpu); |
40d22500 CD |
630 | ret = irq; |
631 | } | |
632 | } | |
633 | ||
cbe1282b LM |
634 | if (gic_is_vcpu(cpu)) { |
635 | gic_update_virt(s); | |
636 | } else { | |
637 | gic_update(s); | |
638 | } | |
40d22500 CD |
639 | DPRINTF("ACK %d\n", irq); |
640 | return ret; | |
e69954b9 PB |
641 | } |
642 | ||
67ce697a | 643 | void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, |
81508470 | 644 | MemTxAttrs attrs) |
9df90ad0 | 645 | { |
81508470 | 646 | if (s->security_extn && !attrs.secure) { |
67ce697a | 647 | if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { |
81508470 FA |
648 | return; /* Ignore Non-secure access of Group0 IRQ */ |
649 | } | |
650 | val = 0x80 | (val >> 1); /* Non-secure view */ | |
651 | } | |
652 | ||
9df90ad0 CD |
653 | if (irq < GIC_INTERNAL) { |
654 | s->priority1[irq][cpu] = val; | |
655 | } else { | |
656 | s->priority2[(irq) - GIC_INTERNAL] = val; | |
657 | } | |
658 | } | |
659 | ||
67ce697a | 660 | static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, |
81508470 FA |
661 | MemTxAttrs attrs) |
662 | { | |
67ce697a | 663 | uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); |
81508470 FA |
664 | |
665 | if (s->security_extn && !attrs.secure) { | |
67ce697a | 666 | if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { |
81508470 FA |
667 | return 0; /* Non-secure access cannot read priority of Group0 IRQ */ |
668 | } | |
669 | prio = (prio << 1) & 0xff; /* Non-secure view */ | |
670 | } | |
671 | return prio; | |
672 | } | |
673 | ||
674 | static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, | |
675 | MemTxAttrs attrs) | |
676 | { | |
3dd0471b | 677 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
81508470 FA |
678 | if (s->priority_mask[cpu] & 0x80) { |
679 | /* Priority Mask in upper half */ | |
680 | pmask = 0x80 | (pmask >> 1); | |
681 | } else { | |
682 | /* Non-secure write ignored if priority mask is in lower half */ | |
683 | return; | |
684 | } | |
685 | } | |
686 | s->priority_mask[cpu] = pmask; | |
687 | } | |
688 | ||
689 | static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) | |
690 | { | |
691 | uint32_t pmask = s->priority_mask[cpu]; | |
692 | ||
3dd0471b | 693 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
81508470 FA |
694 | if (pmask & 0x80) { |
695 | /* Priority Mask in upper half, return Non-secure view */ | |
696 | pmask = (pmask << 1) & 0xff; | |
697 | } else { | |
698 | /* Priority Mask in lower half, RAZ */ | |
699 | pmask = 0; | |
700 | } | |
701 | } | |
702 | return pmask; | |
703 | } | |
704 | ||
32951860 FA |
705 | static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs) |
706 | { | |
707 | uint32_t ret = s->cpu_ctlr[cpu]; | |
708 | ||
3dd0471b | 709 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
32951860 FA |
710 | /* Construct the NS banked view of GICC_CTLR from the correct |
711 | * bits of the S banked view. We don't need to move the bypass | |
712 | * control bits because we don't implement that (IMPDEF) part | |
713 | * of the GIC architecture. | |
714 | */ | |
715 | ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1; | |
716 | } | |
717 | return ret; | |
718 | } | |
719 | ||
720 | static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, | |
721 | MemTxAttrs attrs) | |
722 | { | |
723 | uint32_t mask; | |
724 | ||
3dd0471b | 725 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
32951860 FA |
726 | /* The NS view can only write certain bits in the register; |
727 | * the rest are unchanged | |
728 | */ | |
729 | mask = GICC_CTLR_EN_GRP1; | |
730 | if (s->revision == 2) { | |
731 | mask |= GICC_CTLR_EOIMODE_NS; | |
732 | } | |
733 | s->cpu_ctlr[cpu] &= ~mask; | |
734 | s->cpu_ctlr[cpu] |= (value << 1) & mask; | |
735 | } else { | |
736 | if (s->revision == 2) { | |
737 | mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK; | |
738 | } else { | |
739 | mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK; | |
740 | } | |
741 | s->cpu_ctlr[cpu] = value & mask; | |
742 | } | |
743 | DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, " | |
744 | "Group1 Interrupts %sabled\n", cpu, | |
745 | (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis", | |
746 | (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis"); | |
747 | } | |
748 | ||
08efa9f2 FA |
749 | static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) |
750 | { | |
71aa735b LM |
751 | if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { |
752 | /* Idle priority */ | |
753 | return 0xff; | |
754 | } | |
755 | ||
3dd0471b | 756 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
08efa9f2 FA |
757 | if (s->running_priority[cpu] & 0x80) { |
758 | /* Running priority in upper half of range: return the Non-secure | |
759 | * view of the priority. | |
760 | */ | |
761 | return s->running_priority[cpu] << 1; | |
762 | } else { | |
763 | /* Running priority in lower half of range: RAZ */ | |
764 | return 0; | |
765 | } | |
766 | } else { | |
767 | return s->running_priority[cpu]; | |
768 | } | |
769 | } | |
770 | ||
a55c910e PM |
771 | /* Return true if we should split priority drop and interrupt deactivation, |
772 | * ie whether the relevant EOIMode bit is set. | |
773 | */ | |
774 | static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs) | |
775 | { | |
776 | if (s->revision != 2) { | |
777 | /* Before GICv2 prio-drop and deactivate are not separable */ | |
778 | return false; | |
779 | } | |
3dd0471b | 780 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
a55c910e PM |
781 | return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS; |
782 | } | |
783 | return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE; | |
784 | } | |
785 | ||
786 | static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) | |
787 | { | |
ee03cca8 PM |
788 | int group; |
789 | ||
02f2e22d | 790 | if (irq >= GIC_MAXIRQ || (!gic_is_vcpu(cpu) && irq >= s->num_irq)) { |
ee03cca8 PM |
791 | /* |
792 | * This handles two cases: | |
793 | * 1. If software writes the ID of a spurious interrupt [ie 1023] | |
794 | * to the GICC_DIR, the GIC ignores that write. | |
795 | * 2. If software writes the number of a non-existent interrupt | |
796 | * this must be a subcase of "value written is not an active interrupt" | |
02f2e22d LM |
797 | * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs, |
798 | * all IRQs potentially exist, so this limit does not apply. | |
ee03cca8 PM |
799 | */ |
800 | return; | |
801 | } | |
802 | ||
a55c910e PM |
803 | if (!gic_eoi_split(s, cpu, attrs)) { |
804 | /* This is UNPREDICTABLE; we choose to ignore it */ | |
805 | qemu_log_mask(LOG_GUEST_ERROR, | |
806 | "gic_deactivate_irq: GICC_DIR write when EOIMode clear"); | |
807 | return; | |
808 | } | |
809 | ||
02f2e22d LM |
810 | if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) { |
811 | /* This vIRQ does not have an LR entry which is either active or | |
812 | * pending and active. Increment EOICount and ignore the write. | |
813 | */ | |
814 | int rcpu = gic_get_vcpu_real_id(cpu); | |
815 | s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; | |
cbe1282b LM |
816 | |
817 | /* Update the virtual interface in case a maintenance interrupt should | |
818 | * be raised. | |
819 | */ | |
820 | gic_update_virt(s); | |
02f2e22d LM |
821 | return; |
822 | } | |
823 | ||
824 | group = gic_has_groups(s) && gic_test_group(s, irq, cpu); | |
825 | ||
3dd0471b | 826 | if (gic_cpu_ns_access(s, cpu, attrs) && !group) { |
a55c910e PM |
827 | DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); |
828 | return; | |
829 | } | |
830 | ||
86b350f0 | 831 | gic_clear_active(s, irq, cpu); |
a55c910e PM |
832 | } |
833 | ||
50491c56 | 834 | static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) |
e69954b9 | 835 | { |
9ee6e8bb | 836 | int cm = 1 << cpu; |
72889c8a PM |
837 | int group; |
838 | ||
df628ff1 | 839 | DPRINTF("EOI %d\n", irq); |
02f2e22d LM |
840 | if (gic_is_vcpu(cpu)) { |
841 | /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the | |
842 | * running prio is < 0x100. | |
843 | */ | |
844 | bool prio_drop = s->running_priority[cpu] < 0x100; | |
845 | ||
846 | if (irq >= GIC_MAXIRQ) { | |
847 | /* Ignore spurious interrupt */ | |
848 | return; | |
849 | } | |
850 | ||
851 | gic_drop_prio(s, cpu, 0); | |
852 | ||
853 | if (!gic_eoi_split(s, cpu, attrs)) { | |
854 | bool valid = gic_virq_is_valid(s, irq, cpu); | |
855 | if (prio_drop && !valid) { | |
856 | /* We are in a situation where: | |
857 | * - V_CTRL.EOIMode is false (no EOI split), | |
858 | * - The call to gic_drop_prio() cleared a bit in GICH_APR, | |
859 | * - This vIRQ does not have an LR entry which is either | |
860 | * active or pending and active. | |
861 | * In that case, we must increment EOICount. | |
862 | */ | |
863 | int rcpu = gic_get_vcpu_real_id(cpu); | |
864 | s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT; | |
865 | } else if (valid) { | |
866 | gic_clear_active(s, irq, cpu); | |
867 | } | |
868 | } | |
869 | ||
cbe1282b | 870 | gic_update_virt(s); |
02f2e22d LM |
871 | return; |
872 | } | |
873 | ||
a32134aa | 874 | if (irq >= s->num_irq) { |
217bfb44 PM |
875 | /* This handles two cases: |
876 | * 1. If software writes the ID of a spurious interrupt [ie 1023] | |
877 | * to the GICC_EOIR, the GIC ignores that write. | |
878 | * 2. If software writes the number of a non-existent interrupt | |
879 | * this must be a subcase of "value written does not match the last | |
880 | * valid interrupt value read from the Interrupt Acknowledge | |
881 | * register" and so this is UNPREDICTABLE. We choose to ignore it. | |
882 | */ | |
883 | return; | |
884 | } | |
72889c8a | 885 | if (s->running_priority[cpu] == 0x100) { |
e69954b9 | 886 | return; /* No active IRQ. */ |
72889c8a | 887 | } |
8d999995 | 888 | |
3bc4b52c | 889 | if (s->revision == REV_11MPCORE) { |
8d999995 CD |
890 | /* Mark level triggered interrupts as pending if they are still |
891 | raised. */ | |
67ce697a LM |
892 | if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) |
893 | && GIC_DIST_TEST_LEVEL(irq, cm) | |
894 | && (GIC_DIST_TARGET(irq) & cm) != 0) { | |
8d999995 | 895 | DPRINTF("Set %d pending mask %x\n", irq, cm); |
67ce697a | 896 | GIC_DIST_SET_PENDING(irq, cm); |
8d999995 | 897 | } |
e69954b9 | 898 | } |
8d999995 | 899 | |
86b350f0 | 900 | group = gic_has_groups(s) && gic_test_group(s, irq, cpu); |
72889c8a | 901 | |
3dd0471b | 902 | if (gic_cpu_ns_access(s, cpu, attrs) && !group) { |
f9c6a7f1 FA |
903 | DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); |
904 | return; | |
905 | } | |
906 | ||
907 | /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1 | |
908 | * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1, | |
909 | * i.e. go ahead and complete the irq anyway. | |
910 | */ | |
911 | ||
72889c8a | 912 | gic_drop_prio(s, cpu, group); |
a55c910e PM |
913 | |
914 | /* In GICv2 the guest can choose to split priority-drop and deactivate */ | |
915 | if (!gic_eoi_split(s, cpu, attrs)) { | |
86b350f0 | 916 | gic_clear_active(s, irq, cpu); |
a55c910e | 917 | } |
72889c8a | 918 | gic_update(s); |
e69954b9 PB |
919 | } |
920 | ||
a9d85353 | 921 | static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) |
e69954b9 | 922 | { |
fae15286 | 923 | GICState *s = (GICState *)opaque; |
e69954b9 PB |
924 | uint32_t res; |
925 | int irq; | |
926 | int i; | |
9ee6e8bb PB |
927 | int cpu; |
928 | int cm; | |
929 | int mask; | |
e69954b9 | 930 | |
926c4aff | 931 | cpu = gic_get_current_cpu(s); |
9ee6e8bb | 932 | cm = 1 << cpu; |
e69954b9 | 933 | if (offset < 0x100) { |
679aa175 FA |
934 | if (offset == 0) { /* GICD_CTLR */ |
935 | if (s->security_extn && !attrs.secure) { | |
936 | /* The NS bank of this register is just an alias of the | |
937 | * EnableGrp1 bit in the S bank version. | |
938 | */ | |
939 | return extract32(s->ctlr, 1, 1); | |
940 | } else { | |
941 | return s->ctlr; | |
942 | } | |
943 | } | |
e69954b9 | 944 | if (offset == 4) |
5543d1ab FA |
945 | /* Interrupt Controller Type Register */ |
946 | return ((s->num_irq / 32) - 1) | |
b95690c9 | 947 | | ((s->num_cpu - 1) << 5) |
5543d1ab | 948 | | (s->security_extn << 10); |
e69954b9 PB |
949 | if (offset < 0x08) |
950 | return 0; | |
b79f2265 | 951 | if (offset >= 0x80) { |
c27a5ba9 FA |
952 | /* Interrupt Group Registers: these RAZ/WI if this is an NS |
953 | * access to a GIC with the security extensions, or if the GIC | |
954 | * doesn't have groups at all. | |
955 | */ | |
956 | res = 0; | |
957 | if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { | |
958 | /* Every byte offset holds 8 group status bits */ | |
b6e6c651 | 959 | irq = (offset - 0x080) * 8; |
c27a5ba9 FA |
960 | if (irq >= s->num_irq) { |
961 | goto bad_reg; | |
962 | } | |
963 | for (i = 0; i < 8; i++) { | |
67ce697a | 964 | if (GIC_DIST_TEST_GROUP(irq + i, cm)) { |
c27a5ba9 FA |
965 | res |= (1 << i); |
966 | } | |
967 | } | |
968 | } | |
969 | return res; | |
b79f2265 | 970 | } |
e69954b9 PB |
971 | goto bad_reg; |
972 | } else if (offset < 0x200) { | |
973 | /* Interrupt Set/Clear Enable. */ | |
974 | if (offset < 0x180) | |
975 | irq = (offset - 0x100) * 8; | |
976 | else | |
977 | irq = (offset - 0x180) * 8; | |
a32134aa | 978 | if (irq >= s->num_irq) |
e69954b9 PB |
979 | goto bad_reg; |
980 | res = 0; | |
981 | for (i = 0; i < 8; i++) { | |
fea8a08e | 982 | if (s->security_extn && !attrs.secure && |
67ce697a | 983 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
984 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
985 | } | |
986 | ||
67ce697a | 987 | if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { |
e69954b9 PB |
988 | res |= (1 << i); |
989 | } | |
990 | } | |
991 | } else if (offset < 0x300) { | |
992 | /* Interrupt Set/Clear Pending. */ | |
993 | if (offset < 0x280) | |
994 | irq = (offset - 0x200) * 8; | |
995 | else | |
996 | irq = (offset - 0x280) * 8; | |
a32134aa | 997 | if (irq >= s->num_irq) |
e69954b9 PB |
998 | goto bad_reg; |
999 | res = 0; | |
69253800 | 1000 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 1001 | for (i = 0; i < 8; i++) { |
fea8a08e | 1002 | if (s->security_extn && !attrs.secure && |
67ce697a | 1003 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1004 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1005 | } | |
1006 | ||
8d999995 | 1007 | if (gic_test_pending(s, irq + i, mask)) { |
e69954b9 PB |
1008 | res |= (1 << i); |
1009 | } | |
1010 | } | |
1011 | } else if (offset < 0x400) { | |
3bb0b038 LM |
1012 | /* Interrupt Set/Clear Active. */ |
1013 | if (offset < 0x380) { | |
1014 | irq = (offset - 0x300) * 8; | |
1015 | } else if (s->revision == 2) { | |
1016 | irq = (offset - 0x380) * 8; | |
1017 | } else { | |
1018 | goto bad_reg; | |
1019 | } | |
1020 | ||
a32134aa | 1021 | if (irq >= s->num_irq) |
e69954b9 PB |
1022 | goto bad_reg; |
1023 | res = 0; | |
69253800 | 1024 | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
e69954b9 | 1025 | for (i = 0; i < 8; i++) { |
fea8a08e | 1026 | if (s->security_extn && !attrs.secure && |
67ce697a | 1027 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1028 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1029 | } | |
1030 | ||
67ce697a | 1031 | if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { |
e69954b9 PB |
1032 | res |= (1 << i); |
1033 | } | |
1034 | } | |
1035 | } else if (offset < 0x800) { | |
1036 | /* Interrupt Priority. */ | |
b6e6c651 | 1037 | irq = (offset - 0x400); |
a32134aa | 1038 | if (irq >= s->num_irq) |
e69954b9 | 1039 | goto bad_reg; |
67ce697a | 1040 | res = gic_dist_get_priority(s, cpu, irq, attrs); |
e69954b9 PB |
1041 | } else if (offset < 0xc00) { |
1042 | /* Interrupt CPU Target. */ | |
6b9680bb PM |
1043 | if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { |
1044 | /* For uniprocessor GICs these RAZ/WI */ | |
1045 | res = 0; | |
9ee6e8bb | 1046 | } else { |
b6e6c651 | 1047 | irq = (offset - 0x800); |
6b9680bb PM |
1048 | if (irq >= s->num_irq) { |
1049 | goto bad_reg; | |
1050 | } | |
7995206d PM |
1051 | if (irq < 29 && s->revision == REV_11MPCORE) { |
1052 | res = 0; | |
1053 | } else if (irq < GIC_INTERNAL) { | |
6b9680bb PM |
1054 | res = cm; |
1055 | } else { | |
67ce697a | 1056 | res = GIC_DIST_TARGET(irq); |
6b9680bb | 1057 | } |
9ee6e8bb | 1058 | } |
e69954b9 PB |
1059 | } else if (offset < 0xf00) { |
1060 | /* Interrupt Configuration. */ | |
b6e6c651 | 1061 | irq = (offset - 0xc00) * 4; |
a32134aa | 1062 | if (irq >= s->num_irq) |
e69954b9 PB |
1063 | goto bad_reg; |
1064 | res = 0; | |
1065 | for (i = 0; i < 4; i++) { | |
fea8a08e | 1066 | if (s->security_extn && !attrs.secure && |
67ce697a | 1067 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1068 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1069 | } | |
1070 | ||
67ce697a | 1071 | if (GIC_DIST_TEST_MODEL(irq + i)) { |
e69954b9 | 1072 | res |= (1 << (i * 2)); |
67ce697a LM |
1073 | } |
1074 | if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { | |
e69954b9 | 1075 | res |= (2 << (i * 2)); |
67ce697a | 1076 | } |
e69954b9 | 1077 | } |
40d22500 CD |
1078 | } else if (offset < 0xf10) { |
1079 | goto bad_reg; | |
1080 | } else if (offset < 0xf30) { | |
7c14b3ac | 1081 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
1082 | goto bad_reg; |
1083 | } | |
1084 | ||
1085 | if (offset < 0xf20) { | |
1086 | /* GICD_CPENDSGIRn */ | |
1087 | irq = (offset - 0xf10); | |
1088 | } else { | |
1089 | irq = (offset - 0xf20); | |
1090 | /* GICD_SPENDSGIRn */ | |
1091 | } | |
1092 | ||
fea8a08e | 1093 | if (s->security_extn && !attrs.secure && |
67ce697a | 1094 | !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { |
fea8a08e JW |
1095 | res = 0; /* Ignore Non-secure access of Group0 IRQ */ |
1096 | } else { | |
1097 | res = s->sgi_pending[irq][cpu]; | |
1098 | } | |
3355c360 | 1099 | } else if (offset < 0xfd0) { |
e69954b9 | 1100 | goto bad_reg; |
3355c360 | 1101 | } else if (offset < 0x1000) { |
e69954b9 PB |
1102 | if (offset & 3) { |
1103 | res = 0; | |
1104 | } else { | |
3355c360 AF |
1105 | switch (s->revision) { |
1106 | case REV_11MPCORE: | |
1107 | res = gic_id_11mpcore[(offset - 0xfd0) >> 2]; | |
1108 | break; | |
1109 | case 1: | |
1110 | res = gic_id_gicv1[(offset - 0xfd0) >> 2]; | |
1111 | break; | |
1112 | case 2: | |
1113 | res = gic_id_gicv2[(offset - 0xfd0) >> 2]; | |
1114 | break; | |
3355c360 AF |
1115 | default: |
1116 | res = 0; | |
1117 | } | |
e69954b9 | 1118 | } |
3355c360 AF |
1119 | } else { |
1120 | g_assert_not_reached(); | |
e69954b9 PB |
1121 | } |
1122 | return res; | |
1123 | bad_reg: | |
8c8dc39f PM |
1124 | qemu_log_mask(LOG_GUEST_ERROR, |
1125 | "gic_dist_readb: Bad offset %x\n", (int)offset); | |
e69954b9 PB |
1126 | return 0; |
1127 | } | |
1128 | ||
a9d85353 PM |
1129 | static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, |
1130 | unsigned size, MemTxAttrs attrs) | |
e69954b9 | 1131 | { |
a9d85353 PM |
1132 | switch (size) { |
1133 | case 1: | |
1134 | *data = gic_dist_readb(opaque, offset, attrs); | |
067a2b9c | 1135 | break; |
a9d85353 PM |
1136 | case 2: |
1137 | *data = gic_dist_readb(opaque, offset, attrs); | |
1138 | *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; | |
067a2b9c | 1139 | break; |
a9d85353 PM |
1140 | case 4: |
1141 | *data = gic_dist_readb(opaque, offset, attrs); | |
1142 | *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; | |
1143 | *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; | |
1144 | *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; | |
067a2b9c | 1145 | break; |
a9d85353 PM |
1146 | default: |
1147 | return MEMTX_ERROR; | |
1148 | } | |
067a2b9c LM |
1149 | |
1150 | trace_gic_dist_read(offset, size, *data); | |
1151 | return MEMTX_OK; | |
e69954b9 PB |
1152 | } |
1153 | ||
a8170e5e | 1154 | static void gic_dist_writeb(void *opaque, hwaddr offset, |
a9d85353 | 1155 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 1156 | { |
fae15286 | 1157 | GICState *s = (GICState *)opaque; |
e69954b9 PB |
1158 | int irq; |
1159 | int i; | |
9ee6e8bb | 1160 | int cpu; |
e69954b9 | 1161 | |
926c4aff | 1162 | cpu = gic_get_current_cpu(s); |
e69954b9 PB |
1163 | if (offset < 0x100) { |
1164 | if (offset == 0) { | |
679aa175 FA |
1165 | if (s->security_extn && !attrs.secure) { |
1166 | /* NS version is just an alias of the S version's bit 1 */ | |
1167 | s->ctlr = deposit32(s->ctlr, 1, 1, value); | |
1168 | } else if (gic_has_groups(s)) { | |
1169 | s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1); | |
1170 | } else { | |
1171 | s->ctlr = value & GICD_CTLR_EN_GRP0; | |
1172 | } | |
1173 | DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n", | |
1174 | s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis", | |
1175 | s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis"); | |
e69954b9 PB |
1176 | } else if (offset < 4) { |
1177 | /* ignored. */ | |
b79f2265 | 1178 | } else if (offset >= 0x80) { |
c27a5ba9 FA |
1179 | /* Interrupt Group Registers: RAZ/WI for NS access to secure |
1180 | * GIC, or for GICs without groups. | |
1181 | */ | |
1182 | if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) { | |
1183 | /* Every byte offset holds 8 group status bits */ | |
b6e6c651 | 1184 | irq = (offset - 0x80) * 8; |
c27a5ba9 FA |
1185 | if (irq >= s->num_irq) { |
1186 | goto bad_reg; | |
1187 | } | |
1188 | for (i = 0; i < 8; i++) { | |
1189 | /* Group bits are banked for private interrupts */ | |
1190 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; | |
1191 | if (value & (1 << i)) { | |
1192 | /* Group1 (Non-secure) */ | |
67ce697a | 1193 | GIC_DIST_SET_GROUP(irq + i, cm); |
c27a5ba9 FA |
1194 | } else { |
1195 | /* Group0 (Secure) */ | |
67ce697a | 1196 | GIC_DIST_CLEAR_GROUP(irq + i, cm); |
c27a5ba9 FA |
1197 | } |
1198 | } | |
1199 | } | |
e69954b9 PB |
1200 | } else { |
1201 | goto bad_reg; | |
1202 | } | |
1203 | } else if (offset < 0x180) { | |
1204 | /* Interrupt Set Enable. */ | |
b6e6c651 | 1205 | irq = (offset - 0x100) * 8; |
a32134aa | 1206 | if (irq >= s->num_irq) |
e69954b9 | 1207 | goto bad_reg; |
41ab7b55 CD |
1208 | if (irq < GIC_NR_SGIS) { |
1209 | value = 0xff; | |
1210 | } | |
1211 | ||
e69954b9 PB |
1212 | for (i = 0; i < 8; i++) { |
1213 | if (value & (1 << i)) { | |
f47b48fb | 1214 | int mask = |
67ce697a LM |
1215 | (irq < GIC_INTERNAL) ? (1 << cpu) |
1216 | : GIC_DIST_TARGET(irq + i); | |
69253800 | 1217 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
41bf234d | 1218 | |
fea8a08e | 1219 | if (s->security_extn && !attrs.secure && |
67ce697a | 1220 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1221 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1222 | } | |
1223 | ||
67ce697a | 1224 | if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { |
e69954b9 | 1225 | DPRINTF("Enabled IRQ %d\n", irq + i); |
2531088f | 1226 | trace_gic_enable_irq(irq + i); |
41bf234d | 1227 | } |
67ce697a | 1228 | GIC_DIST_SET_ENABLED(irq + i, cm); |
e69954b9 PB |
1229 | /* If a raised level triggered IRQ enabled then mark |
1230 | is as pending. */ | |
67ce697a LM |
1231 | if (GIC_DIST_TEST_LEVEL(irq + i, mask) |
1232 | && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { | |
9ee6e8bb | 1233 | DPRINTF("Set %d pending mask %x\n", irq + i, mask); |
67ce697a | 1234 | GIC_DIST_SET_PENDING(irq + i, mask); |
9ee6e8bb | 1235 | } |
e69954b9 PB |
1236 | } |
1237 | } | |
1238 | } else if (offset < 0x200) { | |
1239 | /* Interrupt Clear Enable. */ | |
b6e6c651 | 1240 | irq = (offset - 0x180) * 8; |
a32134aa | 1241 | if (irq >= s->num_irq) |
e69954b9 | 1242 | goto bad_reg; |
41ab7b55 CD |
1243 | if (irq < GIC_NR_SGIS) { |
1244 | value = 0; | |
1245 | } | |
1246 | ||
e69954b9 PB |
1247 | for (i = 0; i < 8; i++) { |
1248 | if (value & (1 << i)) { | |
69253800 | 1249 | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
41bf234d | 1250 | |
fea8a08e | 1251 | if (s->security_extn && !attrs.secure && |
67ce697a | 1252 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1253 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1254 | } | |
1255 | ||
67ce697a | 1256 | if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { |
e69954b9 | 1257 | DPRINTF("Disabled IRQ %d\n", irq + i); |
2531088f | 1258 | trace_gic_disable_irq(irq + i); |
41bf234d | 1259 | } |
67ce697a | 1260 | GIC_DIST_CLEAR_ENABLED(irq + i, cm); |
e69954b9 PB |
1261 | } |
1262 | } | |
1263 | } else if (offset < 0x280) { | |
1264 | /* Interrupt Set Pending. */ | |
b6e6c651 | 1265 | irq = (offset - 0x200) * 8; |
a32134aa | 1266 | if (irq >= s->num_irq) |
e69954b9 | 1267 | goto bad_reg; |
41ab7b55 | 1268 | if (irq < GIC_NR_SGIS) { |
5b0adce1 | 1269 | value = 0; |
41ab7b55 | 1270 | } |
9ee6e8bb | 1271 | |
e69954b9 PB |
1272 | for (i = 0; i < 8; i++) { |
1273 | if (value & (1 << i)) { | |
fea8a08e | 1274 | if (s->security_extn && !attrs.secure && |
67ce697a | 1275 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1276 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1277 | } | |
1278 | ||
67ce697a | 1279 | GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i)); |
e69954b9 PB |
1280 | } |
1281 | } | |
1282 | } else if (offset < 0x300) { | |
1283 | /* Interrupt Clear Pending. */ | |
b6e6c651 | 1284 | irq = (offset - 0x280) * 8; |
a32134aa | 1285 | if (irq >= s->num_irq) |
e69954b9 | 1286 | goto bad_reg; |
5b0adce1 CD |
1287 | if (irq < GIC_NR_SGIS) { |
1288 | value = 0; | |
1289 | } | |
1290 | ||
e69954b9 | 1291 | for (i = 0; i < 8; i++) { |
fea8a08e | 1292 | if (s->security_extn && !attrs.secure && |
67ce697a | 1293 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1294 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1295 | } | |
1296 | ||
9ee6e8bb PB |
1297 | /* ??? This currently clears the pending bit for all CPUs, even |
1298 | for per-CPU interrupts. It's unclear whether this is the | |
1299 | corect behavior. */ | |
e69954b9 | 1300 | if (value & (1 << i)) { |
67ce697a | 1301 | GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
e69954b9 PB |
1302 | } |
1303 | } | |
3bb0b038 LM |
1304 | } else if (offset < 0x380) { |
1305 | /* Interrupt Set Active. */ | |
1306 | if (s->revision != 2) { | |
1307 | goto bad_reg; | |
1308 | } | |
1309 | ||
b6e6c651 | 1310 | irq = (offset - 0x300) * 8; |
3bb0b038 LM |
1311 | if (irq >= s->num_irq) { |
1312 | goto bad_reg; | |
1313 | } | |
1314 | ||
1315 | /* This register is banked per-cpu for PPIs */ | |
1316 | int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; | |
1317 | ||
1318 | for (i = 0; i < 8; i++) { | |
1319 | if (s->security_extn && !attrs.secure && | |
1320 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { | |
1321 | continue; /* Ignore Non-secure access of Group0 IRQ */ | |
1322 | } | |
1323 | ||
1324 | if (value & (1 << i)) { | |
1325 | GIC_DIST_SET_ACTIVE(irq + i, cm); | |
1326 | } | |
1327 | } | |
e69954b9 | 1328 | } else if (offset < 0x400) { |
3bb0b038 LM |
1329 | /* Interrupt Clear Active. */ |
1330 | if (s->revision != 2) { | |
1331 | goto bad_reg; | |
1332 | } | |
1333 | ||
b6e6c651 | 1334 | irq = (offset - 0x380) * 8; |
3bb0b038 LM |
1335 | if (irq >= s->num_irq) { |
1336 | goto bad_reg; | |
1337 | } | |
1338 | ||
1339 | /* This register is banked per-cpu for PPIs */ | |
1340 | int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; | |
1341 | ||
1342 | for (i = 0; i < 8; i++) { | |
1343 | if (s->security_extn && !attrs.secure && | |
1344 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { | |
1345 | continue; /* Ignore Non-secure access of Group0 IRQ */ | |
1346 | } | |
1347 | ||
1348 | if (value & (1 << i)) { | |
1349 | GIC_DIST_CLEAR_ACTIVE(irq + i, cm); | |
1350 | } | |
1351 | } | |
e69954b9 PB |
1352 | } else if (offset < 0x800) { |
1353 | /* Interrupt Priority. */ | |
b6e6c651 | 1354 | irq = (offset - 0x400); |
a32134aa | 1355 | if (irq >= s->num_irq) |
e69954b9 | 1356 | goto bad_reg; |
67ce697a | 1357 | gic_dist_set_priority(s, cpu, irq, value, attrs); |
e69954b9 | 1358 | } else if (offset < 0xc00) { |
6b9680bb PM |
1359 | /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the |
1360 | * annoying exception of the 11MPCore's GIC. | |
1361 | */ | |
1362 | if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { | |
b6e6c651 | 1363 | irq = (offset - 0x800); |
6b9680bb PM |
1364 | if (irq >= s->num_irq) { |
1365 | goto bad_reg; | |
1366 | } | |
7995206d | 1367 | if (irq < 29 && s->revision == REV_11MPCORE) { |
6b9680bb PM |
1368 | value = 0; |
1369 | } else if (irq < GIC_INTERNAL) { | |
1370 | value = ALL_CPU_MASK; | |
1371 | } | |
1372 | s->irq_target[irq] = value & ALL_CPU_MASK; | |
1373 | } | |
e69954b9 PB |
1374 | } else if (offset < 0xf00) { |
1375 | /* Interrupt Configuration. */ | |
b6e6c651 | 1376 | irq = (offset - 0xc00) * 4; |
a32134aa | 1377 | if (irq >= s->num_irq) |
e69954b9 | 1378 | goto bad_reg; |
de7a900f | 1379 | if (irq < GIC_NR_SGIS) |
9ee6e8bb | 1380 | value |= 0xaa; |
e69954b9 | 1381 | for (i = 0; i < 4; i++) { |
fea8a08e | 1382 | if (s->security_extn && !attrs.secure && |
67ce697a | 1383 | !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { |
fea8a08e JW |
1384 | continue; /* Ignore Non-secure access of Group0 IRQ */ |
1385 | } | |
1386 | ||
7c14b3ac | 1387 | if (s->revision == REV_11MPCORE) { |
24b790df | 1388 | if (value & (1 << (i * 2))) { |
67ce697a | 1389 | GIC_DIST_SET_MODEL(irq + i); |
24b790df | 1390 | } else { |
67ce697a | 1391 | GIC_DIST_CLEAR_MODEL(irq + i); |
24b790df | 1392 | } |
e69954b9 PB |
1393 | } |
1394 | if (value & (2 << (i * 2))) { | |
67ce697a | 1395 | GIC_DIST_SET_EDGE_TRIGGER(irq + i); |
e69954b9 | 1396 | } else { |
67ce697a | 1397 | GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); |
e69954b9 PB |
1398 | } |
1399 | } | |
40d22500 | 1400 | } else if (offset < 0xf10) { |
9ee6e8bb | 1401 | /* 0xf00 is only handled for 32-bit writes. */ |
e69954b9 | 1402 | goto bad_reg; |
40d22500 CD |
1403 | } else if (offset < 0xf20) { |
1404 | /* GICD_CPENDSGIRn */ | |
7c14b3ac | 1405 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
1406 | goto bad_reg; |
1407 | } | |
1408 | irq = (offset - 0xf10); | |
1409 | ||
fea8a08e | 1410 | if (!s->security_extn || attrs.secure || |
67ce697a | 1411 | GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { |
fea8a08e JW |
1412 | s->sgi_pending[irq][cpu] &= ~value; |
1413 | if (s->sgi_pending[irq][cpu] == 0) { | |
67ce697a | 1414 | GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); |
fea8a08e | 1415 | } |
40d22500 CD |
1416 | } |
1417 | } else if (offset < 0xf30) { | |
1418 | /* GICD_SPENDSGIRn */ | |
7c14b3ac | 1419 | if (s->revision == REV_11MPCORE) { |
40d22500 CD |
1420 | goto bad_reg; |
1421 | } | |
1422 | irq = (offset - 0xf20); | |
1423 | ||
fea8a08e | 1424 | if (!s->security_extn || attrs.secure || |
67ce697a LM |
1425 | GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { |
1426 | GIC_DIST_SET_PENDING(irq, 1 << cpu); | |
fea8a08e JW |
1427 | s->sgi_pending[irq][cpu] |= value; |
1428 | } | |
40d22500 CD |
1429 | } else { |
1430 | goto bad_reg; | |
e69954b9 PB |
1431 | } |
1432 | gic_update(s); | |
1433 | return; | |
1434 | bad_reg: | |
8c8dc39f PM |
1435 | qemu_log_mask(LOG_GUEST_ERROR, |
1436 | "gic_dist_writeb: Bad offset %x\n", (int)offset); | |
e69954b9 PB |
1437 | } |
1438 | ||
a8170e5e | 1439 | static void gic_dist_writew(void *opaque, hwaddr offset, |
a9d85353 | 1440 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 1441 | { |
a9d85353 PM |
1442 | gic_dist_writeb(opaque, offset, value & 0xff, attrs); |
1443 | gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); | |
e69954b9 PB |
1444 | } |
1445 | ||
a8170e5e | 1446 | static void gic_dist_writel(void *opaque, hwaddr offset, |
a9d85353 | 1447 | uint32_t value, MemTxAttrs attrs) |
e69954b9 | 1448 | { |
fae15286 | 1449 | GICState *s = (GICState *)opaque; |
8da3ff18 | 1450 | if (offset == 0xf00) { |
9ee6e8bb PB |
1451 | int cpu; |
1452 | int irq; | |
1453 | int mask; | |
40d22500 | 1454 | int target_cpu; |
9ee6e8bb | 1455 | |
926c4aff | 1456 | cpu = gic_get_current_cpu(s); |
9ee6e8bb PB |
1457 | irq = value & 0x3ff; |
1458 | switch ((value >> 24) & 3) { | |
1459 | case 0: | |
1460 | mask = (value >> 16) & ALL_CPU_MASK; | |
1461 | break; | |
1462 | case 1: | |
fa250144 | 1463 | mask = ALL_CPU_MASK ^ (1 << cpu); |
9ee6e8bb PB |
1464 | break; |
1465 | case 2: | |
fa250144 | 1466 | mask = 1 << cpu; |
9ee6e8bb PB |
1467 | break; |
1468 | default: | |
1469 | DPRINTF("Bad Soft Int target filter\n"); | |
1470 | mask = ALL_CPU_MASK; | |
1471 | break; | |
1472 | } | |
67ce697a | 1473 | GIC_DIST_SET_PENDING(irq, mask); |
40d22500 CD |
1474 | target_cpu = ctz32(mask); |
1475 | while (target_cpu < GIC_NCPU) { | |
1476 | s->sgi_pending[irq][target_cpu] |= (1 << cpu); | |
1477 | mask &= ~(1 << target_cpu); | |
1478 | target_cpu = ctz32(mask); | |
1479 | } | |
9ee6e8bb PB |
1480 | gic_update(s); |
1481 | return; | |
1482 | } | |
a9d85353 PM |
1483 | gic_dist_writew(opaque, offset, value & 0xffff, attrs); |
1484 | gic_dist_writew(opaque, offset + 2, value >> 16, attrs); | |
1485 | } | |
1486 | ||
1487 | static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, | |
1488 | unsigned size, MemTxAttrs attrs) | |
1489 | { | |
067a2b9c LM |
1490 | trace_gic_dist_write(offset, size, data); |
1491 | ||
a9d85353 PM |
1492 | switch (size) { |
1493 | case 1: | |
1494 | gic_dist_writeb(opaque, offset, data, attrs); | |
1495 | return MEMTX_OK; | |
1496 | case 2: | |
1497 | gic_dist_writew(opaque, offset, data, attrs); | |
1498 | return MEMTX_OK; | |
1499 | case 4: | |
1500 | gic_dist_writel(opaque, offset, data, attrs); | |
1501 | return MEMTX_OK; | |
1502 | default: | |
1503 | return MEMTX_ERROR; | |
1504 | } | |
e69954b9 PB |
1505 | } |
1506 | ||
51fd06e0 PM |
1507 | static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno) |
1508 | { | |
1509 | /* Return the Nonsecure view of GICC_APR<regno>. This is the | |
1510 | * second half of GICC_NSAPR. | |
1511 | */ | |
1512 | switch (GIC_MIN_BPR) { | |
1513 | case 0: | |
1514 | if (regno < 2) { | |
1515 | return s->nsapr[regno + 2][cpu]; | |
1516 | } | |
1517 | break; | |
1518 | case 1: | |
1519 | if (regno == 0) { | |
1520 | return s->nsapr[regno + 1][cpu]; | |
1521 | } | |
1522 | break; | |
1523 | case 2: | |
1524 | if (regno == 0) { | |
1525 | return extract32(s->nsapr[0][cpu], 16, 16); | |
1526 | } | |
1527 | break; | |
1528 | case 3: | |
1529 | if (regno == 0) { | |
1530 | return extract32(s->nsapr[0][cpu], 8, 8); | |
1531 | } | |
1532 | break; | |
1533 | default: | |
1534 | g_assert_not_reached(); | |
1535 | } | |
1536 | return 0; | |
1537 | } | |
1538 | ||
1539 | static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno, | |
1540 | uint32_t value) | |
1541 | { | |
1542 | /* Write the Nonsecure view of GICC_APR<regno>. */ | |
1543 | switch (GIC_MIN_BPR) { | |
1544 | case 0: | |
1545 | if (regno < 2) { | |
1546 | s->nsapr[regno + 2][cpu] = value; | |
1547 | } | |
1548 | break; | |
1549 | case 1: | |
1550 | if (regno == 0) { | |
1551 | s->nsapr[regno + 1][cpu] = value; | |
1552 | } | |
1553 | break; | |
1554 | case 2: | |
1555 | if (regno == 0) { | |
1556 | s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value); | |
1557 | } | |
1558 | break; | |
1559 | case 3: | |
1560 | if (regno == 0) { | |
1561 | s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value); | |
1562 | } | |
1563 | break; | |
1564 | default: | |
1565 | g_assert_not_reached(); | |
1566 | } | |
1567 | } | |
1568 | ||
a9d85353 PM |
1569 | static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, |
1570 | uint64_t *data, MemTxAttrs attrs) | |
e69954b9 | 1571 | { |
e69954b9 PB |
1572 | switch (offset) { |
1573 | case 0x00: /* Control */ | |
32951860 | 1574 | *data = gic_get_cpu_control(s, cpu, attrs); |
a9d85353 | 1575 | break; |
e69954b9 | 1576 | case 0x04: /* Priority mask */ |
81508470 | 1577 | *data = gic_get_priority_mask(s, cpu, attrs); |
a9d85353 | 1578 | break; |
e69954b9 | 1579 | case 0x08: /* Binary Point */ |
3dd0471b | 1580 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
421a3c22 LM |
1581 | if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { |
1582 | /* NS view of BPR when CBPR is 1 */ | |
1583 | *data = MIN(s->bpr[cpu] + 1, 7); | |
1584 | } else { | |
1585 | /* BPR is banked. Non-secure copy stored in ABPR. */ | |
1586 | *data = s->abpr[cpu]; | |
1587 | } | |
822e9cc3 FA |
1588 | } else { |
1589 | *data = s->bpr[cpu]; | |
1590 | } | |
a9d85353 | 1591 | break; |
e69954b9 | 1592 | case 0x0c: /* Acknowledge */ |
c5619bf9 | 1593 | *data = gic_acknowledge_irq(s, cpu, attrs); |
a9d85353 | 1594 | break; |
66a0a2cb | 1595 | case 0x14: /* Running Priority */ |
08efa9f2 | 1596 | *data = gic_get_running_priority(s, cpu, attrs); |
a9d85353 | 1597 | break; |
e69954b9 | 1598 | case 0x18: /* Highest Pending Interrupt */ |
7c0fa108 | 1599 | *data = gic_get_current_pending_irq(s, cpu, attrs); |
a9d85353 | 1600 | break; |
aa7d461a | 1601 | case 0x1c: /* Aliased Binary Point */ |
822e9cc3 FA |
1602 | /* GIC v2, no security: ABPR |
1603 | * GIC v1, no security: not implemented (RAZ/WI) | |
1604 | * With security extensions, secure access: ABPR (alias of NS BPR) | |
1605 | * With security extensions, nonsecure access: RAZ/WI | |
1606 | */ | |
3dd0471b | 1607 | if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { |
822e9cc3 FA |
1608 | *data = 0; |
1609 | } else { | |
1610 | *data = s->abpr[cpu]; | |
1611 | } | |
a9d85353 | 1612 | break; |
a9d477c4 | 1613 | case 0xd0: case 0xd4: case 0xd8: case 0xdc: |
51fd06e0 PM |
1614 | { |
1615 | int regno = (offset - 0xd0) / 4; | |
7eb079ec | 1616 | int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; |
51fd06e0 | 1617 | |
7eb079ec | 1618 | if (regno >= nr_aprs || s->revision != 2) { |
51fd06e0 | 1619 | *data = 0; |
7eb079ec LM |
1620 | } else if (gic_is_vcpu(cpu)) { |
1621 | *data = s->h_apr[gic_get_vcpu_real_id(cpu)]; | |
3dd0471b | 1622 | } else if (gic_cpu_ns_access(s, cpu, attrs)) { |
51fd06e0 PM |
1623 | /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ |
1624 | *data = gic_apr_ns_view(s, regno, cpu); | |
1625 | } else { | |
1626 | *data = s->apr[regno][cpu]; | |
1627 | } | |
a9d85353 | 1628 | break; |
51fd06e0 PM |
1629 | } |
1630 | case 0xe0: case 0xe4: case 0xe8: case 0xec: | |
1631 | { | |
1632 | int regno = (offset - 0xe0) / 4; | |
1633 | ||
1634 | if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || | |
7eb079ec | 1635 | gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { |
51fd06e0 PM |
1636 | *data = 0; |
1637 | } else { | |
1638 | *data = s->nsapr[regno][cpu]; | |
1639 | } | |
1640 | break; | |
1641 | } | |
e69954b9 | 1642 | default: |
8c8dc39f PM |
1643 | qemu_log_mask(LOG_GUEST_ERROR, |
1644 | "gic_cpu_read: Bad offset %x\n", (int)offset); | |
0cf09852 PM |
1645 | *data = 0; |
1646 | break; | |
e69954b9 | 1647 | } |
067a2b9c LM |
1648 | |
1649 | trace_gic_cpu_read(gic_is_vcpu(cpu) ? "vcpu" : "cpu", | |
1650 | gic_get_vcpu_real_id(cpu), offset, *data); | |
a9d85353 | 1651 | return MEMTX_OK; |
e69954b9 PB |
1652 | } |
1653 | ||
a9d85353 PM |
1654 | static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, |
1655 | uint32_t value, MemTxAttrs attrs) | |
e69954b9 | 1656 | { |
067a2b9c LM |
1657 | trace_gic_cpu_write(gic_is_vcpu(cpu) ? "vcpu" : "cpu", |
1658 | gic_get_vcpu_real_id(cpu), offset, value); | |
1659 | ||
e69954b9 PB |
1660 | switch (offset) { |
1661 | case 0x00: /* Control */ | |
32951860 | 1662 | gic_set_cpu_control(s, cpu, value, attrs); |
e69954b9 PB |
1663 | break; |
1664 | case 0x04: /* Priority mask */ | |
81508470 | 1665 | gic_set_priority_mask(s, cpu, value, attrs); |
e69954b9 PB |
1666 | break; |
1667 | case 0x08: /* Binary Point */ | |
3dd0471b | 1668 | if (gic_cpu_ns_access(s, cpu, attrs)) { |
421a3c22 LM |
1669 | if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { |
1670 | /* WI when CBPR is 1 */ | |
1671 | return MEMTX_OK; | |
1672 | } else { | |
1673 | s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); | |
1674 | } | |
822e9cc3 | 1675 | } else { |
7eb079ec LM |
1676 | int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; |
1677 | s->bpr[cpu] = MAX(value & 0x7, min_bpr); | |
822e9cc3 | 1678 | } |
e69954b9 PB |
1679 | break; |
1680 | case 0x10: /* End Of Interrupt */ | |
f9c6a7f1 | 1681 | gic_complete_irq(s, cpu, value & 0x3ff, attrs); |
a9d85353 | 1682 | return MEMTX_OK; |
aa7d461a | 1683 | case 0x1c: /* Aliased Binary Point */ |
3dd0471b | 1684 | if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { |
822e9cc3 FA |
1685 | /* unimplemented, or NS access: RAZ/WI */ |
1686 | return MEMTX_OK; | |
1687 | } else { | |
1688 | s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); | |
aa7d461a CD |
1689 | } |
1690 | break; | |
a9d477c4 | 1691 | case 0xd0: case 0xd4: case 0xd8: case 0xdc: |
51fd06e0 PM |
1692 | { |
1693 | int regno = (offset - 0xd0) / 4; | |
7eb079ec | 1694 | int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; |
51fd06e0 | 1695 | |
7eb079ec | 1696 | if (regno >= nr_aprs || s->revision != 2) { |
51fd06e0 PM |
1697 | return MEMTX_OK; |
1698 | } | |
7eb079ec LM |
1699 | if (gic_is_vcpu(cpu)) { |
1700 | s->h_apr[gic_get_vcpu_real_id(cpu)] = value; | |
1701 | } else if (gic_cpu_ns_access(s, cpu, attrs)) { | |
51fd06e0 PM |
1702 | /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ |
1703 | gic_apr_write_ns_view(s, regno, cpu, value); | |
1704 | } else { | |
1705 | s->apr[regno][cpu] = value; | |
1706 | } | |
1707 | break; | |
1708 | } | |
1709 | case 0xe0: case 0xe4: case 0xe8: case 0xec: | |
1710 | { | |
1711 | int regno = (offset - 0xe0) / 4; | |
1712 | ||
1713 | if (regno >= GIC_NR_APRS || s->revision != 2) { | |
1714 | return MEMTX_OK; | |
1715 | } | |
7eb079ec LM |
1716 | if (gic_is_vcpu(cpu)) { |
1717 | return MEMTX_OK; | |
1718 | } | |
3dd0471b | 1719 | if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { |
51fd06e0 PM |
1720 | return MEMTX_OK; |
1721 | } | |
1722 | s->nsapr[regno][cpu] = value; | |
a9d477c4 | 1723 | break; |
51fd06e0 | 1724 | } |
a55c910e PM |
1725 | case 0x1000: |
1726 | /* GICC_DIR */ | |
1727 | gic_deactivate_irq(s, cpu, value & 0x3ff, attrs); | |
1728 | break; | |
e69954b9 | 1729 | default: |
8c8dc39f PM |
1730 | qemu_log_mask(LOG_GUEST_ERROR, |
1731 | "gic_cpu_write: Bad offset %x\n", (int)offset); | |
0cf09852 | 1732 | return MEMTX_OK; |
e69954b9 | 1733 | } |
cbe1282b LM |
1734 | |
1735 | if (gic_is_vcpu(cpu)) { | |
1736 | gic_update_virt(s); | |
1737 | } else { | |
1738 | gic_update(s); | |
1739 | } | |
1740 | ||
a9d85353 | 1741 | return MEMTX_OK; |
e69954b9 | 1742 | } |
e2c56465 PM |
1743 | |
1744 | /* Wrappers to read/write the GIC CPU interface for the current CPU */ | |
a9d85353 PM |
1745 | static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1746 | unsigned size, MemTxAttrs attrs) | |
e2c56465 | 1747 | { |
fae15286 | 1748 | GICState *s = (GICState *)opaque; |
a9d85353 | 1749 | return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); |
e2c56465 PM |
1750 | } |
1751 | ||
a9d85353 PM |
1752 | static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, |
1753 | uint64_t value, unsigned size, | |
1754 | MemTxAttrs attrs) | |
e2c56465 | 1755 | { |
fae15286 | 1756 | GICState *s = (GICState *)opaque; |
a9d85353 | 1757 | return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); |
e2c56465 PM |
1758 | } |
1759 | ||
1760 | /* Wrappers to read/write the GIC CPU interface for a specific CPU. | |
fae15286 | 1761 | * These just decode the opaque pointer into GICState* + cpu id. |
e2c56465 | 1762 | */ |
a9d85353 PM |
1763 | static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1764 | unsigned size, MemTxAttrs attrs) | |
e2c56465 | 1765 | { |
fae15286 PM |
1766 | GICState **backref = (GICState **)opaque; |
1767 | GICState *s = *backref; | |
e2c56465 | 1768 | int id = (backref - s->backref); |
a9d85353 | 1769 | return gic_cpu_read(s, id, addr, data, attrs); |
e2c56465 PM |
1770 | } |
1771 | ||
a9d85353 PM |
1772 | static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr, |
1773 | uint64_t value, unsigned size, | |
1774 | MemTxAttrs attrs) | |
e2c56465 | 1775 | { |
fae15286 PM |
1776 | GICState **backref = (GICState **)opaque; |
1777 | GICState *s = *backref; | |
e2c56465 | 1778 | int id = (backref - s->backref); |
a9d85353 | 1779 | return gic_cpu_write(s, id, addr, value, attrs); |
e2c56465 PM |
1780 | } |
1781 | ||
2c679ac7 LM |
1782 | static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, |
1783 | unsigned size, MemTxAttrs attrs) | |
1784 | { | |
1785 | GICState *s = (GICState *)opaque; | |
1786 | ||
1787 | return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); | |
1788 | } | |
1789 | ||
1790 | static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, | |
1791 | uint64_t value, unsigned size, | |
1792 | MemTxAttrs attrs) | |
1793 | { | |
1794 | GICState *s = (GICState *)opaque; | |
1795 | ||
1796 | return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); | |
1797 | } | |
1798 | ||
527d296f LM |
1799 | static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) |
1800 | { | |
1801 | int lr_idx; | |
1802 | uint32_t ret = 0; | |
1803 | ||
1804 | for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) { | |
1805 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; | |
1806 | ret = deposit32(ret, lr_idx - lr_start, 1, | |
1807 | gic_lr_entry_is_eoi(*entry)); | |
1808 | } | |
1809 | ||
1810 | return ret; | |
1811 | } | |
1812 | ||
1813 | static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) | |
1814 | { | |
1815 | int lr_idx; | |
1816 | uint32_t ret = 0; | |
1817 | ||
1818 | for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) { | |
1819 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; | |
1820 | ret = deposit32(ret, lr_idx - lr_start, 1, | |
1821 | gic_lr_entry_is_free(*entry)); | |
1822 | } | |
1823 | ||
1824 | return ret; | |
1825 | } | |
1826 | ||
1827 | static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) | |
1828 | { | |
1829 | int vcpu = gic_get_current_vcpu(s); | |
1830 | uint32_t ctlr; | |
1831 | uint32_t abpr; | |
1832 | uint32_t bpr; | |
1833 | uint32_t prio_mask; | |
1834 | ||
1835 | ctlr = FIELD_EX32(value, GICH_VMCR, VMCCtlr); | |
1836 | abpr = FIELD_EX32(value, GICH_VMCR, VMABP); | |
1837 | bpr = FIELD_EX32(value, GICH_VMCR, VMBP); | |
1838 | prio_mask = FIELD_EX32(value, GICH_VMCR, VMPriMask) << 3; | |
1839 | ||
1840 | gic_set_cpu_control(s, vcpu, ctlr, attrs); | |
1841 | s->abpr[vcpu] = MAX(abpr, GIC_VIRT_MIN_ABPR); | |
1842 | s->bpr[vcpu] = MAX(bpr, GIC_VIRT_MIN_BPR); | |
1843 | gic_set_priority_mask(s, vcpu, prio_mask, attrs); | |
1844 | } | |
1845 | ||
1846 | static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, | |
1847 | uint64_t *data, MemTxAttrs attrs) | |
1848 | { | |
1849 | GICState *s = ARM_GIC(opaque); | |
1850 | int vcpu = cpu + GIC_NCPU; | |
1851 | ||
1852 | switch (addr) { | |
1853 | case A_GICH_HCR: /* Hypervisor Control */ | |
1854 | *data = s->h_hcr[cpu]; | |
1855 | break; | |
1856 | ||
1857 | case A_GICH_VTR: /* VGIC Type */ | |
1858 | *data = FIELD_DP32(0, GICH_VTR, ListRegs, s->num_lrs - 1); | |
1859 | *data = FIELD_DP32(*data, GICH_VTR, PREbits, | |
1860 | GIC_VIRT_MAX_GROUP_PRIO_BITS - 1); | |
1861 | *data = FIELD_DP32(*data, GICH_VTR, PRIbits, | |
1862 | (7 - GIC_VIRT_MIN_BPR) - 1); | |
1863 | break; | |
1864 | ||
1865 | case A_GICH_VMCR: /* Virtual Machine Control */ | |
1866 | *data = FIELD_DP32(0, GICH_VMCR, VMCCtlr, | |
1867 | extract32(s->cpu_ctlr[vcpu], 0, 10)); | |
1868 | *data = FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]); | |
1869 | *data = FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]); | |
1870 | *data = FIELD_DP32(*data, GICH_VMCR, VMPriMask, | |
1871 | extract32(s->priority_mask[vcpu], 3, 5)); | |
1872 | break; | |
1873 | ||
1874 | case A_GICH_MISR: /* Maintenance Interrupt Status */ | |
1875 | *data = s->h_misr[cpu]; | |
1876 | break; | |
1877 | ||
1878 | case A_GICH_EISR0: /* End of Interrupt Status 0 and 1 */ | |
1879 | case A_GICH_EISR1: | |
1880 | *data = gic_compute_eisr(s, cpu, (addr - A_GICH_EISR0) * 8); | |
1881 | break; | |
1882 | ||
1883 | case A_GICH_ELRSR0: /* Empty List Status 0 and 1 */ | |
1884 | case A_GICH_ELRSR1: | |
1885 | *data = gic_compute_elrsr(s, cpu, (addr - A_GICH_ELRSR0) * 8); | |
1886 | break; | |
1887 | ||
1888 | case A_GICH_APR: /* Active Priorities */ | |
1889 | *data = s->h_apr[cpu]; | |
1890 | break; | |
1891 | ||
1892 | case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ | |
1893 | { | |
1894 | int lr_idx = (addr - A_GICH_LR0) / 4; | |
1895 | ||
1896 | if (lr_idx > s->num_lrs) { | |
1897 | *data = 0; | |
1898 | } else { | |
1899 | *data = s->h_lr[lr_idx][cpu]; | |
1900 | } | |
1901 | break; | |
1902 | } | |
1903 | ||
1904 | default: | |
1905 | qemu_log_mask(LOG_GUEST_ERROR, | |
1906 | "gic_hyp_read: Bad offset %" HWADDR_PRIx "\n", addr); | |
1907 | return MEMTX_OK; | |
1908 | } | |
1909 | ||
067a2b9c | 1910 | trace_gic_hyp_read(addr, *data); |
527d296f LM |
1911 | return MEMTX_OK; |
1912 | } | |
1913 | ||
1914 | static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, | |
1915 | uint64_t value, MemTxAttrs attrs) | |
1916 | { | |
1917 | GICState *s = ARM_GIC(opaque); | |
1918 | int vcpu = cpu + GIC_NCPU; | |
1919 | ||
067a2b9c LM |
1920 | trace_gic_hyp_write(addr, value); |
1921 | ||
527d296f LM |
1922 | switch (addr) { |
1923 | case A_GICH_HCR: /* Hypervisor Control */ | |
1924 | s->h_hcr[cpu] = value & GICH_HCR_MASK; | |
1925 | break; | |
1926 | ||
1927 | case A_GICH_VMCR: /* Virtual Machine Control */ | |
1928 | gic_vmcr_write(s, value, attrs); | |
1929 | break; | |
1930 | ||
1931 | case A_GICH_APR: /* Active Priorities */ | |
1932 | s->h_apr[cpu] = value; | |
1933 | s->running_priority[vcpu] = gic_get_prio_from_apr_bits(s, vcpu); | |
1934 | break; | |
1935 | ||
1936 | case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ | |
1937 | { | |
1938 | int lr_idx = (addr - A_GICH_LR0) / 4; | |
1939 | ||
1940 | if (lr_idx > s->num_lrs) { | |
1941 | return MEMTX_OK; | |
1942 | } | |
1943 | ||
1944 | s->h_lr[lr_idx][cpu] = value & GICH_LR_MASK; | |
067a2b9c | 1945 | trace_gic_lr_entry(cpu, lr_idx, s->h_lr[lr_idx][cpu]); |
527d296f LM |
1946 | break; |
1947 | } | |
1948 | ||
1949 | default: | |
1950 | qemu_log_mask(LOG_GUEST_ERROR, | |
1951 | "gic_hyp_write: Bad offset %" HWADDR_PRIx "\n", addr); | |
1952 | return MEMTX_OK; | |
1953 | } | |
1954 | ||
cbe1282b | 1955 | gic_update_virt(s); |
527d296f LM |
1956 | return MEMTX_OK; |
1957 | } | |
1958 | ||
1959 | static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *data, | |
1960 | unsigned size, MemTxAttrs attrs) | |
1961 | { | |
1962 | GICState *s = (GICState *)opaque; | |
1963 | ||
1964 | return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); | |
1965 | } | |
1966 | ||
1967 | static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, | |
1968 | uint64_t value, unsigned size, | |
1969 | MemTxAttrs attrs) | |
1970 | { | |
1971 | GICState *s = (GICState *)opaque; | |
1972 | ||
1973 | return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); | |
1974 | } | |
1975 | ||
1976 | static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, | |
1977 | unsigned size, MemTxAttrs attrs) | |
1978 | { | |
1979 | GICState **backref = (GICState **)opaque; | |
1980 | GICState *s = *backref; | |
1981 | int id = (backref - s->backref); | |
1982 | ||
1983 | return gic_hyp_read(s, id, addr, data, attrs); | |
1984 | } | |
1985 | ||
1986 | static MemTxResult gic_do_hyp_write(void *opaque, hwaddr addr, | |
1987 | uint64_t value, unsigned size, | |
1988 | MemTxAttrs attrs) | |
1989 | { | |
1990 | GICState **backref = (GICState **)opaque; | |
1991 | GICState *s = *backref; | |
1992 | int id = (backref - s->backref); | |
1993 | ||
1994 | return gic_hyp_write(s, id + GIC_NCPU, addr, value, attrs); | |
1995 | ||
1996 | } | |
1997 | ||
7926c210 PF |
1998 | static const MemoryRegionOps gic_ops[2] = { |
1999 | { | |
2000 | .read_with_attrs = gic_dist_read, | |
2001 | .write_with_attrs = gic_dist_write, | |
2002 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2003 | }, | |
2004 | { | |
2005 | .read_with_attrs = gic_thiscpu_read, | |
2006 | .write_with_attrs = gic_thiscpu_write, | |
2007 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2008 | } | |
e2c56465 PM |
2009 | }; |
2010 | ||
2011 | static const MemoryRegionOps gic_cpu_ops = { | |
a9d85353 PM |
2012 | .read_with_attrs = gic_do_cpu_read, |
2013 | .write_with_attrs = gic_do_cpu_write, | |
e2c56465 PM |
2014 | .endianness = DEVICE_NATIVE_ENDIAN, |
2015 | }; | |
e69954b9 | 2016 | |
2c679ac7 LM |
2017 | static const MemoryRegionOps gic_virt_ops[2] = { |
2018 | { | |
527d296f LM |
2019 | .read_with_attrs = gic_thiscpu_hyp_read, |
2020 | .write_with_attrs = gic_thiscpu_hyp_write, | |
2c679ac7 LM |
2021 | .endianness = DEVICE_NATIVE_ENDIAN, |
2022 | }, | |
2023 | { | |
2024 | .read_with_attrs = gic_thisvcpu_read, | |
2025 | .write_with_attrs = gic_thisvcpu_write, | |
2026 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2027 | } | |
2028 | }; | |
2029 | ||
527d296f LM |
2030 | static const MemoryRegionOps gic_viface_ops = { |
2031 | .read_with_attrs = gic_do_hyp_read, | |
2032 | .write_with_attrs = gic_do_hyp_write, | |
2033 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2034 | }; | |
2035 | ||
53111180 | 2036 | static void arm_gic_realize(DeviceState *dev, Error **errp) |
2b518c56 | 2037 | { |
53111180 | 2038 | /* Device instance realize function for the GIC sysbus device */ |
2b518c56 | 2039 | int i; |
53111180 PM |
2040 | GICState *s = ARM_GIC(dev); |
2041 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
1e8cae4d | 2042 | ARMGICClass *agc = ARM_GIC_GET_CLASS(s); |
0175ba10 | 2043 | Error *local_err = NULL; |
1e8cae4d | 2044 | |
0175ba10 MA |
2045 | agc->parent_realize(dev, &local_err); |
2046 | if (local_err) { | |
2047 | error_propagate(errp, local_err); | |
53111180 PM |
2048 | return; |
2049 | } | |
1e8cae4d | 2050 | |
5d721b78 AG |
2051 | if (kvm_enabled() && !kvm_arm_supports_user_irq()) { |
2052 | error_setg(errp, "KVM with user space irqchip only works when the " | |
2053 | "host kernel supports KVM_CAP_ARM_USER_IRQ"); | |
2054 | return; | |
2055 | } | |
2056 | ||
2c679ac7 LM |
2057 | /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if |
2058 | * enabled, virtualization extensions related interfaces (main virtual | |
2059 | * interface (s->vifaceiomem[0]) and virtual CPU interface). | |
2060 | */ | |
2061 | gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops); | |
2b518c56 | 2062 | |
7926c210 PF |
2063 | /* Extra core-specific regions for the CPU interfaces. This is |
2064 | * necessary for "franken-GIC" implementations, for example on | |
2065 | * Exynos 4. | |
e2c56465 PM |
2066 | * NB that the memory region size of 0x100 applies for the 11MPCore |
2067 | * and also cores following the GIC v1 spec (ie A9). | |
2068 | * GIC v2 defines a larger memory region (0x1000) so this will need | |
2069 | * to be extended when we implement A15. | |
2070 | */ | |
b95690c9 | 2071 | for (i = 0; i < s->num_cpu; i++) { |
e2c56465 | 2072 | s->backref[i] = s; |
1437c94b PB |
2073 | memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, |
2074 | &s->backref[i], "gic_cpu", 0x100); | |
7926c210 | 2075 | sysbus_init_mmio(sbd, &s->cpuiomem[i+1]); |
496dbcd1 | 2076 | } |
527d296f LM |
2077 | |
2078 | /* Extra core-specific regions for virtual interfaces. This is required by | |
2079 | * the GICv2 specification. | |
2080 | */ | |
2081 | if (s->virt_extn) { | |
2082 | for (i = 0; i < s->num_cpu; i++) { | |
2083 | memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s), | |
2084 | &gic_viface_ops, &s->backref[i], | |
7210918c | 2085 | "gic_viface", 0x200); |
527d296f LM |
2086 | sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]); |
2087 | } | |
2088 | } | |
2089 | ||
496dbcd1 PM |
2090 | } |
2091 | ||
496dbcd1 PM |
2092 | static void arm_gic_class_init(ObjectClass *klass, void *data) |
2093 | { | |
2094 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1e8cae4d | 2095 | ARMGICClass *agc = ARM_GIC_CLASS(klass); |
53111180 | 2096 | |
bf853881 | 2097 | device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); |
496dbcd1 PM |
2098 | } |
2099 | ||
8c43a6f0 | 2100 | static const TypeInfo arm_gic_info = { |
1e8cae4d PM |
2101 | .name = TYPE_ARM_GIC, |
2102 | .parent = TYPE_ARM_GIC_COMMON, | |
fae15286 | 2103 | .instance_size = sizeof(GICState), |
496dbcd1 | 2104 | .class_init = arm_gic_class_init, |
998a74bc | 2105 | .class_size = sizeof(ARMGICClass), |
496dbcd1 PM |
2106 | }; |
2107 | ||
2108 | static void arm_gic_register_types(void) | |
2109 | { | |
2110 | type_register_static(&arm_gic_info); | |
2111 | } | |
2112 | ||
2113 | type_init(arm_gic_register_types) |