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Commit | Line | Data |
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b5cec4c5 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics | |
5 | * | |
6 | * Copyright (c) 2010,2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
0d75590d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
83c9f4ca | 30 | #include "hw/hw.h" |
500efa23 | 31 | #include "trace.h" |
5d87e4b7 | 32 | #include "qemu/timer.h" |
0d09e41a PB |
33 | #include "hw/ppc/spapr.h" |
34 | #include "hw/ppc/xics.h" | |
9ccff2a4 | 35 | #include "qemu/error-report.h" |
5a3d7b23 | 36 | #include "qapi/visitor.h" |
b5cec4c5 | 37 | |
0f20ba62 AK |
38 | static int get_cpu_index_by_dt_id(int cpu_dt_id) |
39 | { | |
40 | PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); | |
41 | ||
42 | if (cpu) { | |
43 | return cpu->parent_obj.cpu_index; | |
44 | } | |
45 | ||
46 | return -1; | |
47 | } | |
48 | ||
8ffe04ed AK |
49 | void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) |
50 | { | |
51 | CPUState *cs = CPU(cpu); | |
52 | CPUPPCState *env = &cpu->env; | |
53 | ICPState *ss = &icp->ss[cs->cpu_index]; | |
5eb92ccc | 54 | XICSStateClass *info = XICS_COMMON_GET_CLASS(icp); |
8ffe04ed AK |
55 | |
56 | assert(cs->cpu_index < icp->nr_servers); | |
57 | ||
5eb92ccc AK |
58 | if (info->cpu_setup) { |
59 | info->cpu_setup(icp, cpu); | |
60 | } | |
61 | ||
8ffe04ed AK |
62 | switch (PPC_INPUT(env)) { |
63 | case PPC_FLAGS_INPUT_POWER7: | |
64 | ss->output = env->irq_inputs[POWER7_INPUT_INT]; | |
65 | break; | |
66 | ||
67 | case PPC_FLAGS_INPUT_970: | |
68 | ss->output = env->irq_inputs[PPC970_INPUT_INT]; | |
69 | break; | |
70 | ||
71 | default: | |
9ccff2a4 AK |
72 | error_report("XICS interrupt controller does not support this CPU " |
73 | "bus model"); | |
8ffe04ed AK |
74 | abort(); |
75 | } | |
76 | } | |
77 | ||
5a3d7b23 AK |
78 | /* |
79 | * XICS Common class - parent for emulated XICS and KVM-XICS | |
80 | */ | |
81 | static void xics_common_reset(DeviceState *d) | |
8ffe04ed | 82 | { |
5a3d7b23 | 83 | XICSState *icp = XICS_COMMON(d); |
8ffe04ed AK |
84 | int i; |
85 | ||
86 | for (i = 0; i < icp->nr_servers; i++) { | |
87 | device_reset(DEVICE(&icp->ss[i])); | |
88 | } | |
89 | ||
90 | device_reset(DEVICE(icp->ics)); | |
91 | } | |
92 | ||
d7bce999 EB |
93 | static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name, |
94 | void *opaque, Error **errp) | |
5a3d7b23 AK |
95 | { |
96 | XICSState *icp = XICS_COMMON(obj); | |
97 | int64_t value = icp->nr_irqs; | |
98 | ||
51e72bc1 | 99 | visit_type_int(v, name, &value, errp); |
5a3d7b23 AK |
100 | } |
101 | ||
d7bce999 EB |
102 | static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name, |
103 | void *opaque, Error **errp) | |
5a3d7b23 AK |
104 | { |
105 | XICSState *icp = XICS_COMMON(obj); | |
106 | XICSStateClass *info = XICS_COMMON_GET_CLASS(icp); | |
107 | Error *error = NULL; | |
108 | int64_t value; | |
109 | ||
51e72bc1 | 110 | visit_type_int(v, name, &value, &error); |
5a3d7b23 AK |
111 | if (error) { |
112 | error_propagate(errp, error); | |
113 | return; | |
114 | } | |
115 | if (icp->nr_irqs) { | |
116 | error_setg(errp, "Number of interrupts is already set to %u", | |
117 | icp->nr_irqs); | |
118 | return; | |
119 | } | |
120 | ||
121 | assert(info->set_nr_irqs); | |
122 | assert(icp->ics); | |
123 | info->set_nr_irqs(icp, value, errp); | |
124 | } | |
125 | ||
126 | static void xics_prop_get_nr_servers(Object *obj, Visitor *v, | |
d7bce999 | 127 | const char *name, void *opaque, |
5a3d7b23 AK |
128 | Error **errp) |
129 | { | |
130 | XICSState *icp = XICS_COMMON(obj); | |
131 | int64_t value = icp->nr_servers; | |
132 | ||
51e72bc1 | 133 | visit_type_int(v, name, &value, errp); |
5a3d7b23 AK |
134 | } |
135 | ||
136 | static void xics_prop_set_nr_servers(Object *obj, Visitor *v, | |
d7bce999 | 137 | const char *name, void *opaque, |
5a3d7b23 AK |
138 | Error **errp) |
139 | { | |
140 | XICSState *icp = XICS_COMMON(obj); | |
141 | XICSStateClass *info = XICS_COMMON_GET_CLASS(icp); | |
142 | Error *error = NULL; | |
143 | int64_t value; | |
144 | ||
51e72bc1 | 145 | visit_type_int(v, name, &value, &error); |
5a3d7b23 AK |
146 | if (error) { |
147 | error_propagate(errp, error); | |
148 | return; | |
149 | } | |
150 | if (icp->nr_servers) { | |
151 | error_setg(errp, "Number of servers is already set to %u", | |
152 | icp->nr_servers); | |
153 | return; | |
154 | } | |
155 | ||
156 | assert(info->set_nr_servers); | |
157 | info->set_nr_servers(icp, value, errp); | |
158 | } | |
159 | ||
160 | static void xics_common_initfn(Object *obj) | |
161 | { | |
162 | object_property_add(obj, "nr_irqs", "int", | |
163 | xics_prop_get_nr_irqs, xics_prop_set_nr_irqs, | |
164 | NULL, NULL, NULL); | |
165 | object_property_add(obj, "nr_servers", "int", | |
166 | xics_prop_get_nr_servers, xics_prop_set_nr_servers, | |
167 | NULL, NULL, NULL); | |
168 | } | |
169 | ||
170 | static void xics_common_class_init(ObjectClass *oc, void *data) | |
171 | { | |
172 | DeviceClass *dc = DEVICE_CLASS(oc); | |
173 | ||
174 | dc->reset = xics_common_reset; | |
175 | } | |
176 | ||
177 | static const TypeInfo xics_common_info = { | |
178 | .name = TYPE_XICS_COMMON, | |
179 | .parent = TYPE_SYS_BUS_DEVICE, | |
180 | .instance_size = sizeof(XICSState), | |
181 | .class_size = sizeof(XICSStateClass), | |
182 | .instance_init = xics_common_initfn, | |
183 | .class_init = xics_common_class_init, | |
184 | }; | |
185 | ||
b5cec4c5 DG |
186 | /* |
187 | * ICP: Presentation layer | |
188 | */ | |
189 | ||
b5cec4c5 DG |
190 | #define XISR_MASK 0x00ffffff |
191 | #define CPPR_MASK 0xff000000 | |
192 | ||
193 | #define XISR(ss) (((ss)->xirr) & XISR_MASK) | |
194 | #define CPPR(ss) (((ss)->xirr) >> 24) | |
195 | ||
c04d6cfa AL |
196 | static void ics_reject(ICSState *ics, int nr); |
197 | static void ics_resend(ICSState *ics); | |
198 | static void ics_eoi(ICSState *ics, int nr); | |
b5cec4c5 | 199 | |
c04d6cfa | 200 | static void icp_check_ipi(XICSState *icp, int server) |
b5cec4c5 | 201 | { |
c04d6cfa | 202 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
203 | |
204 | if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) { | |
205 | return; | |
206 | } | |
207 | ||
500efa23 DG |
208 | trace_xics_icp_check_ipi(server, ss->mfrr); |
209 | ||
b5cec4c5 DG |
210 | if (XISR(ss)) { |
211 | ics_reject(icp->ics, XISR(ss)); | |
212 | } | |
213 | ||
214 | ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI; | |
215 | ss->pending_priority = ss->mfrr; | |
216 | qemu_irq_raise(ss->output); | |
217 | } | |
218 | ||
c04d6cfa | 219 | static void icp_resend(XICSState *icp, int server) |
b5cec4c5 | 220 | { |
c04d6cfa | 221 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
222 | |
223 | if (ss->mfrr < CPPR(ss)) { | |
224 | icp_check_ipi(icp, server); | |
225 | } | |
226 | ics_resend(icp->ics); | |
227 | } | |
228 | ||
c04d6cfa | 229 | static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr) |
b5cec4c5 | 230 | { |
c04d6cfa | 231 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
232 | uint8_t old_cppr; |
233 | uint32_t old_xisr; | |
234 | ||
235 | old_cppr = CPPR(ss); | |
236 | ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24); | |
237 | ||
238 | if (cppr < old_cppr) { | |
239 | if (XISR(ss) && (cppr <= ss->pending_priority)) { | |
240 | old_xisr = XISR(ss); | |
241 | ss->xirr &= ~XISR_MASK; /* Clear XISR */ | |
e03c902c | 242 | ss->pending_priority = 0xff; |
b5cec4c5 DG |
243 | qemu_irq_lower(ss->output); |
244 | ics_reject(icp->ics, old_xisr); | |
245 | } | |
246 | } else { | |
247 | if (!XISR(ss)) { | |
248 | icp_resend(icp, server); | |
249 | } | |
250 | } | |
251 | } | |
252 | ||
c04d6cfa | 253 | static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr) |
b5cec4c5 | 254 | { |
c04d6cfa | 255 | ICPState *ss = icp->ss + server; |
b5cec4c5 DG |
256 | |
257 | ss->mfrr = mfrr; | |
258 | if (mfrr < CPPR(ss)) { | |
bf0175de | 259 | icp_check_ipi(icp, server); |
b5cec4c5 DG |
260 | } |
261 | } | |
262 | ||
c04d6cfa | 263 | static uint32_t icp_accept(ICPState *ss) |
b5cec4c5 | 264 | { |
500efa23 | 265 | uint32_t xirr = ss->xirr; |
b5cec4c5 DG |
266 | |
267 | qemu_irq_lower(ss->output); | |
b5cec4c5 | 268 | ss->xirr = ss->pending_priority << 24; |
e03c902c | 269 | ss->pending_priority = 0xff; |
500efa23 DG |
270 | |
271 | trace_xics_icp_accept(xirr, ss->xirr); | |
272 | ||
b5cec4c5 DG |
273 | return xirr; |
274 | } | |
275 | ||
c04d6cfa | 276 | static void icp_eoi(XICSState *icp, int server, uint32_t xirr) |
b5cec4c5 | 277 | { |
c04d6cfa | 278 | ICPState *ss = icp->ss + server; |
b5cec4c5 | 279 | |
b5cec4c5 DG |
280 | /* Send EOI -> ICS */ |
281 | ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK); | |
500efa23 | 282 | trace_xics_icp_eoi(server, xirr, ss->xirr); |
d07fee7e | 283 | ics_eoi(icp->ics, xirr & XISR_MASK); |
b5cec4c5 DG |
284 | if (!XISR(ss)) { |
285 | icp_resend(icp, server); | |
286 | } | |
287 | } | |
288 | ||
c04d6cfa | 289 | static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority) |
b5cec4c5 | 290 | { |
c04d6cfa | 291 | ICPState *ss = icp->ss + server; |
b5cec4c5 | 292 | |
500efa23 DG |
293 | trace_xics_icp_irq(server, nr, priority); |
294 | ||
b5cec4c5 DG |
295 | if ((priority >= CPPR(ss)) |
296 | || (XISR(ss) && (ss->pending_priority <= priority))) { | |
297 | ics_reject(icp->ics, nr); | |
298 | } else { | |
299 | if (XISR(ss)) { | |
300 | ics_reject(icp->ics, XISR(ss)); | |
301 | } | |
302 | ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK); | |
303 | ss->pending_priority = priority; | |
500efa23 | 304 | trace_xics_icp_raise(ss->xirr, ss->pending_priority); |
b5cec4c5 DG |
305 | qemu_irq_raise(ss->output); |
306 | } | |
307 | } | |
308 | ||
d1b5682d AK |
309 | static void icp_dispatch_pre_save(void *opaque) |
310 | { | |
311 | ICPState *ss = opaque; | |
312 | ICPStateClass *info = ICP_GET_CLASS(ss); | |
313 | ||
314 | if (info->pre_save) { | |
315 | info->pre_save(ss); | |
316 | } | |
317 | } | |
318 | ||
319 | static int icp_dispatch_post_load(void *opaque, int version_id) | |
320 | { | |
321 | ICPState *ss = opaque; | |
322 | ICPStateClass *info = ICP_GET_CLASS(ss); | |
323 | ||
324 | if (info->post_load) { | |
325 | return info->post_load(ss, version_id); | |
326 | } | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
c04d6cfa AL |
331 | static const VMStateDescription vmstate_icp_server = { |
332 | .name = "icp/server", | |
333 | .version_id = 1, | |
334 | .minimum_version_id = 1, | |
d1b5682d AK |
335 | .pre_save = icp_dispatch_pre_save, |
336 | .post_load = icp_dispatch_post_load, | |
3aff6c2f | 337 | .fields = (VMStateField[]) { |
c04d6cfa AL |
338 | /* Sanity check */ |
339 | VMSTATE_UINT32(xirr, ICPState), | |
340 | VMSTATE_UINT8(pending_priority, ICPState), | |
341 | VMSTATE_UINT8(mfrr, ICPState), | |
342 | VMSTATE_END_OF_LIST() | |
343 | }, | |
b5cec4c5 DG |
344 | }; |
345 | ||
c04d6cfa AL |
346 | static void icp_reset(DeviceState *dev) |
347 | { | |
348 | ICPState *icp = ICP(dev); | |
349 | ||
350 | icp->xirr = 0; | |
351 | icp->pending_priority = 0xff; | |
352 | icp->mfrr = 0xff; | |
353 | ||
354 | /* Make all outputs are deasserted */ | |
355 | qemu_set_irq(icp->output, 0); | |
356 | } | |
357 | ||
358 | static void icp_class_init(ObjectClass *klass, void *data) | |
359 | { | |
360 | DeviceClass *dc = DEVICE_CLASS(klass); | |
361 | ||
362 | dc->reset = icp_reset; | |
363 | dc->vmsd = &vmstate_icp_server; | |
364 | } | |
365 | ||
456df19c | 366 | static const TypeInfo icp_info = { |
c04d6cfa AL |
367 | .name = TYPE_ICP, |
368 | .parent = TYPE_DEVICE, | |
369 | .instance_size = sizeof(ICPState), | |
370 | .class_init = icp_class_init, | |
d1b5682d | 371 | .class_size = sizeof(ICPStateClass), |
b5cec4c5 DG |
372 | }; |
373 | ||
c04d6cfa AL |
374 | /* |
375 | * ICS: Source layer | |
376 | */ | |
377 | static int ics_valid_irq(ICSState *ics, uint32_t nr) | |
b5cec4c5 DG |
378 | { |
379 | return (nr >= ics->offset) | |
380 | && (nr < (ics->offset + ics->nr_irqs)); | |
381 | } | |
382 | ||
c04d6cfa | 383 | static void resend_msi(ICSState *ics, int srcno) |
d07fee7e | 384 | { |
c04d6cfa | 385 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e DG |
386 | |
387 | /* FIXME: filter by server#? */ | |
98ca8c02 DG |
388 | if (irq->status & XICS_STATUS_REJECTED) { |
389 | irq->status &= ~XICS_STATUS_REJECTED; | |
d07fee7e DG |
390 | if (irq->priority != 0xff) { |
391 | icp_irq(ics->icp, irq->server, srcno + ics->offset, | |
392 | irq->priority); | |
393 | } | |
394 | } | |
395 | } | |
396 | ||
c04d6cfa | 397 | static void resend_lsi(ICSState *ics, int srcno) |
d07fee7e | 398 | { |
c04d6cfa | 399 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 400 | |
98ca8c02 DG |
401 | if ((irq->priority != 0xff) |
402 | && (irq->status & XICS_STATUS_ASSERTED) | |
403 | && !(irq->status & XICS_STATUS_SENT)) { | |
404 | irq->status |= XICS_STATUS_SENT; | |
d07fee7e DG |
405 | icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority); |
406 | } | |
407 | } | |
408 | ||
c04d6cfa | 409 | static void set_irq_msi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 410 | { |
c04d6cfa | 411 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 412 | |
500efa23 DG |
413 | trace_xics_set_irq_msi(srcno, srcno + ics->offset); |
414 | ||
b5cec4c5 DG |
415 | if (val) { |
416 | if (irq->priority == 0xff) { | |
98ca8c02 | 417 | irq->status |= XICS_STATUS_MASKED_PENDING; |
500efa23 | 418 | trace_xics_masked_pending(); |
b5cec4c5 | 419 | } else { |
cc67b9c8 | 420 | icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
421 | } |
422 | } | |
423 | } | |
424 | ||
c04d6cfa | 425 | static void set_irq_lsi(ICSState *ics, int srcno, int val) |
b5cec4c5 | 426 | { |
c04d6cfa | 427 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 | 428 | |
500efa23 | 429 | trace_xics_set_irq_lsi(srcno, srcno + ics->offset); |
98ca8c02 DG |
430 | if (val) { |
431 | irq->status |= XICS_STATUS_ASSERTED; | |
432 | } else { | |
433 | irq->status &= ~XICS_STATUS_ASSERTED; | |
434 | } | |
d07fee7e | 435 | resend_lsi(ics, srcno); |
b5cec4c5 DG |
436 | } |
437 | ||
d07fee7e | 438 | static void ics_set_irq(void *opaque, int srcno, int val) |
b5cec4c5 | 439 | { |
c04d6cfa | 440 | ICSState *ics = (ICSState *)opaque; |
b5cec4c5 | 441 | |
4af88944 | 442 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
d07fee7e DG |
443 | set_irq_lsi(ics, srcno, val); |
444 | } else { | |
445 | set_irq_msi(ics, srcno, val); | |
446 | } | |
447 | } | |
b5cec4c5 | 448 | |
c04d6cfa | 449 | static void write_xive_msi(ICSState *ics, int srcno) |
d07fee7e | 450 | { |
c04d6cfa | 451 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 452 | |
98ca8c02 DG |
453 | if (!(irq->status & XICS_STATUS_MASKED_PENDING) |
454 | || (irq->priority == 0xff)) { | |
d07fee7e | 455 | return; |
b5cec4c5 | 456 | } |
d07fee7e | 457 | |
98ca8c02 | 458 | irq->status &= ~XICS_STATUS_MASKED_PENDING; |
d07fee7e | 459 | icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority); |
b5cec4c5 DG |
460 | } |
461 | ||
c04d6cfa | 462 | static void write_xive_lsi(ICSState *ics, int srcno) |
b5cec4c5 | 463 | { |
d07fee7e DG |
464 | resend_lsi(ics, srcno); |
465 | } | |
466 | ||
c04d6cfa | 467 | static void ics_write_xive(ICSState *ics, int nr, int server, |
3fe719f4 | 468 | uint8_t priority, uint8_t saved_priority) |
d07fee7e DG |
469 | { |
470 | int srcno = nr - ics->offset; | |
c04d6cfa | 471 | ICSIRQState *irq = ics->irqs + srcno; |
b5cec4c5 DG |
472 | |
473 | irq->server = server; | |
474 | irq->priority = priority; | |
3fe719f4 | 475 | irq->saved_priority = saved_priority; |
b5cec4c5 | 476 | |
500efa23 DG |
477 | trace_xics_ics_write_xive(nr, srcno, server, priority); |
478 | ||
4af88944 | 479 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
d07fee7e DG |
480 | write_xive_lsi(ics, srcno); |
481 | } else { | |
482 | write_xive_msi(ics, srcno); | |
b5cec4c5 | 483 | } |
b5cec4c5 DG |
484 | } |
485 | ||
c04d6cfa | 486 | static void ics_reject(ICSState *ics, int nr) |
b5cec4c5 | 487 | { |
c04d6cfa | 488 | ICSIRQState *irq = ics->irqs + nr - ics->offset; |
d07fee7e | 489 | |
500efa23 | 490 | trace_xics_ics_reject(nr, nr - ics->offset); |
98ca8c02 DG |
491 | irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */ |
492 | irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */ | |
b5cec4c5 DG |
493 | } |
494 | ||
c04d6cfa | 495 | static void ics_resend(ICSState *ics) |
b5cec4c5 | 496 | { |
d07fee7e DG |
497 | int i; |
498 | ||
499 | for (i = 0; i < ics->nr_irqs; i++) { | |
d07fee7e | 500 | /* FIXME: filter by server#? */ |
4af88944 | 501 | if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { |
d07fee7e DG |
502 | resend_lsi(ics, i); |
503 | } else { | |
504 | resend_msi(ics, i); | |
505 | } | |
506 | } | |
b5cec4c5 DG |
507 | } |
508 | ||
c04d6cfa | 509 | static void ics_eoi(ICSState *ics, int nr) |
b5cec4c5 | 510 | { |
d07fee7e | 511 | int srcno = nr - ics->offset; |
c04d6cfa | 512 | ICSIRQState *irq = ics->irqs + srcno; |
d07fee7e | 513 | |
500efa23 DG |
514 | trace_xics_ics_eoi(nr); |
515 | ||
4af88944 | 516 | if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) { |
98ca8c02 | 517 | irq->status &= ~XICS_STATUS_SENT; |
d07fee7e | 518 | } |
b5cec4c5 DG |
519 | } |
520 | ||
c04d6cfa AL |
521 | static void ics_reset(DeviceState *dev) |
522 | { | |
523 | ICSState *ics = ICS(dev); | |
524 | int i; | |
a7e519a8 AK |
525 | uint8_t flags[ics->nr_irqs]; |
526 | ||
527 | for (i = 0; i < ics->nr_irqs; i++) { | |
528 | flags[i] = ics->irqs[i].flags; | |
529 | } | |
c04d6cfa AL |
530 | |
531 | memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs); | |
a7e519a8 | 532 | |
c04d6cfa AL |
533 | for (i = 0; i < ics->nr_irqs; i++) { |
534 | ics->irqs[i].priority = 0xff; | |
535 | ics->irqs[i].saved_priority = 0xff; | |
a7e519a8 | 536 | ics->irqs[i].flags = flags[i]; |
c04d6cfa AL |
537 | } |
538 | } | |
539 | ||
d1b5682d | 540 | static int ics_post_load(ICSState *ics, int version_id) |
c04d6cfa AL |
541 | { |
542 | int i; | |
c04d6cfa AL |
543 | |
544 | for (i = 0; i < ics->icp->nr_servers; i++) { | |
545 | icp_resend(ics->icp, i); | |
546 | } | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
d1b5682d AK |
551 | static void ics_dispatch_pre_save(void *opaque) |
552 | { | |
553 | ICSState *ics = opaque; | |
554 | ICSStateClass *info = ICS_GET_CLASS(ics); | |
555 | ||
556 | if (info->pre_save) { | |
557 | info->pre_save(ics); | |
558 | } | |
559 | } | |
560 | ||
561 | static int ics_dispatch_post_load(void *opaque, int version_id) | |
562 | { | |
563 | ICSState *ics = opaque; | |
564 | ICSStateClass *info = ICS_GET_CLASS(ics); | |
565 | ||
566 | if (info->post_load) { | |
567 | return info->post_load(ics, version_id); | |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
c04d6cfa AL |
573 | static const VMStateDescription vmstate_ics_irq = { |
574 | .name = "ics/irq", | |
4af88944 | 575 | .version_id = 2, |
c04d6cfa | 576 | .minimum_version_id = 1, |
3aff6c2f | 577 | .fields = (VMStateField[]) { |
c04d6cfa AL |
578 | VMSTATE_UINT32(server, ICSIRQState), |
579 | VMSTATE_UINT8(priority, ICSIRQState), | |
580 | VMSTATE_UINT8(saved_priority, ICSIRQState), | |
581 | VMSTATE_UINT8(status, ICSIRQState), | |
4af88944 | 582 | VMSTATE_UINT8(flags, ICSIRQState), |
c04d6cfa AL |
583 | VMSTATE_END_OF_LIST() |
584 | }, | |
585 | }; | |
586 | ||
587 | static const VMStateDescription vmstate_ics = { | |
588 | .name = "ics", | |
589 | .version_id = 1, | |
590 | .minimum_version_id = 1, | |
d1b5682d AK |
591 | .pre_save = ics_dispatch_pre_save, |
592 | .post_load = ics_dispatch_post_load, | |
3aff6c2f | 593 | .fields = (VMStateField[]) { |
c04d6cfa AL |
594 | /* Sanity check */ |
595 | VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), | |
596 | ||
597 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs, | |
598 | vmstate_ics_irq, ICSIRQState), | |
599 | VMSTATE_END_OF_LIST() | |
600 | }, | |
601 | }; | |
602 | ||
5a3d7b23 AK |
603 | static void ics_initfn(Object *obj) |
604 | { | |
605 | ICSState *ics = ICS(obj); | |
606 | ||
607 | ics->offset = XICS_IRQ_BASE; | |
608 | } | |
609 | ||
b45ff2d9 | 610 | static void ics_realize(DeviceState *dev, Error **errp) |
c04d6cfa AL |
611 | { |
612 | ICSState *ics = ICS(dev); | |
613 | ||
b45ff2d9 AK |
614 | if (!ics->nr_irqs) { |
615 | error_setg(errp, "Number of interrupts needs to be greater 0"); | |
616 | return; | |
617 | } | |
c04d6cfa | 618 | ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); |
c04d6cfa | 619 | ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); |
c04d6cfa AL |
620 | } |
621 | ||
622 | static void ics_class_init(ObjectClass *klass, void *data) | |
623 | { | |
624 | DeviceClass *dc = DEVICE_CLASS(klass); | |
d1b5682d | 625 | ICSStateClass *isc = ICS_CLASS(klass); |
c04d6cfa | 626 | |
b45ff2d9 | 627 | dc->realize = ics_realize; |
c04d6cfa AL |
628 | dc->vmsd = &vmstate_ics; |
629 | dc->reset = ics_reset; | |
d1b5682d | 630 | isc->post_load = ics_post_load; |
c04d6cfa AL |
631 | } |
632 | ||
456df19c | 633 | static const TypeInfo ics_info = { |
c04d6cfa AL |
634 | .name = TYPE_ICS, |
635 | .parent = TYPE_DEVICE, | |
636 | .instance_size = sizeof(ICSState), | |
637 | .class_init = ics_class_init, | |
d1b5682d | 638 | .class_size = sizeof(ICSStateClass), |
5a3d7b23 | 639 | .instance_init = ics_initfn, |
c04d6cfa AL |
640 | }; |
641 | ||
b5cec4c5 DG |
642 | /* |
643 | * Exported functions | |
644 | */ | |
641c3493 AK |
645 | static int xics_find_source(XICSState *icp, int irq) |
646 | { | |
647 | int sources = 1; | |
648 | int src; | |
649 | ||
650 | /* FIXME: implement multiple sources */ | |
651 | for (src = 0; src < sources; ++src) { | |
652 | ICSState *ics = &icp->ics[src]; | |
653 | if (ics_valid_irq(ics, irq)) { | |
654 | return src; | |
655 | } | |
656 | } | |
657 | ||
658 | return -1; | |
659 | } | |
b5cec4c5 | 660 | |
c04d6cfa | 661 | qemu_irq xics_get_qirq(XICSState *icp, int irq) |
b5cec4c5 | 662 | { |
641c3493 AK |
663 | int src = xics_find_source(icp, irq); |
664 | ||
665 | if (src >= 0) { | |
666 | ICSState *ics = &icp->ics[src]; | |
667 | return ics->qirqs[irq - ics->offset]; | |
b5cec4c5 DG |
668 | } |
669 | ||
641c3493 | 670 | return NULL; |
a307d594 AK |
671 | } |
672 | ||
4af88944 AK |
673 | static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) |
674 | { | |
675 | assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); | |
676 | ||
677 | ics->irqs[srcno].flags |= | |
678 | lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; | |
679 | } | |
680 | ||
c04d6cfa | 681 | void xics_set_irq_type(XICSState *icp, int irq, bool lsi) |
a307d594 | 682 | { |
641c3493 AK |
683 | int src = xics_find_source(icp, irq); |
684 | ICSState *ics; | |
4af88944 | 685 | |
641c3493 | 686 | assert(src >= 0); |
d07fee7e | 687 | |
641c3493 | 688 | ics = &icp->ics[src]; |
4af88944 | 689 | ics_set_irq_type(ics, irq - ics->offset, lsi); |
b5cec4c5 DG |
690 | } |
691 | ||
bee763db AK |
692 | #define ICS_IRQ_FREE(ics, srcno) \ |
693 | (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) | |
694 | ||
695 | static int ics_find_free_block(ICSState *ics, int num, int alignnum) | |
696 | { | |
697 | int first, i; | |
698 | ||
699 | for (first = 0; first < ics->nr_irqs; first += alignnum) { | |
700 | if (num > (ics->nr_irqs - first)) { | |
701 | return -1; | |
702 | } | |
703 | for (i = first; i < first + num; ++i) { | |
704 | if (!ICS_IRQ_FREE(ics, i)) { | |
705 | break; | |
706 | } | |
707 | } | |
708 | if (i == (first + num)) { | |
709 | return first; | |
710 | } | |
711 | } | |
712 | ||
713 | return -1; | |
714 | } | |
715 | ||
a005b3ef | 716 | int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp) |
bee763db AK |
717 | { |
718 | ICSState *ics = &icp->ics[src]; | |
719 | int irq; | |
720 | ||
721 | if (irq_hint) { | |
722 | assert(src == xics_find_source(icp, irq_hint)); | |
723 | if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { | |
a005b3ef | 724 | error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); |
bee763db AK |
725 | return -1; |
726 | } | |
727 | irq = irq_hint; | |
728 | } else { | |
729 | irq = ics_find_free_block(ics, 1, 1); | |
730 | if (irq < 0) { | |
a005b3ef | 731 | error_setg(errp, "can't allocate IRQ: no IRQ left"); |
bee763db AK |
732 | return -1; |
733 | } | |
734 | irq += ics->offset; | |
735 | } | |
736 | ||
737 | ics_set_irq_type(ics, irq - ics->offset, lsi); | |
738 | trace_xics_alloc(src, irq); | |
739 | ||
740 | return irq; | |
741 | } | |
742 | ||
743 | /* | |
67cc32eb | 744 | * Allocate block of consecutive IRQs, and return the number of the first IRQ in the block. |
bee763db AK |
745 | * If align==true, aligns the first IRQ number to num. |
746 | */ | |
a005b3ef GK |
747 | int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align, |
748 | Error **errp) | |
bee763db AK |
749 | { |
750 | int i, first = -1; | |
751 | ICSState *ics = &icp->ics[src]; | |
752 | ||
753 | assert(src == 0); | |
754 | /* | |
755 | * MSIMesage::data is used for storing VIRQ so | |
756 | * it has to be aligned to num to support multiple | |
757 | * MSI vectors. MSI-X is not affected by this. | |
758 | * The hint is used for the first IRQ, the rest should | |
759 | * be allocated continuously. | |
760 | */ | |
761 | if (align) { | |
762 | assert((num == 1) || (num == 2) || (num == 4) || | |
763 | (num == 8) || (num == 16) || (num == 32)); | |
764 | first = ics_find_free_block(ics, num, num); | |
765 | } else { | |
766 | first = ics_find_free_block(ics, num, 1); | |
767 | } | |
a005b3ef GK |
768 | if (first < 0) { |
769 | error_setg(errp, "can't find a free %d-IRQ block", num); | |
770 | return -1; | |
771 | } | |
bee763db AK |
772 | |
773 | if (first >= 0) { | |
774 | for (i = first; i < first + num; ++i) { | |
775 | ics_set_irq_type(ics, i, lsi); | |
776 | } | |
777 | } | |
778 | first += ics->offset; | |
779 | ||
780 | trace_xics_alloc_block(src, first, num, lsi, align); | |
781 | ||
782 | return first; | |
783 | } | |
784 | ||
51bba713 AK |
785 | static void ics_free(ICSState *ics, int srcno, int num) |
786 | { | |
787 | int i; | |
788 | ||
789 | for (i = srcno; i < srcno + num; ++i) { | |
790 | if (ICS_IRQ_FREE(ics, i)) { | |
791 | trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset); | |
792 | } | |
793 | memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); | |
794 | } | |
795 | } | |
796 | ||
797 | void xics_free(XICSState *icp, int irq, int num) | |
798 | { | |
799 | int src = xics_find_source(icp, irq); | |
800 | ||
801 | if (src >= 0) { | |
802 | ICSState *ics = &icp->ics[src]; | |
803 | ||
804 | /* FIXME: implement multiple sources */ | |
805 | assert(src == 0); | |
806 | ||
807 | trace_xics_ics_free(ics - icp->ics, irq, num); | |
808 | ics_free(ics, irq - ics->offset, num); | |
809 | } | |
810 | } | |
811 | ||
c04d6cfa AL |
812 | /* |
813 | * Guest interfaces | |
814 | */ | |
815 | ||
28e02042 | 816 | static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
b5cec4c5 DG |
817 | target_ulong opcode, target_ulong *args) |
818 | { | |
55e5c285 | 819 | CPUState *cs = CPU(cpu); |
b5cec4c5 DG |
820 | target_ulong cppr = args[0]; |
821 | ||
55e5c285 | 822 | icp_set_cppr(spapr->icp, cs->cpu_index, cppr); |
b5cec4c5 DG |
823 | return H_SUCCESS; |
824 | } | |
825 | ||
28e02042 | 826 | static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
b5cec4c5 DG |
827 | target_ulong opcode, target_ulong *args) |
828 | { | |
0f20ba62 | 829 | target_ulong server = get_cpu_index_by_dt_id(args[0]); |
b5cec4c5 DG |
830 | target_ulong mfrr = args[1]; |
831 | ||
832 | if (server >= spapr->icp->nr_servers) { | |
833 | return H_PARAMETER; | |
834 | } | |
835 | ||
836 | icp_set_mfrr(spapr->icp, server, mfrr); | |
837 | return H_SUCCESS; | |
b5cec4c5 DG |
838 | } |
839 | ||
28e02042 | 840 | static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
b5cec4c5 DG |
841 | target_ulong opcode, target_ulong *args) |
842 | { | |
55e5c285 AF |
843 | CPUState *cs = CPU(cpu); |
844 | uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index); | |
b5cec4c5 DG |
845 | |
846 | args[0] = xirr; | |
847 | return H_SUCCESS; | |
848 | } | |
849 | ||
28e02042 | 850 | static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
5d87e4b7 BH |
851 | target_ulong opcode, target_ulong *args) |
852 | { | |
853 | CPUState *cs = CPU(cpu); | |
854 | ICPState *ss = &spapr->icp->ss[cs->cpu_index]; | |
855 | uint32_t xirr = icp_accept(ss); | |
856 | ||
857 | args[0] = xirr; | |
4a7428c5 | 858 | args[1] = cpu_get_host_ticks(); |
5d87e4b7 BH |
859 | return H_SUCCESS; |
860 | } | |
861 | ||
28e02042 | 862 | static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
b5cec4c5 DG |
863 | target_ulong opcode, target_ulong *args) |
864 | { | |
55e5c285 | 865 | CPUState *cs = CPU(cpu); |
b5cec4c5 DG |
866 | target_ulong xirr = args[0]; |
867 | ||
55e5c285 | 868 | icp_eoi(spapr->icp, cs->cpu_index, xirr); |
b5cec4c5 DG |
869 | return H_SUCCESS; |
870 | } | |
871 | ||
28e02042 | 872 | static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
075edbe3 BH |
873 | target_ulong opcode, target_ulong *args) |
874 | { | |
875 | CPUState *cs = CPU(cpu); | |
876 | ICPState *ss = &spapr->icp->ss[cs->cpu_index]; | |
877 | ||
878 | args[0] = ss->xirr; | |
879 | args[1] = ss->mfrr; | |
880 | ||
881 | return H_SUCCESS; | |
882 | } | |
883 | ||
28e02042 | 884 | static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
210b580b | 885 | uint32_t token, |
b5cec4c5 DG |
886 | uint32_t nargs, target_ulong args, |
887 | uint32_t nret, target_ulong rets) | |
888 | { | |
c04d6cfa | 889 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
890 | uint32_t nr, server, priority; |
891 | ||
892 | if ((nargs != 3) || (nret != 1)) { | |
a64d325d | 893 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
894 | return; |
895 | } | |
896 | ||
897 | nr = rtas_ld(args, 0); | |
0f20ba62 | 898 | server = get_cpu_index_by_dt_id(rtas_ld(args, 1)); |
b5cec4c5 DG |
899 | priority = rtas_ld(args, 2); |
900 | ||
901 | if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers) | |
902 | || (priority > 0xff)) { | |
a64d325d | 903 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
904 | return; |
905 | } | |
906 | ||
3fe719f4 | 907 | ics_write_xive(ics, nr, server, priority, priority); |
b5cec4c5 | 908 | |
a64d325d | 909 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
b5cec4c5 DG |
910 | } |
911 | ||
28e02042 | 912 | static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
210b580b | 913 | uint32_t token, |
b5cec4c5 DG |
914 | uint32_t nargs, target_ulong args, |
915 | uint32_t nret, target_ulong rets) | |
916 | { | |
c04d6cfa | 917 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
918 | uint32_t nr; |
919 | ||
920 | if ((nargs != 1) || (nret != 3)) { | |
a64d325d | 921 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
922 | return; |
923 | } | |
924 | ||
925 | nr = rtas_ld(args, 0); | |
926 | ||
927 | if (!ics_valid_irq(ics, nr)) { | |
a64d325d | 928 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
929 | return; |
930 | } | |
931 | ||
a64d325d | 932 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
b5cec4c5 DG |
933 | rtas_st(rets, 1, ics->irqs[nr - ics->offset].server); |
934 | rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority); | |
935 | } | |
936 | ||
28e02042 | 937 | static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
210b580b | 938 | uint32_t token, |
b5cec4c5 DG |
939 | uint32_t nargs, target_ulong args, |
940 | uint32_t nret, target_ulong rets) | |
941 | { | |
c04d6cfa | 942 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
943 | uint32_t nr; |
944 | ||
945 | if ((nargs != 1) || (nret != 1)) { | |
a64d325d | 946 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
947 | return; |
948 | } | |
949 | ||
950 | nr = rtas_ld(args, 0); | |
951 | ||
952 | if (!ics_valid_irq(ics, nr)) { | |
a64d325d | 953 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
954 | return; |
955 | } | |
956 | ||
3fe719f4 DG |
957 | ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff, |
958 | ics->irqs[nr - ics->offset].priority); | |
b5cec4c5 | 959 | |
a64d325d | 960 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
b5cec4c5 DG |
961 | } |
962 | ||
28e02042 | 963 | static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
210b580b | 964 | uint32_t token, |
b5cec4c5 DG |
965 | uint32_t nargs, target_ulong args, |
966 | uint32_t nret, target_ulong rets) | |
967 | { | |
c04d6cfa | 968 | ICSState *ics = spapr->icp->ics; |
b5cec4c5 DG |
969 | uint32_t nr; |
970 | ||
971 | if ((nargs != 1) || (nret != 1)) { | |
a64d325d | 972 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
973 | return; |
974 | } | |
975 | ||
976 | nr = rtas_ld(args, 0); | |
977 | ||
978 | if (!ics_valid_irq(ics, nr)) { | |
a64d325d | 979 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
b5cec4c5 DG |
980 | return; |
981 | } | |
982 | ||
3fe719f4 DG |
983 | ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, |
984 | ics->irqs[nr - ics->offset].saved_priority, | |
985 | ics->irqs[nr - ics->offset].saved_priority); | |
b5cec4c5 | 986 | |
a64d325d | 987 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
b5cec4c5 DG |
988 | } |
989 | ||
c04d6cfa AL |
990 | /* |
991 | * XICS | |
992 | */ | |
993 | ||
5a3d7b23 AK |
994 | static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp) |
995 | { | |
996 | icp->nr_irqs = icp->ics->nr_irqs = nr_irqs; | |
997 | } | |
998 | ||
999 | static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, | |
1000 | Error **errp) | |
1001 | { | |
1002 | int i; | |
1003 | ||
1004 | icp->nr_servers = nr_servers; | |
1005 | ||
1006 | icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState)); | |
1007 | for (i = 0; i < icp->nr_servers; i++) { | |
1008 | char buffer[32]; | |
1009 | object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); | |
1010 | snprintf(buffer, sizeof(buffer), "icp[%d]", i); | |
1011 | object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), | |
1012 | errp); | |
1013 | } | |
1014 | } | |
1015 | ||
c04d6cfa | 1016 | static void xics_realize(DeviceState *dev, Error **errp) |
7b565160 | 1017 | { |
c04d6cfa | 1018 | XICSState *icp = XICS(dev); |
b45ff2d9 | 1019 | Error *error = NULL; |
c04d6cfa | 1020 | int i; |
b5cec4c5 | 1021 | |
b45ff2d9 AK |
1022 | if (!icp->nr_servers) { |
1023 | error_setg(errp, "Number of servers needs to be greater 0"); | |
1024 | return; | |
1025 | } | |
1026 | ||
33a0e5d8 | 1027 | /* Registration of global state belongs into realize */ |
3a3b8502 AK |
1028 | spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive); |
1029 | spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive); | |
1030 | spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off); | |
1031 | spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on); | |
33a0e5d8 AK |
1032 | |
1033 | spapr_register_hypercall(H_CPPR, h_cppr); | |
1034 | spapr_register_hypercall(H_IPI, h_ipi); | |
1035 | spapr_register_hypercall(H_XIRR, h_xirr); | |
5d87e4b7 | 1036 | spapr_register_hypercall(H_XIRR_X, h_xirr_x); |
33a0e5d8 | 1037 | spapr_register_hypercall(H_EOI, h_eoi); |
075edbe3 | 1038 | spapr_register_hypercall(H_IPOLL, h_ipoll); |
33a0e5d8 | 1039 | |
b45ff2d9 AK |
1040 | object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); |
1041 | if (error) { | |
1042 | error_propagate(errp, error); | |
1043 | return; | |
1044 | } | |
b5cec4c5 | 1045 | |
c04d6cfa | 1046 | for (i = 0; i < icp->nr_servers; i++) { |
b45ff2d9 AK |
1047 | object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error); |
1048 | if (error) { | |
1049 | error_propagate(errp, error); | |
1050 | return; | |
1051 | } | |
c04d6cfa AL |
1052 | } |
1053 | } | |
b5cec4c5 | 1054 | |
c04d6cfa AL |
1055 | static void xics_initfn(Object *obj) |
1056 | { | |
1057 | XICSState *xics = XICS(obj); | |
1058 | ||
1059 | xics->ics = ICS(object_new(TYPE_ICS)); | |
1060 | object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); | |
5a3d7b23 | 1061 | xics->ics->icp = xics; |
c04d6cfa AL |
1062 | } |
1063 | ||
c04d6cfa AL |
1064 | static void xics_class_init(ObjectClass *oc, void *data) |
1065 | { | |
1066 | DeviceClass *dc = DEVICE_CLASS(oc); | |
5a3d7b23 | 1067 | XICSStateClass *xsc = XICS_CLASS(oc); |
c04d6cfa AL |
1068 | |
1069 | dc->realize = xics_realize; | |
5a3d7b23 AK |
1070 | xsc->set_nr_irqs = xics_set_nr_irqs; |
1071 | xsc->set_nr_servers = xics_set_nr_servers; | |
c04d6cfa AL |
1072 | } |
1073 | ||
1074 | static const TypeInfo xics_info = { | |
1075 | .name = TYPE_XICS, | |
5a3d7b23 | 1076 | .parent = TYPE_XICS_COMMON, |
c04d6cfa | 1077 | .instance_size = sizeof(XICSState), |
5a3d7b23 | 1078 | .class_size = sizeof(XICSStateClass), |
c04d6cfa AL |
1079 | .class_init = xics_class_init, |
1080 | .instance_init = xics_initfn, | |
1081 | }; | |
256b408a | 1082 | |
c04d6cfa AL |
1083 | static void xics_register_types(void) |
1084 | { | |
5a3d7b23 | 1085 | type_register_static(&xics_common_info); |
c04d6cfa AL |
1086 | type_register_static(&xics_info); |
1087 | type_register_static(&ics_info); | |
1088 | type_register_static(&icp_info); | |
b5cec4c5 | 1089 | } |
c04d6cfa AL |
1090 | |
1091 | type_init(xics_register_types) |