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b2123a48 RH |
1 | /* |
2 | * ARM dummy L210, L220, PL310 cache controller. | |
3 | * | |
4 | * Copyright (c) 2010-2012 Calxeda | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or any later version, as published by the Free Software | |
9 | * Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | */ | |
20 | ||
0d1c9782 | 21 | #include "qemu/osdep.h" |
83c9f4ca | 22 | #include "hw/sysbus.h" |
03dd024f | 23 | #include "qemu/log.h" |
0b8fa32f | 24 | #include "qemu/module.h" |
b2123a48 RH |
25 | |
26 | /* L2C-310 r3p2 */ | |
27 | #define CACHE_ID 0x410000c8 | |
28 | ||
0e8982e9 AF |
29 | #define TYPE_ARM_L2X0 "l2x0" |
30 | #define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0) | |
31 | ||
ae1953d0 | 32 | typedef struct L2x0State { |
0e8982e9 AF |
33 | SysBusDevice parent_obj; |
34 | ||
b2123a48 RH |
35 | MemoryRegion iomem; |
36 | uint32_t cache_type; | |
37 | uint32_t ctrl; | |
38 | uint32_t aux_ctrl; | |
39 | uint32_t data_ctrl; | |
40 | uint32_t tag_ctrl; | |
41 | uint32_t filter_start; | |
42 | uint32_t filter_end; | |
ae1953d0 | 43 | } L2x0State; |
b2123a48 RH |
44 | |
45 | static const VMStateDescription vmstate_l2x0 = { | |
46 | .name = "l2x0", | |
47 | .version_id = 1, | |
48 | .minimum_version_id = 1, | |
49 | .fields = (VMStateField[]) { | |
ae1953d0 AF |
50 | VMSTATE_UINT32(ctrl, L2x0State), |
51 | VMSTATE_UINT32(aux_ctrl, L2x0State), | |
52 | VMSTATE_UINT32(data_ctrl, L2x0State), | |
53 | VMSTATE_UINT32(tag_ctrl, L2x0State), | |
54 | VMSTATE_UINT32(filter_start, L2x0State), | |
55 | VMSTATE_UINT32(filter_end, L2x0State), | |
b2123a48 RH |
56 | VMSTATE_END_OF_LIST() |
57 | } | |
58 | }; | |
59 | ||
60 | ||
a8170e5e | 61 | static uint64_t l2x0_priv_read(void *opaque, hwaddr offset, |
b2123a48 RH |
62 | unsigned size) |
63 | { | |
64 | uint32_t cache_data; | |
ae1953d0 | 65 | L2x0State *s = (L2x0State *)opaque; |
b2123a48 RH |
66 | offset &= 0xfff; |
67 | if (offset >= 0x730 && offset < 0x800) { | |
68 | return 0; /* cache ops complete */ | |
69 | } | |
70 | switch (offset) { | |
71 | case 0: | |
72 | return CACHE_ID; | |
73 | case 0x4: | |
74 | /* aux_ctrl values affect cache_type values */ | |
75 | cache_data = (s->aux_ctrl & (7 << 17)) >> 15; | |
76 | cache_data |= (s->aux_ctrl & (1 << 16)) >> 16; | |
77 | return s->cache_type |= (cache_data << 18) | (cache_data << 6); | |
78 | case 0x100: | |
79 | return s->ctrl; | |
80 | case 0x104: | |
81 | return s->aux_ctrl; | |
82 | case 0x108: | |
83 | return s->tag_ctrl; | |
84 | case 0x10C: | |
85 | return s->data_ctrl; | |
86 | case 0xC00: | |
87 | return s->filter_start; | |
88 | case 0xC04: | |
89 | return s->filter_end; | |
90 | case 0xF40: | |
91 | return 0; | |
92 | case 0xF60: | |
93 | return 0; | |
94 | case 0xF80: | |
95 | return 0; | |
96 | default: | |
a35d4e42 PM |
97 | qemu_log_mask(LOG_GUEST_ERROR, |
98 | "l2x0_priv_read: Bad offset %x\n", (int)offset); | |
b2123a48 RH |
99 | break; |
100 | } | |
101 | return 0; | |
102 | } | |
103 | ||
a8170e5e | 104 | static void l2x0_priv_write(void *opaque, hwaddr offset, |
b2123a48 RH |
105 | uint64_t value, unsigned size) |
106 | { | |
ae1953d0 | 107 | L2x0State *s = (L2x0State *)opaque; |
b2123a48 RH |
108 | offset &= 0xfff; |
109 | if (offset >= 0x730 && offset < 0x800) { | |
110 | /* ignore */ | |
111 | return; | |
112 | } | |
113 | switch (offset) { | |
114 | case 0x100: | |
115 | s->ctrl = value & 1; | |
116 | break; | |
117 | case 0x104: | |
118 | s->aux_ctrl = value; | |
119 | break; | |
120 | case 0x108: | |
121 | s->tag_ctrl = value; | |
122 | break; | |
123 | case 0x10C: | |
124 | s->data_ctrl = value; | |
125 | break; | |
126 | case 0xC00: | |
127 | s->filter_start = value; | |
128 | break; | |
129 | case 0xC04: | |
130 | s->filter_end = value; | |
131 | break; | |
132 | case 0xF40: | |
133 | return; | |
134 | case 0xF60: | |
135 | return; | |
136 | case 0xF80: | |
137 | return; | |
138 | default: | |
a35d4e42 PM |
139 | qemu_log_mask(LOG_GUEST_ERROR, |
140 | "l2x0_priv_write: Bad offset %x\n", (int)offset); | |
b2123a48 RH |
141 | break; |
142 | } | |
143 | } | |
144 | ||
145 | static void l2x0_priv_reset(DeviceState *dev) | |
146 | { | |
0e8982e9 | 147 | L2x0State *s = ARM_L2X0(dev); |
b2123a48 RH |
148 | |
149 | s->ctrl = 0; | |
150 | s->aux_ctrl = 0x02020000; | |
151 | s->tag_ctrl = 0; | |
152 | s->data_ctrl = 0; | |
153 | s->filter_start = 0; | |
154 | s->filter_end = 0; | |
155 | } | |
156 | ||
157 | static const MemoryRegionOps l2x0_mem_ops = { | |
158 | .read = l2x0_priv_read, | |
159 | .write = l2x0_priv_write, | |
160 | .endianness = DEVICE_NATIVE_ENDIAN, | |
161 | }; | |
162 | ||
da8060bf | 163 | static void l2x0_priv_init(Object *obj) |
b2123a48 | 164 | { |
da8060bf XZ |
165 | L2x0State *s = ARM_L2X0(obj); |
166 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
b2123a48 | 167 | |
da8060bf | 168 | memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s, |
3c161542 | 169 | "l2x0_cc", 0x1000); |
b2123a48 | 170 | sysbus_init_mmio(dev, &s->iomem); |
b2123a48 RH |
171 | } |
172 | ||
39bffca2 | 173 | static Property l2x0_properties[] = { |
ae1953d0 | 174 | DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100), |
39bffca2 AL |
175 | DEFINE_PROP_END_OF_LIST(), |
176 | }; | |
177 | ||
999e12bb AL |
178 | static void l2x0_class_init(ObjectClass *klass, void *data) |
179 | { | |
39bffca2 | 180 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 181 | |
39bffca2 | 182 | dc->vmsd = &vmstate_l2x0; |
39bffca2 AL |
183 | dc->props = l2x0_properties; |
184 | dc->reset = l2x0_priv_reset; | |
999e12bb AL |
185 | } |
186 | ||
8c43a6f0 | 187 | static const TypeInfo l2x0_info = { |
0e8982e9 | 188 | .name = TYPE_ARM_L2X0, |
39bffca2 | 189 | .parent = TYPE_SYS_BUS_DEVICE, |
ae1953d0 | 190 | .instance_size = sizeof(L2x0State), |
da8060bf | 191 | .instance_init = l2x0_priv_init, |
999e12bb | 192 | .class_init = l2x0_class_init, |
b2123a48 RH |
193 | }; |
194 | ||
83f7d43a | 195 | static void l2x0_register_types(void) |
b2123a48 | 196 | { |
39bffca2 | 197 | type_register_static(&l2x0_info); |
b2123a48 RH |
198 | } |
199 | ||
83f7d43a | 200 | type_init(l2x0_register_types) |