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Include qemu/module.h where needed, drop it from qemu-common.h
[thirdparty/qemu.git] / hw / pci-bridge / dec.c
CommitLineData
e1c6bbab
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1/*
2 * QEMU DEC 21154 PCI bridge
3 *
4 * Copyright (c) 2006-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
0d75590d 26#include "qemu/osdep.h"
47b43a1f 27#include "dec.h"
83c9f4ca 28#include "hw/sysbus.h"
0b8fa32f 29#include "qemu/module.h"
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30#include "hw/pci/pci.h"
31#include "hw/pci/pci_host.h"
32#include "hw/pci/pci_bridge.h"
33#include "hw/pci/pci_bus.h"
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34
35/* debug DEC */
36//#define DEBUG_DEC
37
38#ifdef DEBUG_DEC
39#define DEC_DPRINTF(fmt, ...) \
40 do { printf("DEC: " fmt , ## __VA_ARGS__); } while (0)
41#else
42#define DEC_DPRINTF(fmt, ...)
43#endif
44
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AF
45#define DEC_21154(obj) OBJECT_CHECK(DECState, (obj), TYPE_DEC_21154)
46
e1c6bbab 47typedef struct DECState {
67c332fd 48 PCIHostState parent_obj;
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49} DECState;
50
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51static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
52{
53 return irq_num;
54}
55
33c28f3b 56static void dec_pci_bridge_realize(PCIDevice *pci_dev, Error **errp)
60a0e443 57{
33c28f3b 58 pci_bridge_initfn(pci_dev, TYPE_PCI_BUS);
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AW
59}
60
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61static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)
62{
39bffca2 63 DeviceClass *dc = DEVICE_CLASS(klass);
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64 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
65
ba949713 66 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
33c28f3b 67 k->realize = dec_pci_bridge_realize;
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68 k->exit = pci_bridge_exitfn;
69 k->vendor_id = PCI_VENDOR_ID_DEC;
70 k->device_id = PCI_DEVICE_ID_DEC_21154;
71 k->config_write = pci_bridge_write_config;
91f4c995 72 k->is_bridge = true;
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73 dc->desc = "DEC 21154 PCI-PCI bridge";
74 dc->reset = pci_bridge_reset;
75 dc->vmsd = &vmstate_pci_device;
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76}
77
4240abff 78static const TypeInfo dec_21154_pci_bridge_info = {
39bffca2 79 .name = "dec-21154-p2p-bridge",
f055e96b 80 .parent = TYPE_PCI_BRIDGE,
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81 .instance_size = sizeof(PCIBridge),
82 .class_init = dec_21154_pci_bridge_class_init,
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83 .interfaces = (InterfaceInfo[]) {
84 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
85 { },
86 },
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87};
88
89PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
90{
91 PCIDevice *dev;
92 PCIBridge *br;
d55380bb 93
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94 dev = pci_create_multifunction(parent_bus, devfn, false,
95 "dec-21154-p2p-bridge");
f055e96b 96 br = PCI_BRIDGE(dev);
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97 pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
98 qdev_init_nofail(&dev->qdev);
99 return pci_bridge_get_sec_bus(br);
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100}
101
9b27555a 102static void pci_dec_21154_device_realize(DeviceState *dev, Error **errp)
e1c6bbab 103{
ab615367 104 PCIHostState *phb;
9b27555a 105 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
e1c6bbab 106
8558d942 107 phb = PCI_HOST_BRIDGE(dev);
e1c6bbab 108
40c5dce9 109 memory_region_init_io(&phb->conf_mem, OBJECT(dev), &pci_host_conf_le_ops,
ab615367 110 dev, "pci-conf-idx", 0x1000);
40c5dce9 111 memory_region_init_io(&phb->data_mem, OBJECT(dev), &pci_host_data_le_ops,
ab615367 112 dev, "pci-data-idx", 0x1000);
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113 sysbus_init_mmio(sbd, &phb->conf_mem);
114 sysbus_init_mmio(sbd, &phb->data_mem);
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115}
116
9af21dbe 117static void dec_21154_pci_host_realize(PCIDevice *d, Error **errp)
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118{
119 /* PCI2PCI bridge same values as PearPC - check this */
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120}
121
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122static void dec_21154_pci_host_class_init(ObjectClass *klass, void *data)
123{
124 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92 125 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 126
ba949713 127 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
9af21dbe 128 k->realize = dec_21154_pci_host_realize;
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129 k->vendor_id = PCI_VENDOR_ID_DEC;
130 k->device_id = PCI_DEVICE_ID_DEC_21154;
131 k->revision = 0x02;
132 k->class_id = PCI_CLASS_BRIDGE_PCI;
91f4c995 133 k->is_bridge = true;
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134 /*
135 * PCI-facing part of the host bridge, not usable without the
136 * host-facing part, which can't be device_add'ed, yet.
137 */
e90f2a8c 138 dc->user_creatable = false;
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139}
140
4240abff 141static const TypeInfo dec_21154_pci_host_info = {
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142 .name = "dec-21154",
143 .parent = TYPE_PCI_DEVICE,
144 .instance_size = sizeof(PCIDevice),
145 .class_init = dec_21154_pci_host_class_init,
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146 .interfaces = (InterfaceInfo[]) {
147 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
148 { },
149 },
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150};
151
999e12bb 152static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data)
e1c6bbab 153{
9b27555a 154 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 155
9b27555a 156 dc->realize = pci_dec_21154_device_realize;
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157}
158
4240abff 159static const TypeInfo pci_dec_21154_device_info = {
ab615367 160 .name = TYPE_DEC_21154,
8558d942 161 .parent = TYPE_PCI_HOST_BRIDGE,
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162 .instance_size = sizeof(DECState),
163 .class_init = pci_dec_21154_device_class_init,
999e12bb 164};
40021f08 165
83f7d43a 166static void dec_register_types(void)
999e12bb 167{
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168 type_register_static(&pci_dec_21154_device_info);
169 type_register_static(&dec_21154_pci_host_info);
170 type_register_static(&dec_21154_pci_bridge_info);
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171}
172
83f7d43a 173type_init(dec_register_types)