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Commit | Line | Data |
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502a5395 | 1 | /* |
3cbee15b | 2 | * QEMU Grackle PCI host (heathrow OldWorld PowerMac) |
502a5395 | 3 | * |
3cbee15b JM |
4 | * Copyright (c) 2006-2007 Fabrice Bellard |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
5fafdf24 | 6 | * |
502a5395 PB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
0d75590d | 26 | #include "qemu/osdep.h" |
83c9f4ca PB |
27 | #include "hw/pci/pci_host.h" |
28 | #include "hw/ppc/mac.h" | |
29 | #include "hw/pci/pci.h" | |
b0318ec1 MCA |
30 | #include "hw/intc/heathrow_pic.h" |
31 | #include "qapi/error.h" | |
0b8fa32f | 32 | #include "qemu/module.h" |
b728fbbc | 33 | #include "trace.h" |
ea026b2f | 34 | |
0e655047 AF |
35 | #define GRACKLE_PCI_HOST_BRIDGE(obj) \ |
36 | OBJECT_CHECK(GrackleState, (obj), TYPE_GRACKLE_PCI_HOST_BRIDGE) | |
37 | ||
426f17bb | 38 | typedef struct GrackleState { |
67c332fd | 39 | PCIHostState parent_obj; |
0e655047 | 40 | |
ac43eb2e | 41 | uint32_t ofw_addr; |
b0318ec1 MCA |
42 | HeathrowState *pic; |
43 | qemu_irq irqs[4]; | |
46f3069c BS |
44 | MemoryRegion pci_mmio; |
45 | MemoryRegion pci_hole; | |
a94e5f99 | 46 | MemoryRegion pci_io; |
426f17bb | 47 | } GrackleState; |
502a5395 | 48 | |
d2b59317 PB |
49 | /* Don't know if this matches real hardware, but it agrees with OHW. */ |
50 | static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) | |
502a5395 | 51 | { |
d2b59317 PB |
52 | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
53 | } | |
54 | ||
5d4e84c8 | 55 | static void pci_grackle_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 56 | { |
b0318ec1 | 57 | GrackleState *s = opaque; |
5d4e84c8 | 58 | |
b728fbbc | 59 | trace_grackle_set_irq(irq_num, level); |
b0318ec1 | 60 | qemu_set_irq(s->irqs[irq_num], level); |
502a5395 PB |
61 | } |
62 | ||
b0318ec1 MCA |
63 | static void grackle_init_irqs(GrackleState *s) |
64 | { | |
65 | int i; | |
66 | ||
67 | for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { | |
68 | s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), 0x15 + i); | |
69 | } | |
70 | } | |
71 | ||
b0318ec1 MCA |
72 | static void grackle_realize(DeviceState *dev, Error **errp) |
73 | { | |
74 | GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev); | |
75 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); | |
76 | ||
1115ff6d DG |
77 | phb->bus = pci_register_root_bus(dev, NULL, |
78 | pci_grackle_set_irq, | |
79 | pci_grackle_map_irq, | |
b0318ec1 MCA |
80 | s, |
81 | &s->pci_mmio, | |
a94e5f99 | 82 | &s->pci_io, |
1115ff6d | 83 | 0, 4, TYPE_PCI_BUS); |
426f17bb | 84 | |
0e655047 | 85 | pci_create_simple(phb->bus, 0, "grackle"); |
b0318ec1 | 86 | grackle_init_irqs(s); |
426f17bb BS |
87 | } |
88 | ||
b0318ec1 | 89 | static void grackle_init(Object *obj) |
426f17bb | 90 | { |
b0318ec1 MCA |
91 | GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj); |
92 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
93 | PCIHostState *phb = PCI_HOST_BRIDGE(obj); | |
426f17bb | 94 | |
b0318ec1 | 95 | memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); |
a94e5f99 MCA |
96 | memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, |
97 | "pci-isa-mmio", 0x00200000); | |
98 | ||
b0318ec1 MCA |
99 | memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio, |
100 | 0x80000000ULL, 0x7e000000ULL); | |
426f17bb | 101 | |
b0318ec1 MCA |
102 | memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, |
103 | DEVICE(obj), "pci-conf-idx", 0x1000); | |
104 | memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, | |
105 | DEVICE(obj), "pci-data-idx", 0x1000); | |
426f17bb | 106 | |
b0318ec1 MCA |
107 | object_property_add_link(obj, "pic", TYPE_HEATHROW, |
108 | (Object **) &s->pic, | |
109 | qdev_prop_allow_set_link_before_realize, | |
110 | 0, NULL); | |
111 | ||
112 | sysbus_init_mmio(sbd, &phb->conf_mem); | |
113 | sysbus_init_mmio(sbd, &phb->data_mem); | |
a773e64a | 114 | sysbus_init_mmio(sbd, &s->pci_hole); |
a94e5f99 | 115 | sysbus_init_mmio(sbd, &s->pci_io); |
426f17bb BS |
116 | } |
117 | ||
b0318ec1 | 118 | static void grackle_pci_realize(PCIDevice *d, Error **errp) |
426f17bb | 119 | { |
502a5395 | 120 | d->config[0x09] = 0x01; |
426f17bb | 121 | } |
502a5395 | 122 | |
40021f08 AL |
123 | static void grackle_pci_class_init(ObjectClass *klass, void *data) |
124 | { | |
39bffca2 | 125 | DeviceClass *dc = DEVICE_CLASS(klass); |
b0318ec1 | 126 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
40021f08 | 127 | |
b0318ec1 | 128 | k->realize = grackle_pci_realize; |
40021f08 AL |
129 | k->vendor_id = PCI_VENDOR_ID_MOTOROLA; |
130 | k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106; | |
131 | k->revision = 0x00; | |
132 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
133 | /* |
134 | * PCI-facing part of the host bridge, not usable without the | |
135 | * host-facing part, which can't be device_add'ed, yet. | |
136 | */ | |
e90f2a8c | 137 | dc->user_creatable = false; |
40021f08 AL |
138 | } |
139 | ||
4240abff | 140 | static const TypeInfo grackle_pci_info = { |
39bffca2 AL |
141 | .name = "grackle", |
142 | .parent = TYPE_PCI_DEVICE, | |
143 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 144 | .class_init = grackle_pci_class_init, |
fd3b02c8 EH |
145 | .interfaces = (InterfaceInfo[]) { |
146 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
147 | { }, | |
148 | }, | |
426f17bb | 149 | }; |
6e6b7363 | 150 | |
ac43eb2e MCA |
151 | static char *grackle_ofw_unit_address(const SysBusDevice *dev) |
152 | { | |
153 | GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev); | |
154 | ||
155 | return g_strdup_printf("%x", s->ofw_addr); | |
156 | } | |
157 | ||
158 | static Property grackle_properties[] = { | |
159 | DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1), | |
160 | DEFINE_PROP_END_OF_LIST() | |
161 | }; | |
162 | ||
b0318ec1 | 163 | static void grackle_class_init(ObjectClass *klass, void *data) |
999e12bb | 164 | { |
e1624435 | 165 | DeviceClass *dc = DEVICE_CLASS(klass); |
ac43eb2e | 166 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
999e12bb | 167 | |
b0318ec1 | 168 | dc->realize = grackle_realize; |
ac43eb2e | 169 | dc->props = grackle_properties; |
e1624435 | 170 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
ac43eb2e MCA |
171 | dc->fw_name = "pci"; |
172 | sbc->explicit_ofw_unit_address = grackle_ofw_unit_address; | |
999e12bb AL |
173 | } |
174 | ||
b0318ec1 | 175 | static const TypeInfo grackle_host_info = { |
0e655047 | 176 | .name = TYPE_GRACKLE_PCI_HOST_BRIDGE, |
8558d942 | 177 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 178 | .instance_size = sizeof(GrackleState), |
b0318ec1 MCA |
179 | .instance_init = grackle_init, |
180 | .class_init = grackle_class_init, | |
0ae46996 AF |
181 | }; |
182 | ||
83f7d43a | 183 | static void grackle_register_types(void) |
426f17bb | 184 | { |
39bffca2 | 185 | type_register_static(&grackle_pci_info); |
b0318ec1 | 186 | type_register_static(&grackle_host_info); |
502a5395 | 187 | } |
426f17bb | 188 | |
83f7d43a | 189 | type_init(grackle_register_types) |