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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
b6a0aa05 | 25 | #include "qemu/osdep.h" |
83c9f4ca | 26 | #include "hw/hw.h" |
0d09e41a | 27 | #include "hw/i386/pc.h" |
83c9f4ca PB |
28 | #include "hw/pci/pci.h" |
29 | #include "hw/pci/pci_host.h" | |
0d09e41a | 30 | #include "hw/isa/isa.h" |
83c9f4ca | 31 | #include "hw/sysbus.h" |
da34e65c | 32 | #include "qapi/error.h" |
1de7afc9 | 33 | #include "qemu/range.h" |
0d09e41a PB |
34 | #include "hw/xen/xen.h" |
35 | #include "hw/pci-host/pam.h" | |
1ec4ba74 | 36 | #include "sysemu/sysemu.h" |
39848901 IM |
37 | #include "hw/i386/ioapic.h" |
38 | #include "qapi/visitor.h" | |
8d211f62 | 39 | #include "qemu/error-report.h" |
87ecb68b | 40 | |
56594fe3 IY |
41 | /* |
42 | * I440FX chipset data sheet. | |
43 | * http://download.intel.com/design/chipsets/datashts/29054901.pdf | |
44 | */ | |
45 | ||
1d0d4aa4 IM |
46 | #define I440FX_PCI_HOST_BRIDGE(obj) \ |
47 | OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE) | |
48 | ||
67c332fd AF |
49 | typedef struct I440FXState { |
50 | PCIHostState parent_obj; | |
39848901 IM |
51 | PcPciInfo pci_info; |
52 | uint64_t pci_hole64_size; | |
04c7d8b8 | 53 | uint32_t short_root_bus; |
67c332fd | 54 | } I440FXState; |
502a5395 | 55 | |
ab431c28 | 56 | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
e735b55a | 57 | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
bf09551a | 58 | #define XEN_PIIX_NUM_PIRQS 128ULL |
ab431c28 | 59 | #define PIIX_PIRQC 0x60 |
e735b55a | 60 | |
1ec4ba74 LE |
61 | /* |
62 | * Reset Control Register: PCI-accessible ISA-Compatible Register at address | |
63 | * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). | |
64 | */ | |
65 | #define RCR_IOPORT 0xcf9 | |
66 | ||
fd37d881 JQ |
67 | typedef struct PIIX3State { |
68 | PCIDevice dev; | |
ab431c28 IY |
69 | |
70 | /* | |
71 | * bitmap to track pic levels. | |
72 | * The pic level is the logical OR of all the PCI irqs mapped to it | |
73 | * So one PIC level is tracked by PIIX_NUM_PIRQS bits. | |
74 | * | |
75 | * PIRQ is mapped to PIC pins, we track it by | |
76 | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with | |
77 | * pic_irq * PIIX_NUM_PIRQS + pirq | |
78 | */ | |
79 | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 | |
80 | #error "unable to encode pic state in 64bit in pic_levels." | |
81 | #endif | |
82 | uint64_t pic_levels; | |
83 | ||
bd7dce87 | 84 | qemu_irq *pic; |
e735b55a IY |
85 | |
86 | /* This member isn't used. Just for save/load compatibility */ | |
87 | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; | |
1ec4ba74 LE |
88 | |
89 | /* Reset Control Register contents */ | |
90 | uint8_t rcr; | |
91 | ||
92 | /* IO memory region for Reset Control Register (RCR_IOPORT) */ | |
93 | MemoryRegion rcr_mem; | |
7cd9eee0 | 94 | } PIIX3State; |
bd7dce87 | 95 | |
b7c69719 GA |
96 | #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" |
97 | #define PIIX3_PCI_DEVICE(obj) \ | |
98 | OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE) | |
99 | ||
57a0f0c6 DW |
100 | #define I440FX_PCI_DEVICE(obj) \ |
101 | OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) | |
102 | ||
0a3bacf3 | 103 | struct PCII440FXState { |
2aedfa46 HT |
104 | /*< private >*/ |
105 | PCIDevice parent_obj; | |
106 | /*< public >*/ | |
107 | ||
ae0a5466 AK |
108 | MemoryRegion *system_memory; |
109 | MemoryRegion *pci_address_space; | |
110 | MemoryRegion *ram_memory; | |
ae0a5466 AK |
111 | PAMMemoryRegion pam_regions[13]; |
112 | MemoryRegion smram_region; | |
fe6567d5 | 113 | MemoryRegion smram, low_smram; |
0a3bacf3 JQ |
114 | }; |
115 | ||
f2c688bb IY |
116 | |
117 | #define I440FX_PAM 0x59 | |
118 | #define I440FX_PAM_SIZE 7 | |
119 | #define I440FX_SMRAM 0x72 | |
120 | ||
e33d22fa EH |
121 | /* Older coreboot versions (4.0 and older) read a config register that doesn't |
122 | * exist in real hardware, to get the RAM size from QEMU. | |
123 | */ | |
124 | #define I440FX_COREBOOT_RAM_SIZE 0x57 | |
125 | ||
ab431c28 | 126 | static void piix3_set_irq(void *opaque, int pirq, int level); |
3afa9bb4 | 127 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); |
bf09551a SS |
128 | static void piix3_write_config_xen(PCIDevice *dev, |
129 | uint32_t address, uint32_t val, int len); | |
d2b59317 PB |
130 | |
131 | /* return the global irq number corresponding to a given device irq | |
132 | pin. We could also use the bus number to have a more precise | |
133 | mapping. */ | |
ab431c28 | 134 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
d2b59317 PB |
135 | { |
136 | int slot_addend; | |
137 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
ab431c28 | 138 | return (pci_intx + slot_addend) & 3; |
d2b59317 | 139 | } |
502a5395 | 140 | |
0a3bacf3 | 141 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 | 142 | { |
410edd92 | 143 | int i; |
2aedfa46 | 144 | PCIDevice *pd = PCI_DEVICE(d); |
84631fd7 | 145 | |
72124c01 | 146 | memory_region_transaction_begin(); |
410edd92 IY |
147 | for (i = 0; i < 13; i++) { |
148 | pam_update(&d->pam_regions[i], i, | |
2aedfa46 | 149 | pd->config[I440FX_PAM + ((i + 1) / 2)]); |
ee0ea1d0 | 150 | } |
3de70c08 PB |
151 | memory_region_set_enabled(&d->smram_region, |
152 | !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); | |
fe6567d5 PB |
153 | memory_region_set_enabled(&d->smram, |
154 | pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME); | |
72124c01 | 155 | memory_region_transaction_commit(); |
ee0ea1d0 FB |
156 | } |
157 | ||
ee0ea1d0 | 158 | |
0a3bacf3 | 159 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
160 | uint32_t address, uint32_t val, int len) |
161 | { | |
57a0f0c6 | 162 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
0a3bacf3 | 163 | |
ee0ea1d0 | 164 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 165 | pci_default_write_config(dev, address, val, len); |
4da5fcd3 IY |
166 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
167 | range_covers_byte(address, len, I440FX_SMRAM)) { | |
ee0ea1d0 | 168 | i440fx_update_memory_mappings(d); |
4da5fcd3 | 169 | } |
ee0ea1d0 FB |
170 | } |
171 | ||
0c7d19e5 | 172 | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
ee0ea1d0 | 173 | { |
0a3bacf3 | 174 | PCII440FXState *d = opaque; |
2aedfa46 | 175 | PCIDevice *pd = PCI_DEVICE(d); |
52fc1d83 | 176 | int ret, i; |
f809c605 | 177 | uint8_t smm_enabled; |
ee0ea1d0 | 178 | |
2aedfa46 | 179 | ret = pci_device_load(pd, f); |
ee0ea1d0 FB |
180 | if (ret < 0) |
181 | return ret; | |
182 | i440fx_update_memory_mappings(d); | |
f809c605 | 183 | qemu_get_8s(f, &smm_enabled); |
52fc1d83 | 184 | |
e735b55a IY |
185 | if (version_id == 2) { |
186 | for (i = 0; i < PIIX_NUM_PIRQS; i++) { | |
187 | qemu_get_be32(f); /* dummy load for compatibility */ | |
188 | } | |
189 | } | |
52fc1d83 | 190 | |
ee0ea1d0 FB |
191 | return 0; |
192 | } | |
193 | ||
e59fb374 | 194 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
195 | { |
196 | PCII440FXState *d = opaque; | |
197 | ||
198 | i440fx_update_memory_mappings(d); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | static const VMStateDescription vmstate_i440fx = { | |
203 | .name = "I440FX", | |
204 | .version_id = 3, | |
205 | .minimum_version_id = 3, | |
206 | .minimum_version_id_old = 1, | |
207 | .load_state_old = i440fx_load_old, | |
752ff2fa | 208 | .post_load = i440fx_post_load, |
d49805ae | 209 | .fields = (VMStateField[]) { |
2aedfa46 | 210 | VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), |
f809c605 PB |
211 | /* Used to be smm_enabled, which was basically always zero because |
212 | * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. | |
213 | */ | |
214 | VMSTATE_UNUSED(1), | |
0c7d19e5 JQ |
215 | VMSTATE_END_OF_LIST() |
216 | } | |
217 | }; | |
218 | ||
39848901 | 219 | static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v, |
d7bce999 | 220 | const char *name, void *opaque, |
39848901 IM |
221 | Error **errp) |
222 | { | |
223 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
224 | uint32_t value = s->pci_info.w32.begin; | |
225 | ||
51e72bc1 | 226 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
227 | } |
228 | ||
229 | static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v, | |
d7bce999 | 230 | const char *name, void *opaque, |
39848901 IM |
231 | Error **errp) |
232 | { | |
233 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
234 | uint32_t value = s->pci_info.w32.end; | |
235 | ||
51e72bc1 | 236 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
237 | } |
238 | ||
239 | static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, | |
d7bce999 EB |
240 | const char *name, |
241 | void *opaque, Error **errp) | |
39848901 | 242 | { |
2028fdf3 MT |
243 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
244 | Range w64; | |
245 | ||
246 | pci_bus_get_w64_range(h->bus, &w64); | |
39848901 | 247 | |
51e72bc1 | 248 | visit_type_uint64(v, name, &w64.begin, errp); |
39848901 IM |
249 | } |
250 | ||
251 | static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, | |
d7bce999 | 252 | const char *name, void *opaque, |
39848901 IM |
253 | Error **errp) |
254 | { | |
2028fdf3 MT |
255 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
256 | Range w64; | |
257 | ||
258 | pci_bus_get_w64_range(h->bus, &w64); | |
39848901 | 259 | |
51e72bc1 | 260 | visit_type_uint64(v, name, &w64.end, errp); |
39848901 IM |
261 | } |
262 | ||
a3560fbf | 263 | static void i440fx_pcihost_initfn(Object *obj) |
502a5395 | 264 | { |
a3560fbf | 265 | PCIHostState *s = PCI_HOST_BRIDGE(obj); |
39848901 | 266 | I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj); |
502a5395 | 267 | |
a3560fbf | 268 | memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, |
d0ed8076 | 269 | "pci-conf-idx", 4); |
a3560fbf | 270 | memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, |
d0ed8076 | 271 | "pci-conf-data", 4); |
39848901 IM |
272 | |
273 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", | |
274 | i440fx_pcihost_get_pci_hole_start, | |
275 | NULL, NULL, NULL, NULL); | |
276 | ||
277 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", | |
278 | i440fx_pcihost_get_pci_hole_end, | |
279 | NULL, NULL, NULL, NULL); | |
280 | ||
281 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", | |
282 | i440fx_pcihost_get_pci_hole64_start, | |
283 | NULL, NULL, NULL, NULL); | |
284 | ||
285 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", | |
286 | i440fx_pcihost_get_pci_hole64_end, | |
287 | NULL, NULL, NULL, NULL); | |
288 | ||
289 | d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; | |
a3560fbf | 290 | } |
502a5395 | 291 | |
a3560fbf HT |
292 | static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) |
293 | { | |
294 | PCIHostState *s = PCI_HOST_BRIDGE(dev); | |
295 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
296 | ||
297 | sysbus_add_io(sbd, 0xcf8, &s->conf_mem); | |
298 | sysbus_init_ioports(sbd, 0xcf8, 4); | |
299 | ||
300 | sysbus_add_io(sbd, 0xcfc, &s->data_mem); | |
301 | sysbus_init_ioports(sbd, 0xcfc, 4); | |
8a14daa5 | 302 | } |
502a5395 | 303 | |
9af21dbe | 304 | static void i440fx_realize(PCIDevice *dev, Error **errp) |
8a14daa5 | 305 | { |
2aedfa46 | 306 | dev->config[I440FX_SMRAM] = 0x02; |
8d211f62 BD |
307 | |
308 | if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { | |
309 | error_report("warning: i440fx doesn't support emulated iommu"); | |
310 | } | |
8a14daa5 GH |
311 | } |
312 | ||
7bb836e4 MT |
313 | PCIBus *i440fx_init(const char *host_type, const char *pci_type, |
314 | PCII440FXState **pi440fx_state, | |
44fc8c5e IM |
315 | int *piix3_devfn, |
316 | ISABus **isa_bus, qemu_irq *pic, | |
317 | MemoryRegion *address_space_mem, | |
318 | MemoryRegion *address_space_io, | |
319 | ram_addr_t ram_size, | |
ddaaefb4 | 320 | ram_addr_t below_4g_mem_size, |
39848901 | 321 | ram_addr_t above_4g_mem_size, |
44fc8c5e IM |
322 | MemoryRegion *pci_address_space, |
323 | MemoryRegion *ram_memory) | |
8a14daa5 GH |
324 | { |
325 | DeviceState *dev; | |
326 | PCIBus *b; | |
327 | PCIDevice *d; | |
8558d942 | 328 | PCIHostState *s; |
7cd9eee0 | 329 | PIIX3State *piix3; |
ae0a5466 | 330 | PCII440FXState *f; |
2725aec7 | 331 | unsigned i; |
39848901 | 332 | I440FXState *i440fx; |
8a14daa5 | 333 | |
7bb836e4 | 334 | dev = qdev_create(NULL, host_type); |
8558d942 | 335 | s = PCI_HOST_BRIDGE(dev); |
67c332fd | 336 | b = pci_bus_new(dev, NULL, pci_address_space, |
60a0e443 | 337 | address_space_io, 0, TYPE_PCI_BUS); |
8a14daa5 | 338 | s->bus = b; |
f05f6b4a | 339 | object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); |
f424d5c4 | 340 | qdev_init_nofail(dev); |
8a14daa5 | 341 | |
7bb836e4 | 342 | d = pci_create_simple(b, 0, pci_type); |
57a0f0c6 | 343 | *pi440fx_state = I440FX_PCI_DEVICE(d); |
ae0a5466 AK |
344 | f = *pi440fx_state; |
345 | f->system_memory = address_space_mem; | |
346 | f->pci_address_space = pci_address_space; | |
347 | f->ram_memory = ram_memory; | |
39848901 IM |
348 | |
349 | i440fx = I440FX_PCI_HOST_BRIDGE(dev); | |
ddaaefb4 | 350 | i440fx->pci_info.w32.begin = below_4g_mem_size; |
39848901 | 351 | |
83d08f26 MT |
352 | /* setup pci memory mapping */ |
353 | pc_pci_as_mapping_init(OBJECT(f), f->system_memory, | |
354 | f->pci_address_space); | |
355 | ||
fe6567d5 | 356 | /* if *disabled* show SMRAM to all CPUs */ |
40c5dce9 | 357 | memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", |
ae0a5466 | 358 | f->pci_address_space, 0xa0000, 0x20000); |
b41e1ed4 AK |
359 | memory_region_add_subregion_overlap(f->system_memory, 0xa0000, |
360 | &f->smram_region, 1); | |
fe6567d5 PB |
361 | memory_region_set_enabled(&f->smram_region, true); |
362 | ||
363 | /* smram, as seen by SMM CPUs */ | |
364 | memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32); | |
365 | memory_region_set_enabled(&f->smram, true); | |
366 | memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", | |
f809c605 | 367 | f->ram_memory, 0xa0000, 0x20000); |
fe6567d5 PB |
368 | memory_region_set_enabled(&f->low_smram, true); |
369 | memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram); | |
370 | object_property_add_const_link(qdev_get_machine(), "smram", | |
371 | OBJECT(&f->smram), &error_abort); | |
372 | ||
3cd2cf43 | 373 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 | 374 | &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); |
2725aec7 | 375 | for (i = 0; i < 12; ++i) { |
3cd2cf43 | 376 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 IY |
377 | &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, |
378 | PAM_EXPAN_SIZE); | |
2725aec7 | 379 | } |
8a14daa5 | 380 | |
bf09551a SS |
381 | /* Xen supports additional interrupt routes from the PCI devices to |
382 | * the IOAPIC: the four pins of each PCI device on the bus are also | |
383 | * connected to the IOAPIC directly. | |
384 | * These additional routes can be discovered through ACPI. */ | |
385 | if (xen_enabled()) { | |
b7c69719 GA |
386 | PCIDevice *pci_dev = pci_create_simple_multifunction(b, |
387 | -1, true, "PIIX3-xen"); | |
388 | piix3 = PIIX3_PCI_DEVICE(pci_dev); | |
bf09551a SS |
389 | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, |
390 | piix3, XEN_PIIX_NUM_PIRQS); | |
391 | } else { | |
b7c69719 GA |
392 | PCIDevice *pci_dev = pci_create_simple_multifunction(b, |
393 | -1, true, "PIIX3"); | |
394 | piix3 = PIIX3_PCI_DEVICE(pci_dev); | |
bf09551a SS |
395 | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, |
396 | PIIX_NUM_PIRQS); | |
3afa9bb4 | 397 | pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); |
bf09551a | 398 | } |
7cd9eee0 | 399 | piix3->pic = pic; |
d93a8a43 | 400 | *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); |
41445300 | 401 | |
7cd9eee0 | 402 | *piix3_devfn = piix3->dev.devfn; |
85a750ca | 403 | |
ec5f92ce | 404 | ram_size = ram_size / 8 / 1024 / 1024; |
2aedfa46 | 405 | if (ram_size > 255) { |
ec5f92ce | 406 | ram_size = 255; |
2aedfa46 | 407 | } |
e33d22fa | 408 | d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; |
ec5f92ce | 409 | |
ae0a5466 AK |
410 | i440fx_update_memory_mappings(f); |
411 | ||
502a5395 PB |
412 | return b; |
413 | } | |
414 | ||
277e9340 MT |
415 | PCIBus *find_i440fx(void) |
416 | { | |
417 | PCIHostState *s = OBJECT_CHECK(PCIHostState, | |
418 | object_resolve_path("/machine/i440fx", NULL), | |
419 | TYPE_PCI_HOST_BRIDGE); | |
420 | return s ? s->bus : NULL; | |
421 | } | |
422 | ||
502a5395 | 423 | /* PIIX3 PCI to ISA bridge */ |
ab431c28 IY |
424 | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
425 | { | |
426 | qemu_set_irq(piix3->pic[pic_irq], | |
427 | !!(piix3->pic_levels & | |
09de0f46 | 428 | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
ab431c28 IY |
429 | (pic_irq * PIIX_NUM_PIRQS)))); |
430 | } | |
502a5395 | 431 | |
2c9ecdeb | 432 | static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) |
ab431c28 IY |
433 | { |
434 | int pic_irq; | |
435 | uint64_t mask; | |
436 | ||
437 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
438 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
439 | return; | |
440 | } | |
441 | ||
442 | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); | |
443 | piix3->pic_levels &= ~mask; | |
444 | piix3->pic_levels |= mask * !!level; | |
2c9ecdeb PD |
445 | } |
446 | ||
447 | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) | |
448 | { | |
449 | int pic_irq; | |
450 | ||
451 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
452 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
453 | return; | |
454 | } | |
455 | ||
456 | piix3_set_irq_level_internal(piix3, pirq, level); | |
ab431c28 | 457 | |
afe3ef1d | 458 | piix3_set_irq_pic(piix3, pic_irq); |
ab431c28 IY |
459 | } |
460 | ||
461 | static void piix3_set_irq(void *opaque, int pirq, int level) | |
502a5395 | 462 | { |
7cd9eee0 | 463 | PIIX3State *piix3 = opaque; |
afe3ef1d | 464 | piix3_set_irq_level(piix3, pirq, level); |
ab431c28 | 465 | } |
502a5395 | 466 | |
3afa9bb4 MT |
467 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) |
468 | { | |
469 | PIIX3State *piix3 = opaque; | |
470 | int irq = piix3->dev.config[PIIX_PIRQC + pin]; | |
471 | PCIINTxRoute route; | |
472 | ||
473 | if (irq < PIIX_NUM_PIC_IRQS) { | |
474 | route.mode = PCI_INTX_ENABLED; | |
475 | route.irq = irq; | |
476 | } else { | |
477 | route.mode = PCI_INTX_DISABLED; | |
478 | route.irq = -1; | |
479 | } | |
480 | return route; | |
481 | } | |
482 | ||
ab431c28 IY |
483 | /* irq routing is changed. so rebuild bitmap */ |
484 | static void piix3_update_irq_levels(PIIX3State *piix3) | |
485 | { | |
486 | int pirq; | |
487 | ||
488 | piix3->pic_levels = 0; | |
489 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
490 | piix3_set_irq_level(piix3, pirq, | |
afe3ef1d | 491 | pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
ab431c28 IY |
492 | } |
493 | } | |
494 | ||
495 | static void piix3_write_config(PCIDevice *dev, | |
496 | uint32_t address, uint32_t val, int len) | |
497 | { | |
498 | pci_default_write_config(dev, address, val, len); | |
499 | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { | |
b7c69719 | 500 | PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); |
ab431c28 | 501 | int pic_irq; |
0ae16251 JK |
502 | |
503 | pci_bus_fire_intx_routing_notifier(piix3->dev.bus); | |
ab431c28 IY |
504 | piix3_update_irq_levels(piix3); |
505 | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { | |
506 | piix3_set_irq_pic(piix3, pic_irq); | |
d2b59317 | 507 | } |
502a5395 PB |
508 | } |
509 | } | |
510 | ||
bf09551a SS |
511 | static void piix3_write_config_xen(PCIDevice *dev, |
512 | uint32_t address, uint32_t val, int len) | |
513 | { | |
514 | xen_piix_pci_write_config_client(address, val, len); | |
515 | piix3_write_config(dev, address, val, len); | |
516 | } | |
517 | ||
15a1956a | 518 | static void piix3_reset(void *opaque) |
502a5395 | 519 | { |
fd37d881 JQ |
520 | PIIX3State *d = opaque; |
521 | uint8_t *pci_conf = d->dev.config; | |
502a5395 | 522 | |
c9721215 | 523 | pci_conf[0x04] = 0x07; /* master, memory and I/O */ |
502a5395 PB |
524 | pci_conf[0x05] = 0x00; |
525 | pci_conf[0x06] = 0x00; | |
c9721215 | 526 | pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ |
502a5395 PB |
527 | pci_conf[0x4c] = 0x4d; |
528 | pci_conf[0x4e] = 0x03; | |
529 | pci_conf[0x4f] = 0x00; | |
530 | pci_conf[0x60] = 0x80; | |
477afee3 AJ |
531 | pci_conf[0x61] = 0x80; |
532 | pci_conf[0x62] = 0x80; | |
533 | pci_conf[0x63] = 0x80; | |
502a5395 PB |
534 | pci_conf[0x69] = 0x02; |
535 | pci_conf[0x70] = 0x80; | |
536 | pci_conf[0x76] = 0x0c; | |
537 | pci_conf[0x77] = 0x0c; | |
538 | pci_conf[0x78] = 0x02; | |
539 | pci_conf[0x79] = 0x00; | |
540 | pci_conf[0x80] = 0x00; | |
541 | pci_conf[0x82] = 0x00; | |
542 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
543 | pci_conf[0xa2] = 0x00; |
544 | pci_conf[0xa3] = 0x00; | |
545 | pci_conf[0xa4] = 0x00; | |
546 | pci_conf[0xa5] = 0x00; | |
547 | pci_conf[0xa6] = 0x00; | |
548 | pci_conf[0xa7] = 0x00; | |
549 | pci_conf[0xa8] = 0x0f; | |
550 | pci_conf[0xaa] = 0x00; | |
551 | pci_conf[0xab] = 0x00; | |
552 | pci_conf[0xac] = 0x00; | |
553 | pci_conf[0xae] = 0x00; | |
ab431c28 IY |
554 | |
555 | d->pic_levels = 0; | |
1ec4ba74 | 556 | d->rcr = 0; |
ab431c28 IY |
557 | } |
558 | ||
559 | static int piix3_post_load(void *opaque, int version_id) | |
560 | { | |
561 | PIIX3State *piix3 = opaque; | |
2c9ecdeb PD |
562 | int pirq; |
563 | ||
564 | /* Because the i8259 has not been deserialized yet, qemu_irq_raise | |
565 | * might bring the system to a different state than the saved one; | |
566 | * for example, the interrupt could be masked but the i8259 would | |
567 | * not know that yet and would trigger an interrupt in the CPU. | |
568 | * | |
569 | * Here, we update irq levels without raising the interrupt. | |
570 | * Interrupt state will be deserialized separately through the i8259. | |
571 | */ | |
572 | piix3->pic_levels = 0; | |
573 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
574 | piix3_set_irq_level_internal(piix3, pirq, | |
575 | pci_bus_get_irq_level(piix3->dev.bus, pirq)); | |
576 | } | |
ab431c28 | 577 | return 0; |
e735b55a | 578 | } |
15a1956a | 579 | |
e735b55a IY |
580 | static void piix3_pre_save(void *opaque) |
581 | { | |
582 | int i; | |
583 | PIIX3State *piix3 = opaque; | |
584 | ||
585 | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { | |
586 | piix3->pci_irq_levels_vmstate[i] = | |
587 | pci_bus_get_irq_level(piix3->dev.bus, i); | |
588 | } | |
502a5395 PB |
589 | } |
590 | ||
1ec4ba74 LE |
591 | static bool piix3_rcr_needed(void *opaque) |
592 | { | |
593 | PIIX3State *piix3 = opaque; | |
594 | ||
595 | return (piix3->rcr != 0); | |
596 | } | |
597 | ||
598 | static const VMStateDescription vmstate_piix3_rcr = { | |
599 | .name = "PIIX3/rcr", | |
600 | .version_id = 1, | |
601 | .minimum_version_id = 1, | |
5cd8cada | 602 | .needed = piix3_rcr_needed, |
d49805ae | 603 | .fields = (VMStateField[]) { |
1ec4ba74 LE |
604 | VMSTATE_UINT8(rcr, PIIX3State), |
605 | VMSTATE_END_OF_LIST() | |
606 | } | |
607 | }; | |
608 | ||
d1f171bd JQ |
609 | static const VMStateDescription vmstate_piix3 = { |
610 | .name = "PIIX3", | |
611 | .version_id = 3, | |
612 | .minimum_version_id = 2, | |
ab431c28 | 613 | .post_load = piix3_post_load, |
e735b55a | 614 | .pre_save = piix3_pre_save, |
d49805ae | 615 | .fields = (VMStateField[]) { |
d1f171bd | 616 | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
e735b55a IY |
617 | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
618 | PIIX_NUM_PIRQS, 3), | |
d1f171bd | 619 | VMSTATE_END_OF_LIST() |
1ec4ba74 | 620 | }, |
5cd8cada JQ |
621 | .subsections = (const VMStateDescription*[]) { |
622 | &vmstate_piix3_rcr, | |
623 | NULL | |
1ec4ba74 LE |
624 | } |
625 | }; | |
626 | ||
627 | ||
628 | static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) | |
629 | { | |
630 | PIIX3State *d = opaque; | |
631 | ||
632 | if (val & 4) { | |
633 | qemu_system_reset_request(); | |
634 | return; | |
da64182c | 635 | } |
1ec4ba74 LE |
636 | d->rcr = val & 2; /* keep System Reset type only */ |
637 | } | |
638 | ||
639 | static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) | |
640 | { | |
641 | PIIX3State *d = opaque; | |
642 | ||
643 | return d->rcr; | |
644 | } | |
645 | ||
646 | static const MemoryRegionOps rcr_ops = { | |
647 | .read = rcr_read, | |
648 | .write = rcr_write, | |
649 | .endianness = DEVICE_LITTLE_ENDIAN | |
d1f171bd | 650 | }; |
1941d19c | 651 | |
9af21dbe | 652 | static void piix3_realize(PCIDevice *dev, Error **errp) |
502a5395 | 653 | { |
b7c69719 | 654 | PIIX3State *d = PIIX3_PCI_DEVICE(dev); |
502a5395 | 655 | |
d10e5432 MA |
656 | if (!isa_bus_new(DEVICE(d), get_system_memory(), |
657 | pci_address_space_io(dev), errp)) { | |
658 | return; | |
659 | } | |
1ec4ba74 | 660 | |
40c5dce9 PB |
661 | memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, |
662 | "piix3-reset-control", 1); | |
1ec4ba74 LE |
663 | memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, |
664 | &d->rcr_mem, 1); | |
665 | ||
a08d4367 | 666 | qemu_register_reset(piix3_reset, d); |
502a5395 | 667 | } |
5c2b87e3 | 668 | |
b7c69719 | 669 | static void pci_piix3_class_init(ObjectClass *klass, void *data) |
40021f08 | 670 | { |
39bffca2 | 671 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
672 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
673 | ||
39bffca2 AL |
674 | dc->desc = "ISA bridge"; |
675 | dc->vmsd = &vmstate_piix3; | |
2897ae02 | 676 | dc->hotpluggable = false; |
9af21dbe | 677 | k->realize = piix3_realize; |
40021f08 | 678 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
c9721215 DW |
679 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
680 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 | 681 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
81aab2ff MA |
682 | /* |
683 | * Reason: part of PIIX3 southbridge, needs to be wired up by | |
684 | * pc_piix.c's pc_init1() | |
685 | */ | |
686 | dc->cannot_instantiate_with_device_add_yet = true; | |
40021f08 AL |
687 | } |
688 | ||
b7c69719 GA |
689 | static const TypeInfo piix3_pci_type_info = { |
690 | .name = TYPE_PIIX3_PCI_DEVICE, | |
691 | .parent = TYPE_PCI_DEVICE, | |
692 | .instance_size = sizeof(PIIX3State), | |
693 | .abstract = true, | |
694 | .class_init = pci_piix3_class_init, | |
695 | }; | |
696 | ||
697 | static void piix3_class_init(ObjectClass *klass, void *data) | |
698 | { | |
699 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
700 | ||
701 | k->config_write = piix3_write_config; | |
702 | } | |
703 | ||
4240abff | 704 | static const TypeInfo piix3_info = { |
39bffca2 | 705 | .name = "PIIX3", |
b7c69719 | 706 | .parent = TYPE_PIIX3_PCI_DEVICE, |
39bffca2 | 707 | .class_init = piix3_class_init, |
e855761c AL |
708 | }; |
709 | ||
40021f08 AL |
710 | static void piix3_xen_class_init(ObjectClass *klass, void *data) |
711 | { | |
712 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
713 | ||
40021f08 | 714 | k->config_write = piix3_write_config_xen; |
e855761c AL |
715 | }; |
716 | ||
4240abff | 717 | static const TypeInfo piix3_xen_info = { |
39bffca2 | 718 | .name = "PIIX3-xen", |
b7c69719 | 719 | .parent = TYPE_PIIX3_PCI_DEVICE, |
39bffca2 | 720 | .class_init = piix3_xen_class_init, |
40021f08 AL |
721 | }; |
722 | ||
723 | static void i440fx_class_init(ObjectClass *klass, void *data) | |
724 | { | |
39bffca2 | 725 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
726 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
727 | ||
9af21dbe | 728 | k->realize = i440fx_realize; |
40021f08 AL |
729 | k->config_write = i440fx_write_config; |
730 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
731 | k->device_id = PCI_DEVICE_ID_INTEL_82441; | |
732 | k->revision = 0x02; | |
733 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 | 734 | dc->desc = "Host bridge"; |
39bffca2 | 735 | dc->vmsd = &vmstate_i440fx; |
08c58f92 MA |
736 | /* |
737 | * PCI-facing part of the host bridge, not usable without the | |
738 | * host-facing part, which can't be device_add'ed, yet. | |
739 | */ | |
740 | dc->cannot_instantiate_with_device_add_yet = true; | |
2897ae02 | 741 | dc->hotpluggable = false; |
40021f08 AL |
742 | } |
743 | ||
4240abff | 744 | static const TypeInfo i440fx_info = { |
57a0f0c6 | 745 | .name = TYPE_I440FX_PCI_DEVICE, |
39bffca2 AL |
746 | .parent = TYPE_PCI_DEVICE, |
747 | .instance_size = sizeof(PCII440FXState), | |
748 | .class_init = i440fx_class_init, | |
8a14daa5 GH |
749 | }; |
750 | ||
595a4f07 TC |
751 | /* IGD Passthrough Host Bridge. */ |
752 | typedef struct { | |
753 | uint8_t offset; | |
754 | uint8_t len; | |
755 | } IGDHostInfo; | |
756 | ||
757 | /* Here we just expose minimal host bridge offset subset. */ | |
758 | static const IGDHostInfo igd_host_bridge_infos[] = { | |
759 | {0x08, 2}, /* revision id */ | |
760 | {0x2c, 2}, /* sybsystem vendor id */ | |
761 | {0x2e, 2}, /* sybsystem id */ | |
762 | {0x50, 2}, /* SNB: processor graphics control register */ | |
763 | {0x52, 2}, /* processor graphics control register */ | |
764 | {0xa4, 4}, /* SNB: graphics base of stolen memory */ | |
765 | {0xa8, 4}, /* SNB: base of GTT stolen memory */ | |
766 | }; | |
767 | ||
349a3b1c | 768 | static int host_pci_config_read(int pos, int len, uint32_t *val) |
595a4f07 TC |
769 | { |
770 | char path[PATH_MAX]; | |
771 | int config_fd; | |
772 | ssize_t size = sizeof(path); | |
773 | /* Access real host bridge. */ | |
774 | int rc = snprintf(path, size, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s", | |
775 | 0, 0, 0, 0, "config"); | |
e3fce97c | 776 | int ret = 0; |
595a4f07 TC |
777 | |
778 | if (rc >= size || rc < 0) { | |
779 | return -ENODEV; | |
780 | } | |
781 | ||
782 | config_fd = open(path, O_RDWR); | |
783 | if (config_fd < 0) { | |
784 | return -ENODEV; | |
785 | } | |
786 | ||
787 | if (lseek(config_fd, pos, SEEK_SET) != pos) { | |
e3fce97c HZ |
788 | ret = -errno; |
789 | goto out; | |
595a4f07 | 790 | } |
349a3b1c | 791 | |
595a4f07 | 792 | do { |
349a3b1c | 793 | rc = read(config_fd, (uint8_t *)val, len); |
595a4f07 TC |
794 | } while (rc < 0 && (errno == EINTR || errno == EAGAIN)); |
795 | if (rc != len) { | |
e3fce97c | 796 | ret = -errno; |
595a4f07 | 797 | } |
349a3b1c | 798 | |
e3fce97c HZ |
799 | out: |
800 | close(config_fd); | |
801 | return ret; | |
595a4f07 TC |
802 | } |
803 | ||
804 | static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev) | |
805 | { | |
806 | uint32_t val = 0; | |
807 | int rc, i, num; | |
808 | int pos, len; | |
809 | ||
810 | num = ARRAY_SIZE(igd_host_bridge_infos); | |
811 | for (i = 0; i < num; i++) { | |
812 | pos = igd_host_bridge_infos[i].offset; | |
813 | len = igd_host_bridge_infos[i].len; | |
349a3b1c | 814 | rc = host_pci_config_read(pos, len, &val); |
595a4f07 TC |
815 | if (rc) { |
816 | return -ENODEV; | |
817 | } | |
818 | pci_default_write_config(pci_dev, pos, val, len); | |
819 | } | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
824 | static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data) | |
825 | { | |
826 | DeviceClass *dc = DEVICE_CLASS(klass); | |
827 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
828 | ||
829 | k->init = igd_pt_i440fx_initfn; | |
830 | dc->desc = "IGD Passthrough Host bridge"; | |
831 | } | |
832 | ||
833 | static const TypeInfo igd_passthrough_i440fx_info = { | |
834 | .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE, | |
835 | .parent = TYPE_I440FX_PCI_DEVICE, | |
836 | .instance_size = sizeof(PCII440FXState), | |
837 | .class_init = igd_passthrough_i440fx_class_init, | |
838 | }; | |
839 | ||
568f0690 DG |
840 | static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, |
841 | PCIBus *rootbus) | |
842 | { | |
04c7d8b8 CR |
843 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge); |
844 | ||
568f0690 | 845 | /* For backwards compat with old device paths */ |
04c7d8b8 CR |
846 | if (s->short_root_bus) { |
847 | return "0000"; | |
848 | } | |
849 | return "0000:00"; | |
568f0690 DG |
850 | } |
851 | ||
39848901 IM |
852 | static Property i440fx_props[] = { |
853 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, | |
854 | pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), | |
04c7d8b8 | 855 | DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0), |
39848901 IM |
856 | DEFINE_PROP_END_OF_LIST(), |
857 | }; | |
858 | ||
999e12bb AL |
859 | static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
860 | { | |
39bffca2 | 861 | DeviceClass *dc = DEVICE_CLASS(klass); |
568f0690 | 862 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
999e12bb | 863 | |
568f0690 | 864 | hc->root_bus_path = i440fx_pcihost_root_bus_path; |
a3560fbf | 865 | dc->realize = i440fx_pcihost_realize; |
39bffca2 | 866 | dc->fw_name = "pci"; |
39848901 | 867 | dc->props = i440fx_props; |
999e12bb AL |
868 | } |
869 | ||
4240abff | 870 | static const TypeInfo i440fx_pcihost_info = { |
1d0d4aa4 | 871 | .name = TYPE_I440FX_PCI_HOST_BRIDGE, |
8558d942 | 872 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 873 | .instance_size = sizeof(I440FXState), |
a3560fbf | 874 | .instance_init = i440fx_pcihost_initfn, |
39bffca2 | 875 | .class_init = i440fx_pcihost_class_init, |
8a14daa5 GH |
876 | }; |
877 | ||
83f7d43a | 878 | static void i440fx_register_types(void) |
8a14daa5 | 879 | { |
39bffca2 | 880 | type_register_static(&i440fx_info); |
595a4f07 | 881 | type_register_static(&igd_passthrough_i440fx_info); |
b7c69719 | 882 | type_register_static(&piix3_pci_type_info); |
39bffca2 AL |
883 | type_register_static(&piix3_info); |
884 | type_register_static(&piix3_xen_info); | |
885 | type_register_static(&i440fx_pcihost_info); | |
8a14daa5 | 886 | } |
83f7d43a AF |
887 | |
888 | type_init(i440fx_register_types) |