[thirdparty/qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "isa.h"
#include "sysbus.h"

typedef uint32_t pci_addr_t;
#include "pci_host.h"

typedef PCIHostState I440FXState;

static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
{
    I440FXState *s = opaque;
    s->config_reg = val;
}

static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
{
    I440FXState *s = opaque;
    return s->config_reg;
}

static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (irq_num + slot_addend) & 3;
}

static target_phys_addr_t isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];

static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
{
    uint32_t addr;

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        cpu_register_physical_memory(start, end - start,
                                     start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        cpu_register_physical_memory(start, end - start,
                                     start | IO_MEM_ROM);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        for(addr = start; addr < end; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         isa_page_descs[(addr - 0xa0000) >> 12]);
        }
        break;
    }
}

static void i440fx_update_memory_mappings(PCIDevice *d)
{
    int i, r;
    uint32_t smram, addr;

    update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
    for(i = 0; i < 12; i++) {
        r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
    }
    smram = d->config[0x72];
    if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
    } else {
        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         isa_page_descs[(addr - 0xa0000) >> 12]);
        }
    }
}

void i440fx_set_smm(PCIDevice *d, int val)
{
    val = (val != 0);
    if (smm_enabled != val) {
        smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


/* XXX: suppress when better memory API. We make the assumption that
   no device (in particular the VGA) changes the memory mappings in
   the 0xa0000-0x100000 range */
void i440fx_init_memory_mappings(PCIDevice *d)
{
    int i;
    for(i = 0; i < 96; i++) {
        isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
    }
}

static void i440fx_write_config(PCIDevice *d,
                                uint32_t address, uint32_t val, int len)
{
    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(d, address, val, len);
    if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
        i440fx_update_memory_mappings(d);
}

static void i440fx_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;
    int i;

    pci_device_save(d, f);
    qemu_put_8s(f, &smm_enabled);

    for (i = 0; i < 4; i++)
        qemu_put_be32(f, pci_irq_levels[i]);
}

static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;
    int ret, i;

    if (version_id > 2)
        return -EINVAL;
    ret = pci_device_load(d, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &smm_enabled);

    if (version_id >= 2)
        for (i = 0; i < 4; i++)
            pci_irq_levels[i] = qemu_get_be32(f);

    return 0;
}

static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
    I440FXState *s = FROM_SYSBUS(I440FXState, dev);

    register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
    register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);

    register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
    register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
    register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
    register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
    return 0;
}

static int i440fx_initfn(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
    d->config[0x08] = 0x02; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

    d->config[0x72] = 0x02; /* SMRAM */

    register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
    return 0;
}

PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
{
    DeviceState *dev;
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;

    dev = qdev_create(NULL, "i440FX-pcihost");
    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
    b = pci_register_bus(&s->busdev.qdev, "pci.0",
                         piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
    s->bus = b;
    qdev_init(dev);

    d = pci_create_simple(b, 0, "i440FX");
    *pi440fx_state = d;

    return b;
}

/* PIIX3 PCI to ISA bridge */

static PCIDevice *piix3_dev;

static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
{
    int i, pic_irq, pic_level;

    pci_irq_levels[irq_num] = level;

    /* now we change the pic irq level according to the piix irq mappings */
    /* XXX: optimize */
    pic_irq = piix3_dev->config[0x60 + irq_num];
    if (pic_irq < 16) {
        /* The pic level is the logical OR of all the PCI irqs mapped
           to it */
        pic_level = 0;
        for (i = 0; i < 4; i++) {
            if (pic_irq == piix3_dev->config[0x60 + i])
                pic_level |= pci_irq_levels[i];
        }
        qemu_set_irq(pic[pic_irq], pic_level);
    }
}

static void piix3_reset(void *opaque)
{
    PCIDevice *d = opaque;
    uint8_t *pci_conf = d->config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
}

static void piix_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;
    pci_device_save(d, f);
}

static int piix_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;
    if (version_id != 2)
        return -EINVAL;
    return pci_device_load(d, f);
}

static int piix3_initfn(PCIDevice *d)
{
    uint8_t *pci_conf;

    isa_bus_new(&d->qdev);
    register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);

    pci_conf = d->config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
    pci_conf[PCI_HEADER_TYPE] =
        PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic

    piix3_dev = d;
    piix3_reset(d);
    qemu_register_reset(piix3_reset, d);
    return 0;
}

int piix3_init(PCIBus *bus, int devfn)
{
    PCIDevice *d;

    d = pci_create_simple(bus, devfn, "PIIX3");
    return d->devfn;
}

static PCIDeviceInfo i440fx_info[] = {
    {
        .qdev.name    = "i440FX",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCIDevice),
        .qdev.no_user = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config,
    },{
        .qdev.name    = "PIIX3",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PCIDevice),
        .qdev.no_user = 1,
        .init         = piix3_initfn,
    },{
        /* end of list */
    }
};

static SysBusDeviceInfo i440fx_pcihost_info = {
    .init         = i440fx_pcihost_initfn,
    .qdev.name    = "i440FX-pcihost",
    .qdev.size    = sizeof(I440FXState),
    .qdev.no_user = 1,
};

static void i440fx_register(void)
{
    sysbus_register_withprop(&i440fx_pcihost_info);
    pci_qdev_register_many(i440fx_info);
}
device_init(i440fx_register);
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
f75247f1	28	#include "isa.h"
8a14daa5	29	#include "sysbus.h"
87ecb68b	30
502a5395 PB	31	typedef uint32_t pci_addr_t;
	32	#include "pci_host.h"
	33
	34	typedef PCIHostState I440FXState;
	35
	36	static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
	37	{
	38	I440FXState *s = opaque;
	39	s->config_reg = val;
	40	}
	41
	42	static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
	43	{
	44	I440FXState *s = opaque;
	45	return s->config_reg;
	46	}
	47
d537cf6c	48	static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
d2b59317 PB	49
	50	/* return the global irq number corresponding to a given device irq
	51	pin. We could also use the bus number to have a more precise
	52	mapping. */
	53	static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
	54	{
	55	int slot_addend;
	56	slot_addend = (pci_dev->devfn >> 3) - 1;
	57	return (irq_num + slot_addend) & 3;
	58	}
502a5395	59
00f82b8a	60	static target_phys_addr_t isa_page_descs[384 / 4];
ee0ea1d0	61	static uint8_t smm_enabled;
52fc1d83	62	static int pci_irq_levels[4];
ee0ea1d0	63
84631fd7 FB	64	static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
	65	{
	66	uint32_t addr;
	67
	68	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	69	switch(r) {
	70	case 3:
	71	/* RAM */
5fafdf24	72	cpu_register_physical_memory(start, end - start,
84631fd7 FB	73	start);
	74	break;
	75	case 1:
	76	/* ROM (XXX: not quite correct) */
5fafdf24	77	cpu_register_physical_memory(start, end - start,
84631fd7 FB	78	start \| IO_MEM_ROM);
	79	break;
	80	case 2:
	81	case 0:
	82	/* XXX: should distinguish read/write cases */
	83	for(addr = start; addr < end; addr += 4096) {
5fafdf24	84	cpu_register_physical_memory(addr, 4096,
84631fd7 FB	85	isa_page_descs[(addr - 0xa0000) >> 12]);
	86	}
	87	break;
	88	}
	89	}
ee0ea1d0 FB	90
	91	static void i440fx_update_memory_mappings(PCIDevice *d)
	92	{
	93	int i, r;
84631fd7 FB	94	uint32_t smram, addr;
	95
	96	update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
	97	for(i = 0; i < 12; i++) {
	98	r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
	99	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0	100	}
84631fd7 FB	101	smram = d->config[0x72];
	102	if ((smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
	103	cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
	104	} else {
	105	for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24	106	cpu_register_physical_memory(addr, 4096,
84631fd7	107	isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0 FB	108	}
	109	}
	110	}
	111
	112	void i440fx_set_smm(PCIDevice *d, int val)
	113	{
	114	val = (val != 0);
	115	if (smm_enabled != val) {
	116	smm_enabled = val;
	117	i440fx_update_memory_mappings(d);
	118	}
	119	}
	120
	121
	122	/* XXX: suppress when better memory API. We make the assumption that
	123	no device (in particular the VGA) changes the memory mappings in
	124	the 0xa0000-0x100000 range */
	125	void i440fx_init_memory_mappings(PCIDevice *d)
	126	{
	127	int i;
	128	for(i = 0; i < 96; i++) {
	129	isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
	130	}
	131	}
	132
5fafdf24	133	static void i440fx_write_config(PCIDevice *d,
ee0ea1d0 FB	134	uint32_t address, uint32_t val, int len)
	135	{
	136	/* XXX: implement SMRAM.D_LOCK */
	137	pci_default_write_config(d, address, val, len);
84631fd7	138	if ((address >= 0x59 && address <= 0x5f) \|\| address == 0x72)
ee0ea1d0 FB	139	i440fx_update_memory_mappings(d);
	140	}
	141
	142	static void i440fx_save(QEMUFile* f, void *opaque)
	143	{
	144	PCIDevice *d = opaque;
52fc1d83 AZ	145	int i;
52fc1d83 AZ	146
ee0ea1d0 FB	147	pci_device_save(d, f);
ee0ea1d0 FB	148	qemu_put_8s(f, &smm_enabled);
52fc1d83 AZ	149
	150	for (i = 0; i < 4; i++)
	151	qemu_put_be32(f, pci_irq_levels[i]);
ee0ea1d0 FB	152	}
	153
	154	static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
	155	{
	156	PCIDevice *d = opaque;
52fc1d83	157	int ret, i;
ee0ea1d0	158
52fc1d83	159	if (version_id > 2)
ee0ea1d0 FB	160	return -EINVAL;
	161	ret = pci_device_load(d, f);
	162	if (ret < 0)
	163	return ret;
	164	i440fx_update_memory_mappings(d);
	165	qemu_get_8s(f, &smm_enabled);
52fc1d83 AZ	166
	167	if (version_id >= 2)
	168	for (i = 0; i < 4; i++)
	169	pci_irq_levels[i] = qemu_get_be32(f);
	170
ee0ea1d0 FB	171	return 0;
	172	}
	173
81a322d4	174	static int i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395	175	{
8a14daa5	176	I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395 PB	177
	178	register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
	179	register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
	180
	181	register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
	182	register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
	183	register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
	184	register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
	185	register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
	186	register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
81a322d4	187	return 0;
8a14daa5	188	}
502a5395	189
81a322d4	190	static int i440fx_initfn(PCIDevice *d)
8a14daa5	191	{
deb54399 AL	192	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
deb54399 AL	193	pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
502a5395	194	d->config[0x08] = 0x02; // revision
173a543b	195	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
6407f373	196	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
ee0ea1d0	197
84631fd7	198	d->config[0x72] = 0x02; /* SMRAM */
ee0ea1d0	199
52fc1d83	200	register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
81a322d4	201	return 0;
8a14daa5 GH	202	}
	203
	204	PCIBus i440fx_init(PCIDevice pi440fx_state, qemu_irq pic)
	205	{
	206	DeviceState *dev;
	207	PCIBus *b;
	208	PCIDevice *d;
	209	I440FXState *s;
	210
	211	dev = qdev_create(NULL, "i440FX-pcihost");
	212	s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
	213	b = pci_register_bus(&s->busdev.qdev, "pci.0",
	214	piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
	215	s->bus = b;
	216	qdev_init(dev);
	217
	218	d = pci_create_simple(b, 0, "i440FX");
ee0ea1d0	219	*pi440fx_state = d;
8a14daa5	220
502a5395 PB	221	return b;
	222	}
	223
	224	/* PIIX3 PCI to ISA bridge */
	225
b1d8e52e	226	static PCIDevice *piix3_dev;
502a5395	227
d537cf6c	228	static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
502a5395	229	{
d2b59317	230	int i, pic_irq, pic_level;
502a5395	231
d2b59317	232	pci_irq_levels[irq_num] = level;
502a5395 PB	233
	234	/* now we change the pic irq level according to the piix irq mappings */
	235	/* XXX: optimize */
	236	pic_irq = piix3_dev->config[0x60 + irq_num];
	237	if (pic_irq < 16) {
d2b59317	238	/* The pic level is the logical OR of all the PCI irqs mapped
502a5395 PB	239	to it */
502a5395 PB	240	pic_level = 0;
d2b59317 PB	241	for (i = 0; i < 4; i++) {
	242	if (pic_irq == piix3_dev->config[0x60 + i])
	243	pic_level \|= pci_irq_levels[i];
	244	}
d537cf6c	245	qemu_set_irq(pic[pic_irq], pic_level);
502a5395 PB	246	}
	247	}
	248
15a1956a	249	static void piix3_reset(void *opaque)
502a5395	250	{
15a1956a	251	PCIDevice *d = opaque;
502a5395 PB	252	uint8_t *pci_conf = d->config;
	253
	254	pci_conf[0x04] = 0x07; // master, memory and I/O
	255	pci_conf[0x05] = 0x00;
	256	pci_conf[0x06] = 0x00;
	257	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	258	pci_conf[0x4c] = 0x4d;
	259	pci_conf[0x4e] = 0x03;
	260	pci_conf[0x4f] = 0x00;
	261	pci_conf[0x60] = 0x80;
477afee3 AJ	262	pci_conf[0x61] = 0x80;
	263	pci_conf[0x62] = 0x80;
	264	pci_conf[0x63] = 0x80;
502a5395 PB	265	pci_conf[0x69] = 0x02;
	266	pci_conf[0x70] = 0x80;
	267	pci_conf[0x76] = 0x0c;
	268	pci_conf[0x77] = 0x0c;
	269	pci_conf[0x78] = 0x02;
	270	pci_conf[0x79] = 0x00;
	271	pci_conf[0x80] = 0x00;
	272	pci_conf[0x82] = 0x00;
	273	pci_conf[0xa0] = 0x08;
502a5395 PB	274	pci_conf[0xa2] = 0x00;
	275	pci_conf[0xa3] = 0x00;
	276	pci_conf[0xa4] = 0x00;
	277	pci_conf[0xa5] = 0x00;
	278	pci_conf[0xa6] = 0x00;
	279	pci_conf[0xa7] = 0x00;
	280	pci_conf[0xa8] = 0x0f;
	281	pci_conf[0xaa] = 0x00;
	282	pci_conf[0xab] = 0x00;
	283	pci_conf[0xac] = 0x00;
	284	pci_conf[0xae] = 0x00;
15a1956a GN	285
15a1956a GN	286	memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
502a5395 PB	287	}
502a5395 PB	288
1941d19c FB	289	static void piix_save(QEMUFile* f, void *opaque)
	290	{
	291	PCIDevice *d = opaque;
	292	pci_device_save(d, f);
	293	}
	294
	295	static int piix_load(QEMUFile* f, void *opaque, int version_id)
	296	{
	297	PCIDevice *d = opaque;
	298	if (version_id != 2)
	299	return -EINVAL;
	300	return pci_device_load(d, f);
	301	}
	302
81a322d4	303	static int piix3_initfn(PCIDevice *d)
502a5395	304	{
502a5395 PB	305	uint8_t *pci_conf;
502a5395 PB	306
f75247f1	307	isa_bus_new(&d->qdev);
1941d19c	308	register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
502a5395	309
502a5395	310	pci_conf = d->config;
deb54399 AL	311	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
deb54399 AL	312	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
173a543b	313	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
6407f373 IY	314	pci_conf[PCI_HEADER_TYPE] =
6407f373 IY	315	PCI_HEADER_TYPE_NORMAL \| PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
502a5395	316
8a14daa5	317	piix3_dev = d;
502a5395	318	piix3_reset(d);
a08d4367	319	qemu_register_reset(piix3_reset, d);
81a322d4	320	return 0;
502a5395	321	}
5c2b87e3	322
8a14daa5 GH	323	int piix3_init(PCIBus *bus, int devfn)
	324	{
	325	PCIDevice *d;
	326
	327	d = pci_create_simple(bus, devfn, "PIIX3");
5c2b87e3 TS	328	return d->devfn;
5c2b87e3 TS	329	}
8a14daa5	330
8a14daa5 GH	331	static PCIDeviceInfo i440fx_info[] = {
	332	{
	333	.qdev.name = "i440FX",
	334	.qdev.desc = "Host bridge",
	335	.qdev.size = sizeof(PCIDevice),
	336	.qdev.no_user = 1,
	337	.init = i440fx_initfn,
	338	.config_write = i440fx_write_config,
	339	},{
	340	.qdev.name = "PIIX3",
	341	.qdev.desc = "ISA bridge",
	342	.qdev.size = sizeof(PCIDevice),
	343	.qdev.no_user = 1,
	344	.init = piix3_initfn,
8a14daa5 GH	345	},{
	346	/* end of list */
	347	}
	348	};
	349
	350	static SysBusDeviceInfo i440fx_pcihost_info = {
	351	.init = i440fx_pcihost_initfn,
	352	.qdev.name = "i440FX-pcihost",
	353	.qdev.size = sizeof(I440FXState),
	354	.qdev.no_user = 1,
	355	};
	356
	357	static void i440fx_register(void)
	358	{
	359	sysbus_register_withprop(&i440fx_pcihost_info);
	360	pci_qdev_register_many(i440fx_info);
	361	}
	362	device_init(i440fx_register);