[thirdparty/qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "pci_host.h"
#include "isa.h"
#include "sysbus.h"
#include "range.h"

/*
 * I440FX chipset data sheet.
 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
 */

typedef PCIHostState I440FXState;

#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
#define PIIX_PIRQC              0x60

typedef struct PIIX3State {
    PCIDevice dev;

    /*
     * bitmap to track pic levels.
     * The pic level is the logical OR of all the PCI irqs mapped to it
     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
     *
     * PIRQ is mapped to PIC pins, we track it by
     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
     * pic_irq * PIIX_NUM_PIRQS + pirq
     */
#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
    uint64_t pic_levels;

    qemu_irq *pic;

    /* This member isn't used. Just for save/load compatibility */
    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;

struct PCII440FXState {
    PCIDevice dev;
    target_phys_addr_t isa_page_descs[384 / 4];
    uint8_t smm_enabled;
    PIIX3State *piix3;
};


#define I440FX_PAM      0x59
#define I440FX_PAM_SIZE 7
#define I440FX_SMRAM    0x72

static void piix3_set_irq(void *opaque, int pirq, int level);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (pci_intx + slot_addend) & 3;
}

static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
{
    uint32_t addr;

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        cpu_register_physical_memory(start, end - start,
                                     start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        cpu_register_physical_memory(start, end - start,
                                     start | IO_MEM_ROM);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        for(addr = start; addr < end; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
        break;
    }
}

static void i440fx_update_memory_mappings(PCII440FXState *d)
{
    int i, r;
    uint32_t smram, addr;

    update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
    for(i = 0; i < 12; i++) {
        r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
    }
    smram = d->dev.config[I440FX_SMRAM];
    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
    } else {
        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
    }
}

static void i440fx_set_smm(int val, void *arg)
{
    PCII440FXState *d = arg;

    val = (val != 0);
    if (d->smm_enabled != val) {
        d->smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


/* XXX: suppress when better memory API. We make the assumption that
   no device (in particular the VGA) changes the memory mappings in
   the 0xa0000-0x100000 range */
void i440fx_init_memory_mappings(PCII440FXState *d)
{
    int i;
    for(i = 0; i < 96; i++) {
        d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
    }
}

static void i440fx_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
        range_covers_byte(address, len, I440FX_SMRAM)) {
        i440fx_update_memory_mappings(d);
    }
}

static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
    PCII440FXState *d = opaque;
    int ret, i;

    ret = pci_device_load(&d->dev, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &d->smm_enabled);

    if (version_id == 2) {
        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
            qemu_get_be32(f); /* dummy load for compatibility */
        }
    }

    return 0;
}

static int i440fx_post_load(void *opaque, int version_id)
{
    PCII440FXState *d = opaque;

    i440fx_update_memory_mappings(d);
    return 0;
}

static const VMStateDescription vmstate_i440fx = {
    .name = "I440FX",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = i440fx_load_old,
    .post_load = i440fx_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCII440FXState),
        VMSTATE_UINT8(smm_enabled, PCII440FXState),
        VMSTATE_END_OF_LIST()
    }
};

static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
    I440FXState *s = FROM_SYSBUS(I440FXState, dev);

    pci_host_conf_register_ioport(0xcf8, s);

    pci_host_data_register_ioport(0xcfc, s);
    return 0;
}

static int i440fx_initfn(PCIDevice *dev)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
    d->dev.config[0x08] = 0x02; // revision
    pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);

    d->dev.config[I440FX_SMRAM] = 0x02;

    cpu_smm_register(&i440fx_set_smm, d);
    return 0;
}

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
{
    DeviceState *dev;
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;
    PIIX3State *piix3;

    dev = qdev_create(NULL, "i440FX-pcihost");
    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
    b = pci_bus_new(&s->busdev.qdev, NULL, 0);
    s->bus = b;
    qdev_init_nofail(dev);

    d = pci_create_simple(b, 0, "i440FX");
    *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);

    piix3 = DO_UPCAST(PIIX3State, dev,
                      pci_create_simple_multifunction(b, -1, true, "PIIX3"));
    piix3->pic = pic;
    pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS);
    (*pi440fx_state)->piix3 = piix3;

    *piix3_devfn = piix3->dev.devfn;

    ram_size = ram_size / 8 / 1024 / 1024;
    if (ram_size > 255)
        ram_size = 255;
    (*pi440fx_state)->dev.config[0x57]=ram_size;

    return b;
}

/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
    qemu_set_irq(piix3->pic[pic_irq],
                 !!(piix3->pic_levels &
                    (((1UL << PIIX_NUM_PIRQS) - 1) <<
                     (pic_irq * PIIX_NUM_PIRQS))));
}

static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level,
                                bool propagate)
{
    int pic_irq;
    uint64_t mask;

    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
        return;
    }

    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
    piix3->pic_levels &= ~mask;
    piix3->pic_levels |= mask * !!level;

    if (propagate) {
        piix3_set_irq_pic(piix3, pic_irq);
    }
}

static void piix3_set_irq(void *opaque, int pirq, int level)
{
    PIIX3State *piix3 = opaque;
    piix3_set_irq_level(piix3, pirq, level, true);
}

/* irq routing is changed. so rebuild bitmap */
static void piix3_update_irq_levels(PIIX3State *piix3)
{
    int pirq;

    piix3->pic_levels = 0;
    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
        piix3_set_irq_level(piix3, pirq,
                            pci_bus_get_irq_level(piix3->dev.bus, pirq),
                            false);
    }
}

static void piix3_write_config(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
        PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
        int pic_irq;
        piix3_update_irq_levels(piix3);
        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
            piix3_set_irq_pic(piix3, pic_irq);
        }
    }
}

static void piix3_reset(void *opaque)
{
    PIIX3State *d = opaque;
    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    d->pic_levels = 0;
}

static int piix3_post_load(void *opaque, int version_id)
{
    PIIX3State *piix3 = opaque;
    piix3_update_irq_levels(piix3);
    return 0;
}

static void piix3_pre_save(void *opaque)
{
    int i;
    PIIX3State *piix3 = opaque;

    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
        piix3->pci_irq_levels_vmstate[i] =
            pci_bus_get_irq_level(piix3->dev.bus, i);
    }
}

static const VMStateDescription vmstate_piix3 = {
    .name = "PIIX3",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .post_load = piix3_post_load,
    .pre_save = piix3_pre_save,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX3State),
        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
                              PIIX_NUM_PIRQS, 3),
        VMSTATE_END_OF_LIST()
    }
};

static int piix3_initfn(PCIDevice *dev)
{
    PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
    uint8_t *pci_conf;

    isa_bus_new(&d->dev.qdev);

    pci_conf = d->dev.config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);

    qemu_register_reset(piix3_reset, d);
    return 0;
}

static PCIDeviceInfo i440fx_info[] = {
    {
        .qdev.name    = "i440FX",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCII440FXState),
        .qdev.vmsd    = &vmstate_i440fx,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config,
    },{
        .qdev.name    = "PIIX3",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PIIX3State),
        .qdev.vmsd    = &vmstate_piix3,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = piix3_initfn,
        .config_write = piix3_write_config,
    },{
        /* end of list */
    }
};

static SysBusDeviceInfo i440fx_pcihost_info = {
    .init         = i440fx_pcihost_initfn,
    .qdev.name    = "i440FX-pcihost",
    .qdev.fw_name = "pci",
    .qdev.size    = sizeof(I440FXState),
    .qdev.no_user = 1,
};

static void i440fx_register(void)
{
    sysbus_register_withprop(&i440fx_pcihost_info);
    pci_qdev_register_many(i440fx_info);
}
device_init(i440fx_register);
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
4f5e19e6	28	#include "pci_host.h"
f75247f1	29	#include "isa.h"
8a14daa5	30	#include "sysbus.h"
bf1b0071	31	#include "range.h"
87ecb68b	32
56594fe3 IY	33	/*
	34	* I440FX chipset data sheet.
	35	* http://download.intel.com/design/chipsets/datashts/29054901.pdf
	36	*/
	37
502a5395 PB	38	typedef PCIHostState I440FXState;
502a5395 PB	39
ab431c28	40	#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
e735b55a	41	#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
ab431c28	42	#define PIIX_PIRQC 0x60
e735b55a	43
fd37d881 JQ	44	typedef struct PIIX3State {
fd37d881 JQ	45	PCIDevice dev;
ab431c28 IY	46
	47	/*
	48	* bitmap to track pic levels.
	49	* The pic level is the logical OR of all the PCI irqs mapped to it
	50	* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
	51	*
	52	* PIRQ is mapped to PIC pins, we track it by
	53	* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
	54	* pic_irq * PIIX_NUM_PIRQS + pirq
	55	*/
	56	#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
	57	#error "unable to encode pic state in 64bit in pic_levels."
	58	#endif
	59	uint64_t pic_levels;
	60
bd7dce87	61	qemu_irq *pic;
e735b55a IY	62
	63	/* This member isn't used. Just for save/load compatibility */
	64	int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
7cd9eee0	65	} PIIX3State;
bd7dce87	66
0a3bacf3 JQ	67	struct PCII440FXState {
0a3bacf3 JQ	68	PCIDevice dev;
c227f099	69	target_phys_addr_t isa_page_descs[384 / 4];
6c009fa4	70	uint8_t smm_enabled;
7cd9eee0	71	PIIX3State *piix3;
0a3bacf3 JQ	72	};
0a3bacf3 JQ	73
f2c688bb IY	74
	75	#define I440FX_PAM 0x59
	76	#define I440FX_PAM_SIZE 7
	77	#define I440FX_SMRAM 0x72
	78
ab431c28	79	static void piix3_set_irq(void *opaque, int pirq, int level);
d2b59317 PB	80
	81	/* return the global irq number corresponding to a given device irq
	82	pin. We could also use the bus number to have a more precise
	83	mapping. */
ab431c28	84	static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
d2b59317 PB	85	{
	86	int slot_addend;
	87	slot_addend = (pci_dev->devfn >> 3) - 1;
ab431c28	88	return (pci_intx + slot_addend) & 3;
d2b59317	89	}
502a5395	90
0a3bacf3	91	static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
84631fd7 FB	92	{
	93	uint32_t addr;
	94
	95	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	96	switch(r) {
	97	case 3:
	98	/* RAM */
5fafdf24	99	cpu_register_physical_memory(start, end - start,
84631fd7 FB	100	start);
	101	break;
	102	case 1:
	103	/* ROM (XXX: not quite correct) */
5fafdf24	104	cpu_register_physical_memory(start, end - start,
84631fd7 FB	105	start \| IO_MEM_ROM);
	106	break;
	107	case 2:
	108	case 0:
	109	/* XXX: should distinguish read/write cases */
	110	for(addr = start; addr < end; addr += 4096) {
5fafdf24	111	cpu_register_physical_memory(addr, 4096,
6c009fa4	112	d->isa_page_descs[(addr - 0xa0000) >> 12]);
84631fd7 FB	113	}
	114	break;
	115	}
	116	}
ee0ea1d0	117
0a3bacf3	118	static void i440fx_update_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	119	{
ee0ea1d0 FB	120	int i, r;
84631fd7 FB	121	uint32_t smram, addr;
84631fd7 FB	122
f2c688bb	123	update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
84631fd7	124	for(i = 0; i < 12; i++) {
f2c688bb	125	r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
84631fd7	126	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0	127	}
f2c688bb	128	smram = d->dev.config[I440FX_SMRAM];
6c009fa4	129	if ((d->smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
84631fd7 FB	130	cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
	131	} else {
	132	for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24	133	cpu_register_physical_memory(addr, 4096,
6c009fa4	134	d->isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0 FB	135	}
	136	}
	137	}
	138
f885f1ea	139	static void i440fx_set_smm(int val, void *arg)
ee0ea1d0	140	{
f885f1ea IY	141	PCII440FXState *d = arg;
f885f1ea IY	142
ee0ea1d0	143	val = (val != 0);
6c009fa4 JQ	144	if (d->smm_enabled != val) {
6c009fa4 JQ	145	d->smm_enabled = val;
ee0ea1d0 FB	146	i440fx_update_memory_mappings(d);
	147	}
	148	}
	149
	150
	151	/* XXX: suppress when better memory API. We make the assumption that
	152	no device (in particular the VGA) changes the memory mappings in
	153	the 0xa0000-0x100000 range */
0a3bacf3	154	void i440fx_init_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	155	{
	156	int i;
	157	for(i = 0; i < 96; i++) {
6c009fa4	158	d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
ee0ea1d0 FB	159	}
	160	}
	161
0a3bacf3	162	static void i440fx_write_config(PCIDevice *dev,
ee0ea1d0 FB	163	uint32_t address, uint32_t val, int len)
ee0ea1d0 FB	164	{
0a3bacf3 JQ	165	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
0a3bacf3 JQ	166
ee0ea1d0	167	/* XXX: implement SMRAM.D_LOCK */
0a3bacf3	168	pci_default_write_config(dev, address, val, len);
4da5fcd3 IY	169	if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) \|\|
4da5fcd3 IY	170	range_covers_byte(address, len, I440FX_SMRAM)) {
ee0ea1d0	171	i440fx_update_memory_mappings(d);
4da5fcd3	172	}
ee0ea1d0 FB	173	}
ee0ea1d0 FB	174
0c7d19e5	175	static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
ee0ea1d0	176	{
0a3bacf3	177	PCII440FXState *d = opaque;
52fc1d83	178	int ret, i;
ee0ea1d0	179
0a3bacf3	180	ret = pci_device_load(&d->dev, f);
ee0ea1d0 FB	181	if (ret < 0)
	182	return ret;
	183	i440fx_update_memory_mappings(d);
6c009fa4	184	qemu_get_8s(f, &d->smm_enabled);
52fc1d83	185
e735b55a IY	186	if (version_id == 2) {
	187	for (i = 0; i < PIIX_NUM_PIRQS; i++) {
	188	qemu_get_be32(f); /* dummy load for compatibility */
	189	}
	190	}
52fc1d83	191
ee0ea1d0 FB	192	return 0;
	193	}
	194
e59fb374	195	static int i440fx_post_load(void *opaque, int version_id)
0c7d19e5 JQ	196	{
	197	PCII440FXState *d = opaque;
	198
	199	i440fx_update_memory_mappings(d);
	200	return 0;
	201	}
	202
	203	static const VMStateDescription vmstate_i440fx = {
	204	.name = "I440FX",
	205	.version_id = 3,
	206	.minimum_version_id = 3,
	207	.minimum_version_id_old = 1,
	208	.load_state_old = i440fx_load_old,
752ff2fa	209	.post_load = i440fx_post_load,
0c7d19e5 JQ	210	.fields = (VMStateField []) {
	211	VMSTATE_PCI_DEVICE(dev, PCII440FXState),
	212	VMSTATE_UINT8(smm_enabled, PCII440FXState),
	213	VMSTATE_END_OF_LIST()
	214	}
	215	};
	216
81a322d4	217	static int i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395	218	{
8a14daa5	219	I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395	220
f08b32fe	221	pci_host_conf_register_ioport(0xcf8, s);
502a5395	222
4f5e19e6	223	pci_host_data_register_ioport(0xcfc, s);
81a322d4	224	return 0;
8a14daa5	225	}
502a5395	226
0a3bacf3	227	static int i440fx_initfn(PCIDevice *dev)
8a14daa5	228	{
0a3bacf3	229	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
ee0ea1d0	230
0a3bacf3 JQ	231	pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
	232	pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
	233	d->dev.config[0x08] = 0x02; // revision
	234	pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
0a3bacf3	235
f2c688bb	236	d->dev.config[I440FX_SMRAM] = 0x02;
ee0ea1d0	237
f885f1ea	238	cpu_smm_register(&i440fx_set_smm, d);
81a322d4	239	return 0;
8a14daa5 GH	240	}
8a14daa5 GH	241
97679527	242	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
8a14daa5 GH	243	{
	244	DeviceState *dev;
	245	PCIBus *b;
	246	PCIDevice *d;
	247	I440FXState *s;
7cd9eee0	248	PIIX3State *piix3;
8a14daa5 GH	249
	250	dev = qdev_create(NULL, "i440FX-pcihost");
	251	s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
7cd9eee0	252	b = pci_bus_new(&s->busdev.qdev, NULL, 0);
8a14daa5	253	s->bus = b;
e23a1b33	254	qdev_init_nofail(dev);
8a14daa5 GH	255
8a14daa5 GH	256	d = pci_create_simple(b, 0, "i440FX");
0a3bacf3	257	*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
8a14daa5	258
7cd9eee0	259	piix3 = DO_UPCAST(PIIX3State, dev,
fecb93c4	260	pci_create_simple_multifunction(b, -1, true, "PIIX3"));
7cd9eee0	261	piix3->pic = pic;
e735b55a	262	pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS);
7cd9eee0 GH	263	(*pi440fx_state)->piix3 = piix3;
	264
	265	*piix3_devfn = piix3->dev.devfn;
85a750ca	266
ec5f92ce BW	267	ram_size = ram_size / 8 / 1024 / 1024;
	268	if (ram_size > 255)
	269	ram_size = 255;
	270	(*pi440fx_state)->dev.config[0x57]=ram_size;
	271
502a5395 PB	272	return b;
	273	}
	274
	275	/* PIIX3 PCI to ISA bridge */
ab431c28 IY	276	static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
	277	{
	278	qemu_set_irq(piix3->pic[pic_irq],
	279	!!(piix3->pic_levels &
	280	(((1UL << PIIX_NUM_PIRQS) - 1) <<
	281	(pic_irq * PIIX_NUM_PIRQS))));
	282	}
502a5395	283
ab431c28 IY	284	static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level,
	285	bool propagate)
	286	{
	287	int pic_irq;
	288	uint64_t mask;
	289
	290	pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
	291	if (pic_irq >= PIIX_NUM_PIC_IRQS) {
	292	return;
	293	}
	294
	295	mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
	296	piix3->pic_levels &= ~mask;
	297	piix3->pic_levels \|= mask * !!level;
	298
	299	if (propagate) {
	300	piix3_set_irq_pic(piix3, pic_irq);
	301	}
	302	}
	303
	304	static void piix3_set_irq(void *opaque, int pirq, int level)
502a5395	305	{
7cd9eee0	306	PIIX3State *piix3 = opaque;
ab431c28 IY	307	piix3_set_irq_level(piix3, pirq, level, true);
ab431c28 IY	308	}
502a5395	309
ab431c28 IY	310	/* irq routing is changed. so rebuild bitmap */
	311	static void piix3_update_irq_levels(PIIX3State *piix3)
	312	{
	313	int pirq;
	314
	315	piix3->pic_levels = 0;
	316	for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
	317	piix3_set_irq_level(piix3, pirq,
	318	pci_bus_get_irq_level(piix3->dev.bus, pirq),
	319	false);
	320	}
	321	}
	322
	323	static void piix3_write_config(PCIDevice *dev,
	324	uint32_t address, uint32_t val, int len)
	325	{
	326	pci_default_write_config(dev, address, val, len);
	327	if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
	328	PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
	329	int pic_irq;
	330	piix3_update_irq_levels(piix3);
	331	for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
	332	piix3_set_irq_pic(piix3, pic_irq);
d2b59317	333	}
502a5395 PB	334	}
	335	}
	336
15a1956a	337	static void piix3_reset(void *opaque)
502a5395	338	{
fd37d881 JQ	339	PIIX3State *d = opaque;
fd37d881 JQ	340	uint8_t *pci_conf = d->dev.config;
502a5395 PB	341
	342	pci_conf[0x04] = 0x07; // master, memory and I/O
	343	pci_conf[0x05] = 0x00;
	344	pci_conf[0x06] = 0x00;
	345	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	346	pci_conf[0x4c] = 0x4d;
	347	pci_conf[0x4e] = 0x03;
	348	pci_conf[0x4f] = 0x00;
	349	pci_conf[0x60] = 0x80;
477afee3 AJ	350	pci_conf[0x61] = 0x80;
	351	pci_conf[0x62] = 0x80;
	352	pci_conf[0x63] = 0x80;
502a5395 PB	353	pci_conf[0x69] = 0x02;
	354	pci_conf[0x70] = 0x80;
	355	pci_conf[0x76] = 0x0c;
	356	pci_conf[0x77] = 0x0c;
	357	pci_conf[0x78] = 0x02;
	358	pci_conf[0x79] = 0x00;
	359	pci_conf[0x80] = 0x00;
	360	pci_conf[0x82] = 0x00;
	361	pci_conf[0xa0] = 0x08;
502a5395 PB	362	pci_conf[0xa2] = 0x00;
	363	pci_conf[0xa3] = 0x00;
	364	pci_conf[0xa4] = 0x00;
	365	pci_conf[0xa5] = 0x00;
	366	pci_conf[0xa6] = 0x00;
	367	pci_conf[0xa7] = 0x00;
	368	pci_conf[0xa8] = 0x0f;
	369	pci_conf[0xaa] = 0x00;
	370	pci_conf[0xab] = 0x00;
	371	pci_conf[0xac] = 0x00;
	372	pci_conf[0xae] = 0x00;
ab431c28 IY	373
	374	d->pic_levels = 0;
	375	}
	376
	377	static int piix3_post_load(void *opaque, int version_id)
	378	{
	379	PIIX3State *piix3 = opaque;
	380	piix3_update_irq_levels(piix3);
	381	return 0;
e735b55a	382	}
15a1956a	383
e735b55a IY	384	static void piix3_pre_save(void *opaque)
	385	{
	386	int i;
	387	PIIX3State *piix3 = opaque;
	388
	389	for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
	390	piix3->pci_irq_levels_vmstate[i] =
	391	pci_bus_get_irq_level(piix3->dev.bus, i);
	392	}
502a5395 PB	393	}
502a5395 PB	394
d1f171bd JQ	395	static const VMStateDescription vmstate_piix3 = {
	396	.name = "PIIX3",
	397	.version_id = 3,
	398	.minimum_version_id = 2,
	399	.minimum_version_id_old = 2,
ab431c28	400	.post_load = piix3_post_load,
e735b55a	401	.pre_save = piix3_pre_save,
d1f171bd JQ	402	.fields = (VMStateField []) {
d1f171bd JQ	403	VMSTATE_PCI_DEVICE(dev, PIIX3State),
e735b55a IY	404	VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
e735b55a IY	405	PIIX_NUM_PIRQS, 3),
d1f171bd	406	VMSTATE_END_OF_LIST()
da64182c	407	}
d1f171bd	408	};
1941d19c	409
fd37d881	410	static int piix3_initfn(PCIDevice *dev)
502a5395	411	{
fd37d881	412	PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
502a5395 PB	413	uint8_t *pci_conf;
502a5395 PB	414
fd37d881	415	isa_bus_new(&d->dev.qdev);
502a5395	416
fd37d881	417	pci_conf = d->dev.config;
deb54399 AL	418	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
deb54399 AL	419	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
173a543b	420	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
502a5395	421
a08d4367	422	qemu_register_reset(piix3_reset, d);
81a322d4	423	return 0;
502a5395	424	}
5c2b87e3	425
8a14daa5 GH	426	static PCIDeviceInfo i440fx_info[] = {
	427	{
	428	.qdev.name = "i440FX",
	429	.qdev.desc = "Host bridge",
0a3bacf3	430	.qdev.size = sizeof(PCII440FXState),
be73cfe2	431	.qdev.vmsd = &vmstate_i440fx,
8a14daa5	432	.qdev.no_user = 1,
0965f12d	433	.no_hotplug = 1,
8a14daa5 GH	434	.init = i440fx_initfn,
	435	.config_write = i440fx_write_config,
	436	},{
	437	.qdev.name = "PIIX3",
	438	.qdev.desc = "ISA bridge",
fd37d881	439	.qdev.size = sizeof(PIIX3State),
be73cfe2	440	.qdev.vmsd = &vmstate_piix3,
8a14daa5	441	.qdev.no_user = 1,
0965f12d	442	.no_hotplug = 1,
8a14daa5	443	.init = piix3_initfn,
ab431c28	444	.config_write = piix3_write_config,
8a14daa5 GH	445	},{
	446	/* end of list */
	447	}
	448	};
	449
	450	static SysBusDeviceInfo i440fx_pcihost_info = {
	451	.init = i440fx_pcihost_initfn,
	452	.qdev.name = "i440FX-pcihost",
779206de	453	.qdev.fw_name = "pci",
8a14daa5 GH	454	.qdev.size = sizeof(I440FXState),
	455	.qdev.no_user = 1,
	456	};
	457
	458	static void i440fx_register(void)
	459	{
	460	sysbus_register_withprop(&i440fx_pcihost_info);
	461	pci_qdev_register_many(i440fx_info);
	462	}
	463	device_init(i440fx_register);