]>
Commit | Line | Data |
---|---|---|
0d75590d | 1 | #include "qemu/osdep.h" |
0c21e073 | 2 | #include "qemu/cutils.h" |
da34e65c | 3 | #include "qapi/error.h" |
b3946626 | 4 | #include "sysemu/hw_accel.h" |
54d31236 | 5 | #include "sysemu/runstate.h" |
03dd024f | 6 | #include "qemu/log.h" |
db725815 | 7 | #include "qemu/main-loop.h" |
0b8fa32f | 8 | #include "qemu/module.h" |
0b0b8310 | 9 | #include "qemu/error-report.h" |
9fdf0c29 | 10 | #include "cpu.h" |
63c91552 | 11 | #include "exec/exec-all.h" |
ed120055 | 12 | #include "helper_regs.h" |
0d09e41a | 13 | #include "hw/ppc/spapr.h" |
7388efaf | 14 | #include "hw/ppc/spapr_cpu_core.h" |
d5aea6f3 | 15 | #include "mmu-hash64.h" |
3794d548 AK |
16 | #include "cpu-models.h" |
17 | #include "trace.h" | |
18 | #include "kvm_ppc.h" | |
0c21e073 | 19 | #include "hw/ppc/fdt.h" |
facdb8b6 | 20 | #include "hw/ppc/spapr_ovec.h" |
b4db5413 | 21 | #include "mmu-book3s-v3.h" |
2cc0e2e8 | 22 | #include "hw/mem/memory-device.h" |
f43e3525 | 23 | |
af08a58f TH |
24 | static bool has_spr(PowerPCCPU *cpu, int spr) |
25 | { | |
26 | /* We can test whether the SPR is defined by checking for a valid name */ | |
27 | return cpu->env.spr_cb[spr].name != NULL; | |
28 | } | |
29 | ||
c6404ade | 30 | static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) |
f3c75d42 AK |
31 | { |
32 | /* | |
36778660 | 33 | * hash value/pteg group index is normalized by HPT mask |
f3c75d42 | 34 | */ |
36778660 | 35 | if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { |
f3c75d42 AK |
36 | return false; |
37 | } | |
38 | return true; | |
39 | } | |
40 | ||
ce2918cb | 41 | static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) |
ecbc25fa DG |
42 | { |
43 | MachineState *machine = MACHINE(spapr); | |
e017da37 | 44 | DeviceMemoryState *dms = machine->device_memory; |
ecbc25fa DG |
45 | |
46 | if (addr < machine->ram_size) { | |
47 | return true; | |
48 | } | |
e017da37 DH |
49 | if ((addr >= dms->base) |
50 | && ((addr - dms->base) < memory_region_size(&dms->mr))) { | |
ecbc25fa DG |
51 | return true; |
52 | } | |
53 | ||
54 | return false; | |
55 | } | |
56 | ||
ce2918cb | 57 | static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, |
f43e3525 DG |
58 | target_ulong opcode, target_ulong *args) |
59 | { | |
60 | target_ulong flags = args[0]; | |
c6404ade | 61 | target_ulong ptex = args[1]; |
f43e3525 DG |
62 | target_ulong pteh = args[2]; |
63 | target_ulong ptel = args[3]; | |
1f0252e6 | 64 | unsigned apshift; |
f73a2575 | 65 | target_ulong raddr; |
c6404ade | 66 | target_ulong slot; |
7222b94a | 67 | const ppc_hash_pte64_t *hptes; |
f43e3525 | 68 | |
1f0252e6 | 69 | apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); |
1114e712 DG |
70 | if (!apshift) { |
71 | /* Bad page size encoding */ | |
72 | return H_PARAMETER; | |
f43e3525 DG |
73 | } |
74 | ||
1114e712 | 75 | raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); |
f43e3525 | 76 | |
ecbc25fa | 77 | if (is_ram_address(spapr, raddr)) { |
f73a2575 | 78 | /* Regular RAM - should have WIMG=0010 */ |
d5aea6f3 | 79 | if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { |
f73a2575 DG |
80 | return H_PARAMETER; |
81 | } | |
82 | } else { | |
c1175907 | 83 | target_ulong wimg_flags; |
f73a2575 DG |
84 | /* Looks like an IO address */ |
85 | /* FIXME: What WIMG combinations could be sensible for IO? | |
86 | * For now we allow WIMG=010x, but are there others? */ | |
87 | /* FIXME: Should we check against registered IO addresses? */ | |
c1175907 AK |
88 | wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); |
89 | ||
90 | if (wimg_flags != HPTE64_R_I && | |
91 | wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { | |
f73a2575 DG |
92 | return H_PARAMETER; |
93 | } | |
f43e3525 | 94 | } |
f73a2575 | 95 | |
f43e3525 DG |
96 | pteh &= ~0x60ULL; |
97 | ||
c6404ade | 98 | if (!valid_ptex(cpu, ptex)) { |
f43e3525 DG |
99 | return H_PARAMETER; |
100 | } | |
7c43bca0 | 101 | |
c6404ade DG |
102 | slot = ptex & 7ULL; |
103 | ptex = ptex & ~7ULL; | |
104 | ||
f43e3525 | 105 | if (likely((flags & H_EXACT) == 0)) { |
7222b94a | 106 | hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); |
c6404ade | 107 | for (slot = 0; slot < 8; slot++) { |
7222b94a | 108 | if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { |
f43e3525 DG |
109 | break; |
110 | } | |
7aaf4957 | 111 | } |
7222b94a | 112 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); |
c6404ade | 113 | if (slot == 8) { |
7aaf4957 AK |
114 | return H_PTEG_FULL; |
115 | } | |
f43e3525 | 116 | } else { |
7222b94a DG |
117 | hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); |
118 | if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { | |
119 | ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); | |
f43e3525 DG |
120 | return H_PTEG_FULL; |
121 | } | |
7222b94a | 122 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); |
f43e3525 | 123 | } |
7c43bca0 | 124 | |
a2dd4e83 | 125 | spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); |
f43e3525 | 126 | |
c6404ade | 127 | args[0] = ptex + slot; |
f43e3525 DG |
128 | return H_SUCCESS; |
129 | } | |
130 | ||
a3801402 | 131 | typedef enum { |
a3d0abae DG |
132 | REMOVE_SUCCESS = 0, |
133 | REMOVE_NOT_FOUND = 1, | |
134 | REMOVE_PARM = 2, | |
135 | REMOVE_HW = 3, | |
a3801402 | 136 | } RemoveResult; |
a3d0abae | 137 | |
a2dd4e83 BH |
138 | static RemoveResult remove_hpte(PowerPCCPU *cpu |
139 | , target_ulong ptex, | |
a3d0abae DG |
140 | target_ulong avpn, |
141 | target_ulong flags, | |
142 | target_ulong *vp, target_ulong *rp) | |
f43e3525 | 143 | { |
7222b94a | 144 | const ppc_hash_pte64_t *hptes; |
61a36c9b | 145 | target_ulong v, r; |
f43e3525 | 146 | |
c6404ade | 147 | if (!valid_ptex(cpu, ptex)) { |
a3d0abae | 148 | return REMOVE_PARM; |
f43e3525 DG |
149 | } |
150 | ||
7222b94a DG |
151 | hptes = ppc_hash64_map_hptes(cpu, ptex, 1); |
152 | v = ppc_hash64_hpte0(cpu, hptes, 0); | |
153 | r = ppc_hash64_hpte1(cpu, hptes, 0); | |
154 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); | |
f43e3525 | 155 | |
d5aea6f3 | 156 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 DG |
157 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || |
158 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { | |
a3d0abae | 159 | return REMOVE_NOT_FOUND; |
f43e3525 | 160 | } |
35f9304d | 161 | *vp = v; |
a3d0abae | 162 | *rp = r; |
a2dd4e83 | 163 | spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); |
61a36c9b | 164 | ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); |
a3d0abae DG |
165 | return REMOVE_SUCCESS; |
166 | } | |
167 | ||
ce2918cb | 168 | static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, |
a3d0abae DG |
169 | target_ulong opcode, target_ulong *args) |
170 | { | |
cd0c6f47 | 171 | CPUPPCState *env = &cpu->env; |
a3d0abae | 172 | target_ulong flags = args[0]; |
c6404ade | 173 | target_ulong ptex = args[1]; |
a3d0abae | 174 | target_ulong avpn = args[2]; |
a3801402 | 175 | RemoveResult ret; |
a3d0abae | 176 | |
c6404ade | 177 | ret = remove_hpte(cpu, ptex, avpn, flags, |
a3d0abae DG |
178 | &args[0], &args[1]); |
179 | ||
180 | switch (ret) { | |
181 | case REMOVE_SUCCESS: | |
e3cffe6f | 182 | check_tlb_flush(env, true); |
a3d0abae DG |
183 | return H_SUCCESS; |
184 | ||
185 | case REMOVE_NOT_FOUND: | |
186 | return H_NOT_FOUND; | |
187 | ||
188 | case REMOVE_PARM: | |
189 | return H_PARAMETER; | |
190 | ||
191 | case REMOVE_HW: | |
192 | return H_HARDWARE; | |
193 | } | |
194 | ||
9a39970d | 195 | g_assert_not_reached(); |
a3d0abae DG |
196 | } |
197 | ||
198 | #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL | |
199 | #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL | |
200 | #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL | |
201 | #define H_BULK_REMOVE_END 0xc000000000000000ULL | |
202 | #define H_BULK_REMOVE_CODE 0x3000000000000000ULL | |
203 | #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL | |
204 | #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL | |
205 | #define H_BULK_REMOVE_PARM 0x2000000000000000ULL | |
206 | #define H_BULK_REMOVE_HW 0x3000000000000000ULL | |
207 | #define H_BULK_REMOVE_RC 0x0c00000000000000ULL | |
208 | #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL | |
209 | #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL | |
210 | #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL | |
211 | #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL | |
212 | #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL | |
213 | ||
214 | #define H_BULK_REMOVE_MAX_BATCH 4 | |
215 | ||
ce2918cb | 216 | static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, |
a3d0abae DG |
217 | target_ulong opcode, target_ulong *args) |
218 | { | |
cd0c6f47 | 219 | CPUPPCState *env = &cpu->env; |
a3d0abae | 220 | int i; |
cd0c6f47 | 221 | target_ulong rc = H_SUCCESS; |
a3d0abae DG |
222 | |
223 | for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { | |
224 | target_ulong *tsh = &args[i*2]; | |
225 | target_ulong tsl = args[i*2 + 1]; | |
226 | target_ulong v, r, ret; | |
227 | ||
228 | if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { | |
229 | break; | |
230 | } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { | |
231 | return H_PARAMETER; | |
232 | } | |
233 | ||
234 | *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; | |
235 | *tsh |= H_BULK_REMOVE_RESPONSE; | |
236 | ||
237 | if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { | |
238 | *tsh |= H_BULK_REMOVE_PARM; | |
239 | return H_PARAMETER; | |
240 | } | |
241 | ||
7ef23068 | 242 | ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, |
a3d0abae DG |
243 | (*tsh & H_BULK_REMOVE_FLAGS) >> 26, |
244 | &v, &r); | |
245 | ||
246 | *tsh |= ret << 60; | |
247 | ||
248 | switch (ret) { | |
249 | case REMOVE_SUCCESS: | |
d5aea6f3 | 250 | *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; |
a3d0abae DG |
251 | break; |
252 | ||
253 | case REMOVE_PARM: | |
cd0c6f47 BH |
254 | rc = H_PARAMETER; |
255 | goto exit; | |
a3d0abae DG |
256 | |
257 | case REMOVE_HW: | |
cd0c6f47 BH |
258 | rc = H_HARDWARE; |
259 | goto exit; | |
a3d0abae DG |
260 | } |
261 | } | |
cd0c6f47 | 262 | exit: |
e3cffe6f | 263 | check_tlb_flush(env, true); |
a3d0abae | 264 | |
cd0c6f47 | 265 | return rc; |
f43e3525 DG |
266 | } |
267 | ||
ce2918cb | 268 | static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, |
f43e3525 DG |
269 | target_ulong opcode, target_ulong *args) |
270 | { | |
b13ce26d | 271 | CPUPPCState *env = &cpu->env; |
f43e3525 | 272 | target_ulong flags = args[0]; |
c6404ade | 273 | target_ulong ptex = args[1]; |
f43e3525 | 274 | target_ulong avpn = args[2]; |
7222b94a | 275 | const ppc_hash_pte64_t *hptes; |
61a36c9b | 276 | target_ulong v, r; |
f43e3525 | 277 | |
c6404ade | 278 | if (!valid_ptex(cpu, ptex)) { |
f43e3525 DG |
279 | return H_PARAMETER; |
280 | } | |
281 | ||
7222b94a DG |
282 | hptes = ppc_hash64_map_hptes(cpu, ptex, 1); |
283 | v = ppc_hash64_hpte0(cpu, hptes, 0); | |
284 | r = ppc_hash64_hpte1(cpu, hptes, 0); | |
285 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); | |
f43e3525 | 286 | |
d5aea6f3 | 287 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 | 288 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { |
f43e3525 DG |
289 | return H_NOT_FOUND; |
290 | } | |
291 | ||
d5aea6f3 DG |
292 | r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | |
293 | HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); | |
294 | r |= (flags << 55) & HPTE64_R_PP0; | |
295 | r |= (flags << 48) & HPTE64_R_KEY_HI; | |
296 | r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); | |
a2dd4e83 BH |
297 | spapr_store_hpte(cpu, ptex, |
298 | (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); | |
c6404ade | 299 | ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); |
d76ab5e1 ND |
300 | /* Flush the tlb */ |
301 | check_tlb_flush(env, true); | |
f43e3525 | 302 | /* Don't need a memory barrier, due to qemu's global lock */ |
a2dd4e83 | 303 | spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); |
f43e3525 DG |
304 | return H_SUCCESS; |
305 | } | |
306 | ||
ce2918cb | 307 | static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, |
6bbd5dde EC |
308 | target_ulong opcode, target_ulong *args) |
309 | { | |
6bbd5dde | 310 | target_ulong flags = args[0]; |
c6404ade | 311 | target_ulong ptex = args[1]; |
6bbd5dde | 312 | int i, ridx, n_entries = 1; |
993aaf0c | 313 | const ppc_hash_pte64_t *hptes; |
6bbd5dde | 314 | |
c6404ade | 315 | if (!valid_ptex(cpu, ptex)) { |
6bbd5dde EC |
316 | return H_PARAMETER; |
317 | } | |
318 | ||
319 | if (flags & H_READ_4) { | |
320 | /* Clear the two low order bits */ | |
c6404ade | 321 | ptex &= ~(3ULL); |
6bbd5dde EC |
322 | n_entries = 4; |
323 | } | |
324 | ||
993aaf0c | 325 | hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries); |
6bbd5dde | 326 | for (i = 0, ridx = 0; i < n_entries; i++) { |
993aaf0c BH |
327 | args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i); |
328 | args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i); | |
6bbd5dde | 329 | } |
993aaf0c | 330 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); |
6bbd5dde EC |
331 | |
332 | return H_SUCCESS; | |
333 | } | |
334 | ||
ce2918cb | 335 | struct SpaprPendingHpt { |
0b0b8310 DG |
336 | /* These fields are read-only after initialization */ |
337 | int shift; | |
338 | QemuThread thread; | |
339 | ||
340 | /* These fields are protected by the BQL */ | |
341 | bool complete; | |
342 | ||
343 | /* These fields are private to the preparation thread if | |
344 | * !complete, otherwise protected by the BQL */ | |
345 | int ret; | |
346 | void *hpt; | |
347 | }; | |
348 | ||
ce2918cb | 349 | static void free_pending_hpt(SpaprPendingHpt *pending) |
0b0b8310 DG |
350 | { |
351 | if (pending->hpt) { | |
352 | qemu_vfree(pending->hpt); | |
353 | } | |
354 | ||
355 | g_free(pending); | |
356 | } | |
357 | ||
358 | static void *hpt_prepare_thread(void *opaque) | |
359 | { | |
ce2918cb | 360 | SpaprPendingHpt *pending = opaque; |
0b0b8310 DG |
361 | size_t size = 1ULL << pending->shift; |
362 | ||
363 | pending->hpt = qemu_memalign(size, size); | |
364 | if (pending->hpt) { | |
365 | memset(pending->hpt, 0, size); | |
366 | pending->ret = H_SUCCESS; | |
367 | } else { | |
368 | pending->ret = H_NO_MEM; | |
369 | } | |
370 | ||
371 | qemu_mutex_lock_iothread(); | |
372 | ||
373 | if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { | |
374 | /* Ready to go */ | |
375 | pending->complete = true; | |
376 | } else { | |
377 | /* We've been cancelled, clean ourselves up */ | |
378 | free_pending_hpt(pending); | |
379 | } | |
380 | ||
381 | qemu_mutex_unlock_iothread(); | |
382 | return NULL; | |
383 | } | |
384 | ||
385 | /* Must be called with BQL held */ | |
ce2918cb | 386 | static void cancel_hpt_prepare(SpaprMachineState *spapr) |
0b0b8310 | 387 | { |
ce2918cb | 388 | SpaprPendingHpt *pending = spapr->pending_hpt; |
0b0b8310 DG |
389 | |
390 | /* Let the thread know it's cancelled */ | |
391 | spapr->pending_hpt = NULL; | |
392 | ||
393 | if (!pending) { | |
394 | /* Nothing to do */ | |
395 | return; | |
396 | } | |
397 | ||
398 | if (!pending->complete) { | |
399 | /* thread will clean itself up */ | |
400 | return; | |
401 | } | |
402 | ||
403 | free_pending_hpt(pending); | |
404 | } | |
405 | ||
b55d295e DG |
406 | /* Convert a return code from the KVM ioctl()s implementing resize HPT |
407 | * into a PAPR hypercall return code */ | |
408 | static target_ulong resize_hpt_convert_rc(int ret) | |
409 | { | |
410 | if (ret >= 100000) { | |
411 | return H_LONG_BUSY_ORDER_100_SEC; | |
412 | } else if (ret >= 10000) { | |
413 | return H_LONG_BUSY_ORDER_10_SEC; | |
414 | } else if (ret >= 1000) { | |
415 | return H_LONG_BUSY_ORDER_1_SEC; | |
416 | } else if (ret >= 100) { | |
417 | return H_LONG_BUSY_ORDER_100_MSEC; | |
418 | } else if (ret >= 10) { | |
419 | return H_LONG_BUSY_ORDER_10_MSEC; | |
420 | } else if (ret > 0) { | |
421 | return H_LONG_BUSY_ORDER_1_MSEC; | |
422 | } | |
423 | ||
424 | switch (ret) { | |
425 | case 0: | |
426 | return H_SUCCESS; | |
427 | case -EPERM: | |
428 | return H_AUTHORITY; | |
429 | case -EINVAL: | |
430 | return H_PARAMETER; | |
431 | case -ENXIO: | |
432 | return H_CLOSED; | |
433 | case -ENOSPC: | |
434 | return H_PTEG_FULL; | |
435 | case -EBUSY: | |
436 | return H_BUSY; | |
437 | case -ENOMEM: | |
438 | return H_NO_MEM; | |
439 | default: | |
440 | return H_HARDWARE; | |
441 | } | |
442 | } | |
443 | ||
30f4b05b | 444 | static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, |
ce2918cb | 445 | SpaprMachineState *spapr, |
30f4b05b DG |
446 | target_ulong opcode, |
447 | target_ulong *args) | |
448 | { | |
449 | target_ulong flags = args[0]; | |
0b0b8310 | 450 | int shift = args[1]; |
ce2918cb | 451 | SpaprPendingHpt *pending = spapr->pending_hpt; |
db50f280 | 452 | uint64_t current_ram_size; |
b55d295e | 453 | int rc; |
30f4b05b DG |
454 | |
455 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { | |
456 | return H_AUTHORITY; | |
457 | } | |
458 | ||
0b0b8310 DG |
459 | if (!spapr->htab_shift) { |
460 | /* Radix guest, no HPT */ | |
461 | return H_NOT_AVAILABLE; | |
462 | } | |
463 | ||
30f4b05b | 464 | trace_spapr_h_resize_hpt_prepare(flags, shift); |
0b0b8310 DG |
465 | |
466 | if (flags != 0) { | |
467 | return H_PARAMETER; | |
468 | } | |
469 | ||
470 | if (shift && ((shift < 18) || (shift > 46))) { | |
471 | return H_PARAMETER; | |
472 | } | |
473 | ||
db50f280 | 474 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); |
0b0b8310 DG |
475 | |
476 | /* We only allow the guest to allocate an HPT one order above what | |
477 | * we'd normally give them (to stop a small guest claiming a huge | |
478 | * chunk of resources in the HPT */ | |
479 | if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { | |
480 | return H_RESOURCE; | |
481 | } | |
482 | ||
b55d295e DG |
483 | rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); |
484 | if (rc != -ENOSYS) { | |
485 | return resize_hpt_convert_rc(rc); | |
486 | } | |
487 | ||
0b0b8310 DG |
488 | if (pending) { |
489 | /* something already in progress */ | |
490 | if (pending->shift == shift) { | |
491 | /* and it's suitable */ | |
492 | if (pending->complete) { | |
493 | return pending->ret; | |
494 | } else { | |
495 | return H_LONG_BUSY_ORDER_100_MSEC; | |
496 | } | |
497 | } | |
498 | ||
499 | /* not suitable, cancel and replace */ | |
500 | cancel_hpt_prepare(spapr); | |
501 | } | |
502 | ||
503 | if (!shift) { | |
504 | /* nothing to do */ | |
505 | return H_SUCCESS; | |
506 | } | |
507 | ||
508 | /* start new prepare */ | |
509 | ||
ce2918cb | 510 | pending = g_new0(SpaprPendingHpt, 1); |
0b0b8310 DG |
511 | pending->shift = shift; |
512 | pending->ret = H_HARDWARE; | |
513 | ||
514 | qemu_thread_create(&pending->thread, "sPAPR HPT prepare", | |
515 | hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); | |
516 | ||
517 | spapr->pending_hpt = pending; | |
518 | ||
519 | /* In theory we could estimate the time more accurately based on | |
520 | * the new size, but there's not much point */ | |
521 | return H_LONG_BUSY_ORDER_100_MSEC; | |
522 | } | |
523 | ||
524 | static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) | |
525 | { | |
526 | uint8_t *addr = htab; | |
527 | ||
528 | addr += pteg * HASH_PTEG_SIZE_64; | |
529 | addr += slot * HASH_PTE_SIZE_64; | |
530 | return ldq_p(addr); | |
531 | } | |
532 | ||
533 | static void new_hpte_store(void *htab, uint64_t pteg, int slot, | |
534 | uint64_t pte0, uint64_t pte1) | |
535 | { | |
536 | uint8_t *addr = htab; | |
537 | ||
538 | addr += pteg * HASH_PTEG_SIZE_64; | |
539 | addr += slot * HASH_PTE_SIZE_64; | |
540 | ||
541 | stq_p(addr, pte0); | |
542 | stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); | |
543 | } | |
544 | ||
545 | static int rehash_hpte(PowerPCCPU *cpu, | |
546 | const ppc_hash_pte64_t *hptes, | |
547 | void *old_hpt, uint64_t oldsize, | |
548 | void *new_hpt, uint64_t newsize, | |
549 | uint64_t pteg, int slot) | |
550 | { | |
551 | uint64_t old_hash_mask = (oldsize >> 7) - 1; | |
552 | uint64_t new_hash_mask = (newsize >> 7) - 1; | |
553 | target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); | |
554 | target_ulong pte1; | |
555 | uint64_t avpn; | |
556 | unsigned base_pg_shift; | |
557 | uint64_t hash, new_pteg, replace_pte0; | |
558 | ||
559 | if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { | |
560 | return H_SUCCESS; | |
561 | } | |
562 | ||
563 | pte1 = ppc_hash64_hpte1(cpu, hptes, slot); | |
564 | ||
565 | base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); | |
566 | assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ | |
567 | avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); | |
568 | ||
569 | if (pte0 & HPTE64_V_SECONDARY) { | |
570 | pteg = ~pteg; | |
571 | } | |
572 | ||
573 | if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { | |
574 | uint64_t offset, vsid; | |
575 | ||
576 | /* We only have 28 - 23 bits of offset in avpn */ | |
577 | offset = (avpn & 0x1f) << 23; | |
578 | vsid = avpn >> 5; | |
579 | /* We can find more bits from the pteg value */ | |
580 | if (base_pg_shift < 23) { | |
581 | offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; | |
582 | } | |
583 | ||
584 | hash = vsid ^ (offset >> base_pg_shift); | |
585 | } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { | |
586 | uint64_t offset, vsid; | |
587 | ||
588 | /* We only have 40 - 23 bits of seg_off in avpn */ | |
589 | offset = (avpn & 0x1ffff) << 23; | |
590 | vsid = avpn >> 17; | |
591 | if (base_pg_shift < 23) { | |
592 | offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) | |
593 | << base_pg_shift; | |
594 | } | |
595 | ||
596 | hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); | |
597 | } else { | |
598 | error_report("rehash_pte: Bad segment size in HPTE"); | |
599 | return H_HARDWARE; | |
600 | } | |
601 | ||
602 | new_pteg = hash & new_hash_mask; | |
603 | if (pte0 & HPTE64_V_SECONDARY) { | |
604 | assert(~pteg == (hash & old_hash_mask)); | |
605 | new_pteg = ~new_pteg; | |
606 | } else { | |
607 | assert(pteg == (hash & old_hash_mask)); | |
608 | } | |
609 | assert((oldsize != newsize) || (pteg == new_pteg)); | |
610 | replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); | |
611 | /* | |
612 | * Strictly speaking, we don't need all these tests, since we only | |
613 | * ever rehash bolted HPTEs. We might in future handle non-bolted | |
614 | * HPTEs, though so make the logic correct for those cases as | |
615 | * well. | |
616 | */ | |
617 | if (replace_pte0 & HPTE64_V_VALID) { | |
618 | assert(newsize < oldsize); | |
619 | if (replace_pte0 & HPTE64_V_BOLTED) { | |
620 | if (pte0 & HPTE64_V_BOLTED) { | |
621 | /* Bolted collision, nothing we can do */ | |
622 | return H_PTEG_FULL; | |
623 | } else { | |
624 | /* Discard this hpte */ | |
625 | return H_SUCCESS; | |
626 | } | |
627 | } | |
628 | } | |
629 | ||
630 | new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); | |
631 | return H_SUCCESS; | |
632 | } | |
633 | ||
634 | static int rehash_hpt(PowerPCCPU *cpu, | |
635 | void *old_hpt, uint64_t oldsize, | |
636 | void *new_hpt, uint64_t newsize) | |
637 | { | |
638 | uint64_t n_ptegs = oldsize >> 7; | |
639 | uint64_t pteg; | |
640 | int slot; | |
641 | int rc; | |
642 | ||
643 | for (pteg = 0; pteg < n_ptegs; pteg++) { | |
644 | hwaddr ptex = pteg * HPTES_PER_GROUP; | |
645 | const ppc_hash_pte64_t *hptes | |
646 | = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); | |
647 | ||
648 | if (!hptes) { | |
649 | return H_HARDWARE; | |
650 | } | |
651 | ||
652 | for (slot = 0; slot < HPTES_PER_GROUP; slot++) { | |
653 | rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, | |
654 | pteg, slot); | |
655 | if (rc != H_SUCCESS) { | |
656 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); | |
657 | return rc; | |
658 | } | |
659 | } | |
660 | ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); | |
661 | } | |
662 | ||
663 | return H_SUCCESS; | |
30f4b05b DG |
664 | } |
665 | ||
1ec26c75 GK |
666 | static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) |
667 | { | |
668 | int ret; | |
669 | ||
670 | cpu_synchronize_state(cs); | |
671 | ||
672 | ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); | |
673 | if (ret < 0) { | |
674 | error_report("failed to push sregs to KVM: %s", strerror(-ret)); | |
675 | exit(1); | |
676 | } | |
677 | } | |
678 | ||
ce2918cb | 679 | static void push_sregs_to_kvm_pr(SpaprMachineState *spapr) |
1ec26c75 GK |
680 | { |
681 | CPUState *cs; | |
682 | ||
683 | /* | |
684 | * This is a hack for the benefit of KVM PR - it abuses the SDR1 | |
685 | * slot in kvm_sregs to communicate the userspace address of the | |
686 | * HPT | |
687 | */ | |
688 | if (!kvm_enabled() || !spapr->htab) { | |
689 | return; | |
690 | } | |
691 | ||
692 | CPU_FOREACH(cs) { | |
693 | run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); | |
694 | } | |
695 | } | |
696 | ||
30f4b05b | 697 | static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, |
ce2918cb | 698 | SpaprMachineState *spapr, |
30f4b05b DG |
699 | target_ulong opcode, |
700 | target_ulong *args) | |
701 | { | |
702 | target_ulong flags = args[0]; | |
703 | target_ulong shift = args[1]; | |
ce2918cb | 704 | SpaprPendingHpt *pending = spapr->pending_hpt; |
0b0b8310 DG |
705 | int rc; |
706 | size_t newsize; | |
30f4b05b DG |
707 | |
708 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { | |
709 | return H_AUTHORITY; | |
710 | } | |
711 | ||
94789567 DHB |
712 | if (!spapr->htab_shift) { |
713 | /* Radix guest, no HPT */ | |
714 | return H_NOT_AVAILABLE; | |
715 | } | |
716 | ||
30f4b05b | 717 | trace_spapr_h_resize_hpt_commit(flags, shift); |
0b0b8310 | 718 | |
b55d295e DG |
719 | rc = kvmppc_resize_hpt_commit(cpu, flags, shift); |
720 | if (rc != -ENOSYS) { | |
94789567 DHB |
721 | rc = resize_hpt_convert_rc(rc); |
722 | if (rc == H_SUCCESS) { | |
723 | /* Need to set the new htab_shift in the machine state */ | |
724 | spapr->htab_shift = shift; | |
725 | } | |
726 | return rc; | |
b55d295e DG |
727 | } |
728 | ||
0b0b8310 DG |
729 | if (flags != 0) { |
730 | return H_PARAMETER; | |
731 | } | |
732 | ||
733 | if (!pending || (pending->shift != shift)) { | |
734 | /* no matching prepare */ | |
735 | return H_CLOSED; | |
736 | } | |
737 | ||
738 | if (!pending->complete) { | |
739 | /* prepare has not completed */ | |
740 | return H_BUSY; | |
741 | } | |
742 | ||
743 | /* Shouldn't have got past PREPARE without an HPT */ | |
744 | g_assert(spapr->htab_shift); | |
745 | ||
746 | newsize = 1ULL << pending->shift; | |
747 | rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), | |
748 | pending->hpt, newsize); | |
749 | if (rc == H_SUCCESS) { | |
750 | qemu_vfree(spapr->htab); | |
751 | spapr->htab = pending->hpt; | |
752 | spapr->htab_shift = pending->shift; | |
753 | ||
1ec26c75 | 754 | push_sregs_to_kvm_pr(spapr); |
b55d295e | 755 | |
0b0b8310 DG |
756 | pending->hpt = NULL; /* so it's not free()d */ |
757 | } | |
758 | ||
759 | /* Clean up */ | |
760 | spapr->pending_hpt = NULL; | |
761 | free_pending_hpt(pending); | |
762 | ||
763 | return rc; | |
30f4b05b DG |
764 | } |
765 | ||
ce2918cb | 766 | static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, |
423576f7 TH |
767 | target_ulong opcode, target_ulong *args) |
768 | { | |
769 | cpu_synchronize_state(CPU(cpu)); | |
770 | cpu->env.spr[SPR_SPRG0] = args[0]; | |
771 | ||
772 | return H_SUCCESS; | |
773 | } | |
774 | ||
ce2918cb | 775 | static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, |
821303f5 DG |
776 | target_ulong opcode, target_ulong *args) |
777 | { | |
af08a58f TH |
778 | if (!has_spr(cpu, SPR_DABR)) { |
779 | return H_HARDWARE; /* DABR register not available */ | |
780 | } | |
781 | cpu_synchronize_state(CPU(cpu)); | |
782 | ||
783 | if (has_spr(cpu, SPR_DABRX)) { | |
784 | cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ | |
785 | } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ | |
786 | return H_RESERVED_DABR; | |
787 | } | |
788 | ||
789 | cpu->env.spr[SPR_DABR] = args[0]; | |
790 | return H_SUCCESS; | |
821303f5 DG |
791 | } |
792 | ||
ce2918cb | 793 | static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, |
e49ff266 TH |
794 | target_ulong opcode, target_ulong *args) |
795 | { | |
796 | target_ulong dabrx = args[1]; | |
797 | ||
798 | if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { | |
799 | return H_HARDWARE; | |
800 | } | |
801 | ||
802 | if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 | |
803 | || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { | |
804 | return H_PARAMETER; | |
805 | } | |
806 | ||
807 | cpu_synchronize_state(CPU(cpu)); | |
808 | cpu->env.spr[SPR_DABRX] = dabrx; | |
809 | cpu->env.spr[SPR_DABR] = args[0]; | |
810 | ||
811 | return H_SUCCESS; | |
812 | } | |
813 | ||
ce2918cb | 814 | static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, |
3240dd9a TH |
815 | target_ulong opcode, target_ulong *args) |
816 | { | |
817 | target_ulong flags = args[0]; | |
818 | hwaddr dst = args[1]; | |
819 | hwaddr src = args[2]; | |
820 | hwaddr len = TARGET_PAGE_SIZE; | |
821 | uint8_t *pdst, *psrc; | |
822 | target_long ret = H_SUCCESS; | |
823 | ||
824 | if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE | |
825 | | H_COPY_PAGE | H_ZERO_PAGE)) { | |
826 | qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", | |
827 | flags); | |
828 | return H_PARAMETER; | |
829 | } | |
830 | ||
831 | /* Map-in destination */ | |
832 | if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { | |
833 | return H_PARAMETER; | |
834 | } | |
85eb7c18 | 835 | pdst = cpu_physical_memory_map(dst, &len, true); |
3240dd9a TH |
836 | if (!pdst || len != TARGET_PAGE_SIZE) { |
837 | return H_PARAMETER; | |
838 | } | |
839 | ||
840 | if (flags & H_COPY_PAGE) { | |
841 | /* Map-in source, copy to destination, and unmap source again */ | |
842 | if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { | |
843 | ret = H_PARAMETER; | |
844 | goto unmap_out; | |
845 | } | |
85eb7c18 | 846 | psrc = cpu_physical_memory_map(src, &len, false); |
3240dd9a TH |
847 | if (!psrc || len != TARGET_PAGE_SIZE) { |
848 | ret = H_PARAMETER; | |
849 | goto unmap_out; | |
850 | } | |
851 | memcpy(pdst, psrc, len); | |
852 | cpu_physical_memory_unmap(psrc, len, 0, len); | |
853 | } else if (flags & H_ZERO_PAGE) { | |
854 | memset(pdst, 0, len); /* Just clear the destination page */ | |
855 | } | |
856 | ||
857 | if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { | |
858 | kvmppc_dcbst_range(cpu, pdst, len); | |
859 | } | |
860 | if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { | |
861 | if (kvm_enabled()) { | |
862 | kvmppc_icbi_range(cpu, pdst, len); | |
863 | } else { | |
864 | tb_flush(CPU(cpu)); | |
865 | } | |
866 | } | |
867 | ||
868 | unmap_out: | |
869 | cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); | |
870 | return ret; | |
871 | } | |
872 | ||
ed120055 DG |
873 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
874 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL | |
875 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL | |
876 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL | |
877 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL | |
878 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL | |
879 | ||
7388efaf | 880 | static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) |
ed120055 | 881 | { |
7388efaf DG |
882 | CPUState *cs = CPU(cpu); |
883 | CPUPPCState *env = &cpu->env; | |
ce2918cb | 884 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
ed120055 DG |
885 | uint16_t size; |
886 | uint8_t tmp; | |
887 | ||
888 | if (vpa == 0) { | |
889 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); | |
890 | return H_HARDWARE; | |
891 | } | |
892 | ||
893 | if (vpa % env->dcache_line_size) { | |
894 | return H_PARAMETER; | |
895 | } | |
896 | /* FIXME: bounds check the address */ | |
897 | ||
41701aa4 | 898 | size = lduw_be_phys(cs->as, vpa + 0x4); |
ed120055 DG |
899 | |
900 | if (size < VPA_MIN_SIZE) { | |
901 | return H_PARAMETER; | |
902 | } | |
903 | ||
904 | /* VPA is not allowed to cross a page boundary */ | |
905 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { | |
906 | return H_PARAMETER; | |
907 | } | |
908 | ||
7388efaf | 909 | spapr_cpu->vpa_addr = vpa; |
ed120055 | 910 | |
7388efaf | 911 | tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); |
ed120055 | 912 | tmp |= VPA_SHARED_PROC_VAL; |
7388efaf | 913 | stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
ed120055 DG |
914 | |
915 | return H_SUCCESS; | |
916 | } | |
917 | ||
7388efaf | 918 | static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) |
ed120055 | 919 | { |
ce2918cb | 920 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
7388efaf DG |
921 | |
922 | if (spapr_cpu->slb_shadow_addr) { | |
ed120055 DG |
923 | return H_RESOURCE; |
924 | } | |
925 | ||
7388efaf | 926 | if (spapr_cpu->dtl_addr) { |
ed120055 DG |
927 | return H_RESOURCE; |
928 | } | |
929 | ||
7388efaf | 930 | spapr_cpu->vpa_addr = 0; |
ed120055 DG |
931 | return H_SUCCESS; |
932 | } | |
933 | ||
7388efaf | 934 | static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) |
ed120055 | 935 | { |
ce2918cb | 936 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
ed120055 DG |
937 | uint32_t size; |
938 | ||
939 | if (addr == 0) { | |
940 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); | |
941 | return H_HARDWARE; | |
942 | } | |
943 | ||
7388efaf | 944 | size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); |
ed120055 DG |
945 | if (size < 0x8) { |
946 | return H_PARAMETER; | |
947 | } | |
948 | ||
949 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { | |
950 | return H_PARAMETER; | |
951 | } | |
952 | ||
7388efaf | 953 | if (!spapr_cpu->vpa_addr) { |
ed120055 DG |
954 | return H_RESOURCE; |
955 | } | |
956 | ||
7388efaf DG |
957 | spapr_cpu->slb_shadow_addr = addr; |
958 | spapr_cpu->slb_shadow_size = size; | |
ed120055 DG |
959 | |
960 | return H_SUCCESS; | |
961 | } | |
962 | ||
7388efaf | 963 | static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) |
ed120055 | 964 | { |
ce2918cb | 965 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
7388efaf DG |
966 | |
967 | spapr_cpu->slb_shadow_addr = 0; | |
968 | spapr_cpu->slb_shadow_size = 0; | |
ed120055 DG |
969 | return H_SUCCESS; |
970 | } | |
971 | ||
7388efaf | 972 | static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) |
ed120055 | 973 | { |
ce2918cb | 974 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
ed120055 DG |
975 | uint32_t size; |
976 | ||
977 | if (addr == 0) { | |
978 | hcall_dprintf("Can't cope with DTL at logical 0\n"); | |
979 | return H_HARDWARE; | |
980 | } | |
981 | ||
7388efaf | 982 | size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); |
ed120055 DG |
983 | |
984 | if (size < 48) { | |
985 | return H_PARAMETER; | |
986 | } | |
987 | ||
7388efaf | 988 | if (!spapr_cpu->vpa_addr) { |
ed120055 DG |
989 | return H_RESOURCE; |
990 | } | |
991 | ||
7388efaf DG |
992 | spapr_cpu->dtl_addr = addr; |
993 | spapr_cpu->dtl_size = size; | |
ed120055 DG |
994 | |
995 | return H_SUCCESS; | |
996 | } | |
997 | ||
7388efaf | 998 | static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) |
ed120055 | 999 | { |
ce2918cb | 1000 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
7388efaf DG |
1001 | |
1002 | spapr_cpu->dtl_addr = 0; | |
1003 | spapr_cpu->dtl_size = 0; | |
ed120055 DG |
1004 | |
1005 | return H_SUCCESS; | |
1006 | } | |
1007 | ||
ce2918cb | 1008 | static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, |
ed120055 DG |
1009 | target_ulong opcode, target_ulong *args) |
1010 | { | |
1011 | target_ulong flags = args[0]; | |
1012 | target_ulong procno = args[1]; | |
1013 | target_ulong vpa = args[2]; | |
1014 | target_ulong ret = H_PARAMETER; | |
0f20ba62 | 1015 | PowerPCCPU *tcpu; |
ed120055 | 1016 | |
2e886fb3 | 1017 | tcpu = spapr_find_cpu(procno); |
5353d03d | 1018 | if (!tcpu) { |
ed120055 DG |
1019 | return H_PARAMETER; |
1020 | } | |
1021 | ||
1022 | switch (flags) { | |
1023 | case FLAGS_REGISTER_VPA: | |
7388efaf | 1024 | ret = register_vpa(tcpu, vpa); |
ed120055 DG |
1025 | break; |
1026 | ||
1027 | case FLAGS_DEREGISTER_VPA: | |
7388efaf | 1028 | ret = deregister_vpa(tcpu, vpa); |
ed120055 DG |
1029 | break; |
1030 | ||
1031 | case FLAGS_REGISTER_SLBSHADOW: | |
7388efaf | 1032 | ret = register_slb_shadow(tcpu, vpa); |
ed120055 DG |
1033 | break; |
1034 | ||
1035 | case FLAGS_DEREGISTER_SLBSHADOW: | |
7388efaf | 1036 | ret = deregister_slb_shadow(tcpu, vpa); |
ed120055 DG |
1037 | break; |
1038 | ||
1039 | case FLAGS_REGISTER_DTL: | |
7388efaf | 1040 | ret = register_dtl(tcpu, vpa); |
ed120055 DG |
1041 | break; |
1042 | ||
1043 | case FLAGS_DEREGISTER_DTL: | |
7388efaf | 1044 | ret = deregister_dtl(tcpu, vpa); |
ed120055 DG |
1045 | break; |
1046 | } | |
1047 | ||
1048 | return ret; | |
1049 | } | |
1050 | ||
ce2918cb | 1051 | static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, |
ed120055 DG |
1052 | target_ulong opcode, target_ulong *args) |
1053 | { | |
b13ce26d | 1054 | CPUPPCState *env = &cpu->env; |
fcd7d003 | 1055 | CPUState *cs = CPU(cpu); |
3a6e6224 | 1056 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); |
b13ce26d | 1057 | |
ed120055 DG |
1058 | env->msr |= (1ULL << MSR_EE); |
1059 | hreg_compute_hflags(env); | |
3a6e6224 NP |
1060 | |
1061 | if (spapr_cpu->prod) { | |
1062 | spapr_cpu->prod = false; | |
1063 | return H_SUCCESS; | |
1064 | } | |
1065 | ||
fcd7d003 | 1066 | if (!cpu_has_work(cs)) { |
259186a7 | 1067 | cs->halted = 1; |
27103424 | 1068 | cs->exception_index = EXCP_HLT; |
fcd7d003 | 1069 | cs->exit_request = 1; |
ed120055 | 1070 | } |
3a6e6224 NP |
1071 | |
1072 | return H_SUCCESS; | |
1073 | } | |
1074 | ||
10741314 NP |
1075 | /* |
1076 | * Confer to self, aka join. Cede could use the same pattern as well, if | |
1077 | * EXCP_HLT can be changed to ECXP_HALTED. | |
1078 | */ | |
1079 | static target_ulong h_confer_self(PowerPCCPU *cpu) | |
1080 | { | |
1081 | CPUState *cs = CPU(cpu); | |
1082 | SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); | |
1083 | ||
1084 | if (spapr_cpu->prod) { | |
1085 | spapr_cpu->prod = false; | |
1086 | return H_SUCCESS; | |
1087 | } | |
1088 | cs->halted = 1; | |
1089 | cs->exception_index = EXCP_HALTED; | |
1090 | cs->exit_request = 1; | |
1091 | ||
1092 | return H_SUCCESS; | |
1093 | } | |
1094 | ||
1095 | static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, | |
1096 | target_ulong opcode, target_ulong *args) | |
1097 | { | |
1098 | CPUPPCState *env = &cpu->env; | |
1099 | CPUState *cs; | |
1100 | bool last_unjoined = true; | |
1101 | ||
1102 | if (env->msr & (1ULL << MSR_EE)) { | |
1103 | return H_BAD_MODE; | |
1104 | } | |
1105 | ||
1106 | /* | |
1107 | * Must not join the last CPU running. Interestingly, no such restriction | |
1108 | * for H_CONFER-to-self, but that is probably not intended to be used | |
1109 | * when H_JOIN is available. | |
1110 | */ | |
1111 | CPU_FOREACH(cs) { | |
1112 | PowerPCCPU *c = POWERPC_CPU(cs); | |
1113 | CPUPPCState *e = &c->env; | |
1114 | if (c == cpu) { | |
1115 | continue; | |
1116 | } | |
1117 | ||
1118 | /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ | |
1119 | if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { | |
1120 | last_unjoined = false; | |
1121 | break; | |
1122 | } | |
1123 | } | |
1124 | if (last_unjoined) { | |
1125 | return H_CONTINUE; | |
1126 | } | |
1127 | ||
1128 | return h_confer_self(cpu); | |
1129 | } | |
1130 | ||
e8ce0e40 NP |
1131 | static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, |
1132 | target_ulong opcode, target_ulong *args) | |
1133 | { | |
1134 | target_long target = args[0]; | |
1135 | uint32_t dispatch = args[1]; | |
1136 | CPUState *cs = CPU(cpu); | |
1137 | SpaprCpuState *spapr_cpu; | |
1138 | ||
1139 | /* | |
1140 | * -1 means confer to all other CPUs without dispatch counter check, | |
1141 | * otherwise it's a targeted confer. | |
1142 | */ | |
1143 | if (target != -1) { | |
1144 | PowerPCCPU *target_cpu = spapr_find_cpu(target); | |
1145 | uint32_t target_dispatch; | |
1146 | ||
1147 | if (!target_cpu) { | |
1148 | return H_PARAMETER; | |
1149 | } | |
1150 | ||
e8ce0e40 NP |
1151 | /* |
1152 | * target == self is a special case, we wait until prodded, without | |
1153 | * dispatch counter check. | |
1154 | */ | |
1155 | if (cpu == target_cpu) { | |
10741314 | 1156 | return h_confer_self(cpu); |
e8ce0e40 NP |
1157 | } |
1158 | ||
10741314 | 1159 | spapr_cpu = spapr_cpu_state(target_cpu); |
e8ce0e40 NP |
1160 | if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { |
1161 | return H_SUCCESS; | |
1162 | } | |
1163 | ||
1164 | target_dispatch = ldl_be_phys(cs->as, | |
1165 | spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); | |
1166 | if (target_dispatch != dispatch) { | |
1167 | return H_SUCCESS; | |
1168 | } | |
1169 | ||
1170 | /* | |
1171 | * The targeted confer does not do anything special beyond yielding | |
1172 | * the current vCPU, but even this should be better than nothing. | |
1173 | * At least for single-threaded tcg, it gives the target a chance to | |
1174 | * run before we run again. Multi-threaded tcg does not really do | |
1175 | * anything with EXCP_YIELD yet. | |
1176 | */ | |
1177 | } | |
1178 | ||
1179 | cs->exception_index = EXCP_YIELD; | |
1180 | cs->exit_request = 1; | |
1181 | cpu_loop_exit(cs); | |
1182 | ||
1183 | return H_SUCCESS; | |
1184 | } | |
1185 | ||
3a6e6224 NP |
1186 | static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, |
1187 | target_ulong opcode, target_ulong *args) | |
1188 | { | |
1189 | target_long target = args[0]; | |
1190 | PowerPCCPU *tcpu; | |
1191 | CPUState *cs; | |
1192 | SpaprCpuState *spapr_cpu; | |
1193 | ||
1194 | tcpu = spapr_find_cpu(target); | |
1195 | cs = CPU(tcpu); | |
1196 | if (!cs) { | |
1197 | return H_PARAMETER; | |
1198 | } | |
1199 | ||
1200 | spapr_cpu = spapr_cpu_state(tcpu); | |
1201 | spapr_cpu->prod = true; | |
1202 | cs->halted = 0; | |
1203 | qemu_cpu_kick(cs); | |
1204 | ||
ed120055 DG |
1205 | return H_SUCCESS; |
1206 | } | |
1207 | ||
ce2918cb | 1208 | static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, |
39ac8455 DG |
1209 | target_ulong opcode, target_ulong *args) |
1210 | { | |
1211 | target_ulong rtas_r3 = args[0]; | |
4fe822e0 AK |
1212 | uint32_t token = rtas_ld(rtas_r3, 0); |
1213 | uint32_t nargs = rtas_ld(rtas_r3, 1); | |
1214 | uint32_t nret = rtas_ld(rtas_r3, 2); | |
39ac8455 | 1215 | |
210b580b | 1216 | return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, |
39ac8455 DG |
1217 | nret, rtas_r3 + 12 + 4*nargs); |
1218 | } | |
1219 | ||
ce2918cb | 1220 | static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, |
827200a2 DG |
1221 | target_ulong opcode, target_ulong *args) |
1222 | { | |
fdfba1a2 | 1223 | CPUState *cs = CPU(cpu); |
827200a2 DG |
1224 | target_ulong size = args[0]; |
1225 | target_ulong addr = args[1]; | |
1226 | ||
1227 | switch (size) { | |
1228 | case 1: | |
2c17449b | 1229 | args[0] = ldub_phys(cs->as, addr); |
827200a2 DG |
1230 | return H_SUCCESS; |
1231 | case 2: | |
41701aa4 | 1232 | args[0] = lduw_phys(cs->as, addr); |
827200a2 DG |
1233 | return H_SUCCESS; |
1234 | case 4: | |
fdfba1a2 | 1235 | args[0] = ldl_phys(cs->as, addr); |
827200a2 DG |
1236 | return H_SUCCESS; |
1237 | case 8: | |
2c17449b | 1238 | args[0] = ldq_phys(cs->as, addr); |
827200a2 DG |
1239 | return H_SUCCESS; |
1240 | } | |
1241 | return H_PARAMETER; | |
1242 | } | |
1243 | ||
ce2918cb | 1244 | static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, |
827200a2 DG |
1245 | target_ulong opcode, target_ulong *args) |
1246 | { | |
f606604f EI |
1247 | CPUState *cs = CPU(cpu); |
1248 | ||
827200a2 DG |
1249 | target_ulong size = args[0]; |
1250 | target_ulong addr = args[1]; | |
1251 | target_ulong val = args[2]; | |
1252 | ||
1253 | switch (size) { | |
1254 | case 1: | |
db3be60d | 1255 | stb_phys(cs->as, addr, val); |
827200a2 DG |
1256 | return H_SUCCESS; |
1257 | case 2: | |
5ce5944d | 1258 | stw_phys(cs->as, addr, val); |
827200a2 DG |
1259 | return H_SUCCESS; |
1260 | case 4: | |
ab1da857 | 1261 | stl_phys(cs->as, addr, val); |
827200a2 DG |
1262 | return H_SUCCESS; |
1263 | case 8: | |
f606604f | 1264 | stq_phys(cs->as, addr, val); |
827200a2 DG |
1265 | return H_SUCCESS; |
1266 | } | |
1267 | return H_PARAMETER; | |
1268 | } | |
1269 | ||
ce2918cb | 1270 | static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, |
c73e3771 BH |
1271 | target_ulong opcode, target_ulong *args) |
1272 | { | |
fdfba1a2 EI |
1273 | CPUState *cs = CPU(cpu); |
1274 | ||
c73e3771 BH |
1275 | target_ulong dst = args[0]; /* Destination address */ |
1276 | target_ulong src = args[1]; /* Source address */ | |
1277 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ | |
1278 | target_ulong count = args[3]; /* Element count */ | |
1279 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ | |
1280 | uint64_t tmp; | |
1281 | unsigned int mask = (1 << esize) - 1; | |
1282 | int step = 1 << esize; | |
1283 | ||
1284 | if (count > 0x80000000) { | |
1285 | return H_PARAMETER; | |
1286 | } | |
1287 | ||
1288 | if ((dst & mask) || (src & mask) || (op > 1)) { | |
1289 | return H_PARAMETER; | |
1290 | } | |
1291 | ||
1292 | if (dst >= src && dst < (src + (count << esize))) { | |
1293 | dst = dst + ((count - 1) << esize); | |
1294 | src = src + ((count - 1) << esize); | |
1295 | step = -step; | |
1296 | } | |
1297 | ||
1298 | while (count--) { | |
1299 | switch (esize) { | |
1300 | case 0: | |
2c17449b | 1301 | tmp = ldub_phys(cs->as, src); |
c73e3771 BH |
1302 | break; |
1303 | case 1: | |
41701aa4 | 1304 | tmp = lduw_phys(cs->as, src); |
c73e3771 BH |
1305 | break; |
1306 | case 2: | |
fdfba1a2 | 1307 | tmp = ldl_phys(cs->as, src); |
c73e3771 BH |
1308 | break; |
1309 | case 3: | |
2c17449b | 1310 | tmp = ldq_phys(cs->as, src); |
c73e3771 BH |
1311 | break; |
1312 | default: | |
1313 | return H_PARAMETER; | |
1314 | } | |
1315 | if (op == 1) { | |
1316 | tmp = ~tmp; | |
1317 | } | |
1318 | switch (esize) { | |
1319 | case 0: | |
db3be60d | 1320 | stb_phys(cs->as, dst, tmp); |
c73e3771 BH |
1321 | break; |
1322 | case 1: | |
5ce5944d | 1323 | stw_phys(cs->as, dst, tmp); |
c73e3771 BH |
1324 | break; |
1325 | case 2: | |
ab1da857 | 1326 | stl_phys(cs->as, dst, tmp); |
c73e3771 BH |
1327 | break; |
1328 | case 3: | |
f606604f | 1329 | stq_phys(cs->as, dst, tmp); |
c73e3771 BH |
1330 | break; |
1331 | } | |
1332 | dst = dst + step; | |
1333 | src = src + step; | |
1334 | } | |
1335 | ||
1336 | return H_SUCCESS; | |
1337 | } | |
1338 | ||
ce2918cb | 1339 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, |
827200a2 DG |
1340 | target_ulong opcode, target_ulong *args) |
1341 | { | |
1342 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
1343 | return H_SUCCESS; | |
1344 | } | |
1345 | ||
ce2918cb | 1346 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, |
827200a2 DG |
1347 | target_ulong opcode, target_ulong *args) |
1348 | { | |
1349 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
1350 | return H_SUCCESS; | |
1351 | } | |
1352 | ||
7d0cd464 PM |
1353 | static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, |
1354 | target_ulong mflags, | |
1355 | target_ulong value1, | |
1356 | target_ulong value2) | |
42561bf2 | 1357 | { |
c4015bbd AK |
1358 | if (value1) { |
1359 | return H_P3; | |
1360 | } | |
1361 | if (value2) { | |
1362 | return H_P4; | |
1363 | } | |
1364 | ||
1365 | switch (mflags) { | |
1366 | case H_SET_MODE_ENDIAN_BIG: | |
00fd075e | 1367 | spapr_set_all_lpcrs(0, LPCR_ILE); |
eefaccc0 | 1368 | spapr_pci_switch_vga(true); |
c4015bbd AK |
1369 | return H_SUCCESS; |
1370 | ||
1371 | case H_SET_MODE_ENDIAN_LITTLE: | |
00fd075e | 1372 | spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); |
eefaccc0 | 1373 | spapr_pci_switch_vga(false); |
c4015bbd AK |
1374 | return H_SUCCESS; |
1375 | } | |
42561bf2 | 1376 | |
c4015bbd AK |
1377 | return H_UNSUPPORTED_FLAG; |
1378 | } | |
42561bf2 | 1379 | |
7d0cd464 PM |
1380 | static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, |
1381 | target_ulong mflags, | |
1382 | target_ulong value1, | |
1383 | target_ulong value2) | |
d5ac4f54 | 1384 | { |
d5ac4f54 | 1385 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
d5ac4f54 AK |
1386 | |
1387 | if (!(pcc->insns_flags2 & PPC2_ISA207S)) { | |
1388 | return H_P2; | |
1389 | } | |
1390 | if (value1) { | |
1391 | return H_P3; | |
1392 | } | |
1393 | if (value2) { | |
1394 | return H_P4; | |
1395 | } | |
1396 | ||
5c94b2a5 | 1397 | if (mflags == AIL_RESERVED) { |
d5ac4f54 AK |
1398 | return H_UNSUPPORTED_FLAG; |
1399 | } | |
1400 | ||
00fd075e | 1401 | spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); |
d5ac4f54 AK |
1402 | |
1403 | return H_SUCCESS; | |
1404 | } | |
1405 | ||
ce2918cb | 1406 | static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, |
c4015bbd AK |
1407 | target_ulong opcode, target_ulong *args) |
1408 | { | |
1409 | target_ulong resource = args[1]; | |
1410 | target_ulong ret = H_P2; | |
1411 | ||
1412 | switch (resource) { | |
1413 | case H_SET_MODE_RESOURCE_LE: | |
7d0cd464 | 1414 | ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); |
c4015bbd | 1415 | break; |
d5ac4f54 | 1416 | case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: |
7d0cd464 PM |
1417 | ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], |
1418 | args[2], args[3]); | |
d5ac4f54 | 1419 | break; |
42561bf2 AB |
1420 | } |
1421 | ||
42561bf2 AB |
1422 | return ret; |
1423 | } | |
1424 | ||
ce2918cb | 1425 | static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, |
d77a98b0 SJS |
1426 | target_ulong opcode, target_ulong *args) |
1427 | { | |
1428 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", | |
1429 | opcode, " (H_CLEAN_SLB)"); | |
1430 | return H_FUNCTION; | |
1431 | } | |
1432 | ||
ce2918cb | 1433 | static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, |
d77a98b0 SJS |
1434 | target_ulong opcode, target_ulong *args) |
1435 | { | |
1436 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", | |
1437 | opcode, " (H_INVALIDATE_PID)"); | |
1438 | return H_FUNCTION; | |
1439 | } | |
1440 | ||
ce2918cb | 1441 | static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, |
b4db5413 SJS |
1442 | uint64_t patbe_old, uint64_t patbe_new) |
1443 | { | |
1444 | /* | |
1445 | * We have 4 Options: | |
1446 | * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing | |
1447 | * HASH->RADIX : Free HPT | |
1448 | * RADIX->HASH : Allocate HPT | |
1449 | * NOTHING->HASH : Allocate HPT | |
1450 | * Note: NOTHING implies the case where we said the guest could choose | |
1451 | * later and so assumed radix and now it's called H_REG_PROC_TBL | |
1452 | */ | |
1453 | ||
79825f4d | 1454 | if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { |
b4db5413 | 1455 | /* We assume RADIX, so this catches all the "Do Nothing" cases */ |
79825f4d | 1456 | } else if (!(patbe_old & PATE1_GR)) { |
b4db5413 | 1457 | /* HASH->RADIX : Free HPT */ |
06ec79e8 | 1458 | spapr_free_hpt(spapr); |
79825f4d | 1459 | } else if (!(patbe_new & PATE1_GR)) { |
b4db5413 | 1460 | /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ |
8897ea5a | 1461 | spapr_setup_hpt(spapr); |
b4db5413 SJS |
1462 | } |
1463 | return; | |
1464 | } | |
1465 | ||
1466 | #define FLAGS_MASK 0x01FULL | |
1467 | #define FLAG_MODIFY 0x10 | |
1468 | #define FLAG_REGISTER 0x08 | |
1469 | #define FLAG_RADIX 0x04 | |
1470 | #define FLAG_HASH_PROC_TBL 0x02 | |
1471 | #define FLAG_GTSE 0x01 | |
1472 | ||
d77a98b0 | 1473 | static target_ulong h_register_process_table(PowerPCCPU *cpu, |
ce2918cb | 1474 | SpaprMachineState *spapr, |
d77a98b0 SJS |
1475 | target_ulong opcode, |
1476 | target_ulong *args) | |
1477 | { | |
b4db5413 SJS |
1478 | target_ulong flags = args[0]; |
1479 | target_ulong proc_tbl = args[1]; | |
1480 | target_ulong page_size = args[2]; | |
1481 | target_ulong table_size = args[3]; | |
176dccee | 1482 | target_ulong update_lpcr = 0; |
b4db5413 SJS |
1483 | uint64_t cproc; |
1484 | ||
1485 | if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ | |
1486 | return H_PARAMETER; | |
1487 | } | |
1488 | if (flags & FLAG_MODIFY) { | |
1489 | if (flags & FLAG_REGISTER) { | |
1490 | if (flags & FLAG_RADIX) { /* Register new RADIX process table */ | |
1491 | if (proc_tbl & 0xfff || proc_tbl >> 60) { | |
1492 | return H_P2; | |
1493 | } else if (page_size) { | |
1494 | return H_P3; | |
1495 | } else if (table_size > 24) { | |
1496 | return H_P4; | |
1497 | } | |
79825f4d | 1498 | cproc = PATE1_GR | proc_tbl | table_size; |
b4db5413 SJS |
1499 | } else { /* Register new HPT process table */ |
1500 | if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ | |
1501 | /* TODO - Not Supported */ | |
1502 | /* Technically caused by flag bits => H_PARAMETER */ | |
1503 | return H_PARAMETER; | |
1504 | } else { /* Hash with SLB */ | |
1505 | if (proc_tbl >> 38) { | |
1506 | return H_P2; | |
1507 | } else if (page_size & ~0x7) { | |
1508 | return H_P3; | |
1509 | } else if (table_size > 24) { | |
1510 | return H_P4; | |
1511 | } | |
1512 | } | |
1513 | cproc = (proc_tbl << 25) | page_size << 5 | table_size; | |
1514 | } | |
1515 | ||
1516 | } else { /* Deregister current process table */ | |
79825f4d BH |
1517 | /* |
1518 | * Set to benign value: (current GR) | 0. This allows | |
1519 | * deregistration in KVM to succeed even if the radix bit | |
1520 | * in flags doesn't match the radix bit in the old PATE. | |
1521 | */ | |
1522 | cproc = spapr->patb_entry & PATE1_GR; | |
b4db5413 SJS |
1523 | } |
1524 | } else { /* Maintain current registration */ | |
79825f4d | 1525 | if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { |
b4db5413 SJS |
1526 | /* Technically caused by flag bits => H_PARAMETER */ |
1527 | return H_PARAMETER; /* Existing Process Table Mismatch */ | |
1528 | } | |
1529 | cproc = spapr->patb_entry; | |
1530 | } | |
1531 | ||
1532 | /* Check if we need to setup OR free the hpt */ | |
1533 | spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); | |
1534 | ||
1535 | spapr->patb_entry = cproc; /* Save new process table */ | |
6de83307 | 1536 | |
00fd075e | 1537 | /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ |
176dccee SJS |
1538 | if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ |
1539 | update_lpcr |= (LPCR_UPRT | LPCR_HR); | |
1540 | else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ | |
1541 | update_lpcr |= LPCR_UPRT; | |
1542 | if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ | |
49e9fdd7 DG |
1543 | update_lpcr |= LPCR_GTSE; |
1544 | ||
176dccee | 1545 | spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); |
b4db5413 SJS |
1546 | |
1547 | if (kvm_enabled()) { | |
1548 | return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, | |
1549 | flags & FLAG_GTSE, cproc); | |
1550 | } | |
1551 | return H_SUCCESS; | |
d77a98b0 SJS |
1552 | } |
1553 | ||
1c7ad77e NP |
1554 | #define H_SIGNAL_SYS_RESET_ALL -1 |
1555 | #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 | |
1556 | ||
1557 | static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, | |
ce2918cb | 1558 | SpaprMachineState *spapr, |
1c7ad77e NP |
1559 | target_ulong opcode, target_ulong *args) |
1560 | { | |
1561 | target_long target = args[0]; | |
1562 | CPUState *cs; | |
1563 | ||
1564 | if (target < 0) { | |
1565 | /* Broadcast */ | |
1566 | if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { | |
1567 | return H_PARAMETER; | |
1568 | } | |
1569 | ||
1570 | CPU_FOREACH(cs) { | |
1571 | PowerPCCPU *c = POWERPC_CPU(cs); | |
1572 | ||
1573 | if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { | |
1574 | if (c == cpu) { | |
1575 | continue; | |
1576 | } | |
1577 | } | |
1578 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); | |
1579 | } | |
1580 | return H_SUCCESS; | |
1581 | ||
1582 | } else { | |
1583 | /* Unicast */ | |
2e886fb3 | 1584 | cs = CPU(spapr_find_cpu(target)); |
f57467e3 SB |
1585 | if (cs) { |
1586 | run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); | |
1587 | return H_SUCCESS; | |
1c7ad77e NP |
1588 | } |
1589 | return H_PARAMETER; | |
1590 | } | |
1591 | } | |
1592 | ||
ce2918cb | 1593 | static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu, |
cc7b35b1 GK |
1594 | target_ulong *addr, bool *raw_mode_supported, |
1595 | Error **errp) | |
2a6593cb | 1596 | { |
152ef803 | 1597 | bool explicit_match = false; /* Matched the CPU's real PVR */ |
7843c0d6 | 1598 | uint32_t max_compat = spapr->max_compat_pvr; |
152ef803 DG |
1599 | uint32_t best_compat = 0; |
1600 | int i; | |
3794d548 | 1601 | |
152ef803 DG |
1602 | /* |
1603 | * We scan the supplied table of PVRs looking for two things | |
1604 | * 1. Is our real CPU PVR in the list? | |
1605 | * 2. What's the "best" listed logical PVR | |
1606 | */ | |
1607 | for (i = 0; i < 512; ++i) { | |
3794d548 AK |
1608 | uint32_t pvr, pvr_mask; |
1609 | ||
80c33d34 DG |
1610 | pvr_mask = ldl_be_phys(&address_space_memory, *addr); |
1611 | pvr = ldl_be_phys(&address_space_memory, *addr + 4); | |
1612 | *addr += 8; | |
152ef803 | 1613 | |
3794d548 | 1614 | if (~pvr_mask & pvr) { |
152ef803 | 1615 | break; /* Terminator record */ |
3794d548 | 1616 | } |
152ef803 DG |
1617 | |
1618 | if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { | |
1619 | explicit_match = true; | |
1620 | } else { | |
1621 | if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { | |
1622 | best_compat = pvr; | |
1623 | } | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | if ((best_compat == 0) && (!explicit_match || max_compat)) { | |
1628 | /* We couldn't find a suitable compatibility mode, and either | |
1629 | * the guest doesn't support "raw" mode for this CPU, or raw | |
1630 | * mode is disabled because a maximum compat mode is set */ | |
80c33d34 DG |
1631 | error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); |
1632 | return 0; | |
3794d548 AK |
1633 | } |
1634 | ||
cc7b35b1 GK |
1635 | *raw_mode_supported = explicit_match; |
1636 | ||
3794d548 | 1637 | /* Parsing finished */ |
152ef803 | 1638 | trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); |
3794d548 | 1639 | |
80c33d34 DG |
1640 | return best_compat; |
1641 | } | |
3794d548 | 1642 | |
ad334d89 | 1643 | static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr) |
0c21e073 | 1644 | { |
4b63db12 | 1645 | Object *drc_container; |
0c21e073 DG |
1646 | ObjectProperty *prop; |
1647 | ObjectPropertyIterator iter; | |
1648 | ||
1649 | drc_container = container_get(object_get_root(), "/dr-connector"); | |
1650 | object_property_iter_init(&iter, drc_container); | |
1651 | while ((prop = object_property_iter_next(&iter))) { | |
4b63db12 GK |
1652 | SpaprDrc *drc; |
1653 | ||
0c21e073 DG |
1654 | if (!strstart(prop->type, "link<", NULL)) { |
1655 | continue; | |
1656 | } | |
4b63db12 GK |
1657 | drc = SPAPR_DR_CONNECTOR(object_property_get_link(drc_container, |
1658 | prop->name, NULL)); | |
1659 | ||
1660 | if (spapr_drc_transient(drc)) { | |
ad334d89 | 1661 | spapr_drc_reset(drc); |
0c21e073 DG |
1662 | } |
1663 | } | |
ad334d89 GK |
1664 | |
1665 | spapr_clear_pending_hotplug_events(spapr); | |
0c21e073 DG |
1666 | } |
1667 | ||
80c33d34 | 1668 | static target_ulong h_client_architecture_support(PowerPCCPU *cpu, |
ce2918cb | 1669 | SpaprMachineState *spapr, |
80c33d34 DG |
1670 | target_ulong opcode, |
1671 | target_ulong *args) | |
1672 | { | |
1673 | /* Working address in data buffer */ | |
1674 | target_ulong addr = ppc64_phys_to_real(args[0]); | |
0c21e073 DG |
1675 | target_ulong fdt_buf = args[1]; |
1676 | target_ulong fdt_bufsize = args[2]; | |
80c33d34 DG |
1677 | target_ulong ov_table; |
1678 | uint32_t cas_pvr; | |
d1d32d62 | 1679 | SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old; |
80c33d34 DG |
1680 | bool guest_radix; |
1681 | Error *local_err = NULL; | |
cc7b35b1 | 1682 | bool raw_mode_supported = false; |
e7f78db9 | 1683 | bool guest_xive; |
12b3868e GK |
1684 | CPUState *cs; |
1685 | ||
1686 | /* CAS is supposed to be called early when only the boot vCPU is active. */ | |
1687 | CPU_FOREACH(cs) { | |
1688 | if (cs == CPU(cpu)) { | |
1689 | continue; | |
1690 | } | |
1691 | if (!cs->halted) { | |
1692 | warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); | |
1693 | return H_MULTI_THREADS_ACTIVE; | |
1694 | } | |
1695 | } | |
80c33d34 | 1696 | |
cc7b35b1 | 1697 | cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); |
80c33d34 DG |
1698 | if (local_err) { |
1699 | error_report_err(local_err); | |
1700 | return H_HARDWARE; | |
1701 | } | |
1702 | ||
1703 | /* Update CPUs */ | |
1704 | if (cpu->compat_pvr != cas_pvr) { | |
1705 | ppc_set_compat_all(cas_pvr, &local_err); | |
f6f242c7 | 1706 | if (local_err) { |
cc7b35b1 GK |
1707 | /* We fail to set compat mode (likely because running with KVM PR), |
1708 | * but maybe we can fallback to raw mode if the guest supports it. | |
1709 | */ | |
1710 | if (!raw_mode_supported) { | |
1711 | error_report_err(local_err); | |
1712 | return H_HARDWARE; | |
1713 | } | |
2c9dfdac | 1714 | error_free(local_err); |
cc7b35b1 | 1715 | local_err = NULL; |
3794d548 AK |
1716 | } |
1717 | } | |
1718 | ||
03d196b7 | 1719 | /* For the future use: here @ov_table points to the first option vector */ |
80c33d34 | 1720 | ov_table = addr; |
03d196b7 | 1721 | |
e957f6a9 | 1722 | ov1_guest = spapr_ovec_parse_vector(ov_table, 1); |
cbd0d7f3 GK |
1723 | if (!ov1_guest) { |
1724 | warn_report("guest didn't provide option vector 1"); | |
1725 | return H_PARAMETER; | |
1726 | } | |
facdb8b6 | 1727 | ov5_guest = spapr_ovec_parse_vector(ov_table, 5); |
cbd0d7f3 | 1728 | if (!ov5_guest) { |
ce05fa0f | 1729 | spapr_ovec_cleanup(ov1_guest); |
cbd0d7f3 GK |
1730 | warn_report("guest didn't provide option vector 5"); |
1731 | return H_PARAMETER; | |
1732 | } | |
9fb4541f SB |
1733 | if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { |
1734 | error_report("guest requested hash and radix MMU, which is invalid."); | |
1735 | exit(EXIT_FAILURE); | |
1736 | } | |
e7f78db9 GK |
1737 | if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { |
1738 | error_report("guest requested an invalid interrupt mode"); | |
1739 | exit(EXIT_FAILURE); | |
1740 | } | |
1741 | ||
9fb4541f SB |
1742 | /* The radix/hash bit in byte 24 requires special handling: */ |
1743 | guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); | |
1744 | spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); | |
2a6593cb | 1745 | |
e7f78db9 GK |
1746 | guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); |
1747 | ||
2772cf6b DG |
1748 | /* |
1749 | * HPT resizing is a bit of a special case, because when enabled | |
1750 | * we assume an HPT guest will support it until it says it | |
1751 | * doesn't, instead of assuming it won't support it until it says | |
1752 | * it does. Strictly speaking that approach could break for | |
1753 | * guests which don't make a CAS call, but those are so old we | |
1754 | * don't care about them. Without that assumption we'd have to | |
1755 | * make at least a temporary allocation of an HPT sized for max | |
1756 | * memory, which could be impossibly difficult under KVM HV if | |
1757 | * maxram is large. | |
1758 | */ | |
1759 | if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { | |
1760 | int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); | |
1761 | ||
1762 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { | |
1763 | error_report( | |
1764 | "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); | |
1765 | exit(1); | |
1766 | } | |
1767 | ||
1768 | if (spapr->htab_shift < maxshift) { | |
1769 | /* Guest doesn't know about HPT resizing, so we | |
1770 | * pre-emptively resize for the maximum permitted RAM. At | |
1771 | * the point this is called, nothing should have been | |
1772 | * entered into the existing HPT */ | |
1773 | spapr_reallocate_hpt(spapr, maxshift, &error_fatal); | |
1ec26c75 | 1774 | push_sregs_to_kvm_pr(spapr); |
2772cf6b DG |
1775 | } |
1776 | } | |
1777 | ||
facdb8b6 MR |
1778 | /* NOTE: there are actually a number of ov5 bits where input from the |
1779 | * guest is always zero, and the platform/QEMU enables them independently | |
1780 | * of guest input. To model these properly we'd want some sort of mask, | |
1781 | * but since they only currently apply to memory migration as defined | |
1782 | * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need | |
6787d27b | 1783 | * to worry about this for now. |
facdb8b6 | 1784 | */ |
6787d27b | 1785 | ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); |
30bf9ed1 CLG |
1786 | |
1787 | /* also clear the radix/hash bit from the current ov5_cas bits to | |
1788 | * be in sync with the newly ov5 bits. Else the radix bit will be | |
1789 | * seen as being removed and this will generate a reset loop | |
1790 | */ | |
1791 | spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); | |
1792 | ||
6787d27b | 1793 | /* full range of negotiated ov5 capabilities */ |
facdb8b6 MR |
1794 | spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); |
1795 | spapr_ovec_cleanup(ov5_guest); | |
6787d27b MR |
1796 | /* capabilities that have been added since CAS-generated guest reset. |
1797 | * if capabilities have since been removed, generate another reset | |
1798 | */ | |
d1d32d62 | 1799 | spapr->cas_reboot = !spapr_ovec_subset(ov5_cas_old, spapr->ov5_cas); |
00005f22 | 1800 | spapr_ovec_cleanup(ov5_cas_old); |
9fb4541f SB |
1801 | /* Now that processing is finished, set the radix/hash bit for the |
1802 | * guest if it requested a valid mode; otherwise terminate the boot. */ | |
1803 | if (guest_radix) { | |
1804 | if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { | |
1805 | error_report("Guest requested unavailable MMU mode (radix)."); | |
1806 | exit(EXIT_FAILURE); | |
1807 | } | |
1808 | spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); | |
1809 | } else { | |
1810 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() | |
1811 | && !kvmppc_has_cap_mmu_hash_v3()) { | |
1812 | error_report("Guest requested unavailable MMU mode (hash)."); | |
1813 | exit(EXIT_FAILURE); | |
1814 | } | |
1815 | } | |
daa36379 | 1816 | spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); |
00005f22 | 1817 | spapr_ovec_cleanup(ov1_guest); |
13db0cd9 | 1818 | |
e7f78db9 | 1819 | /* |
8deb8019 DG |
1820 | * Ensure the guest asks for an interrupt mode we support; |
1821 | * otherwise terminate the boot. | |
e7f78db9 GK |
1822 | */ |
1823 | if (guest_xive) { | |
ca62823b | 1824 | if (!spapr->irq->xive) { |
75de5941 GK |
1825 | error_report( |
1826 | "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); | |
e7f78db9 GK |
1827 | exit(EXIT_FAILURE); |
1828 | } | |
1829 | } else { | |
ca62823b | 1830 | if (!spapr->irq->xics) { |
75de5941 GK |
1831 | error_report( |
1832 | "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); | |
e7f78db9 GK |
1833 | exit(EXIT_FAILURE); |
1834 | } | |
1835 | } | |
1836 | ||
8deb8019 DG |
1837 | spapr_irq_update_active_intc(spapr); |
1838 | ||
ad334d89 | 1839 | spapr_handle_transient_dev_before_cas(spapr); |
0c21e073 | 1840 | |
13db0cd9 | 1841 | if (!spapr->cas_reboot) { |
0c21e073 DG |
1842 | void *fdt; |
1843 | SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
1844 | ||
8deb8019 DG |
1845 | /* If spapr_machine_reset() did not set up a HPT but one is necessary |
1846 | * (because the guest isn't going to use radix) then set it up here. */ | |
1847 | if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { | |
1848 | /* legacy hash or new hash: */ | |
8897ea5a | 1849 | spapr_setup_hpt(spapr); |
8deb8019 | 1850 | } |
0c21e073 DG |
1851 | |
1852 | if (fdt_bufsize < sizeof(hdr)) { | |
1853 | error_report("SLOF provided insufficient CAS buffer " | |
1854 | TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); | |
1855 | exit(EXIT_FAILURE); | |
1856 | } | |
1857 | ||
1858 | fdt_bufsize -= sizeof(hdr); | |
1859 | ||
1860 | fdt = spapr_build_fdt(spapr, false, fdt_bufsize); | |
1861 | _FDT((fdt_pack(fdt))); | |
1862 | ||
1863 | cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); | |
1864 | cpu_physical_memory_write(fdt_buf + sizeof(hdr), fdt, | |
1865 | fdt_totalsize(fdt)); | |
1866 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
1867 | ||
1868 | g_free(spapr->fdt_blob); | |
1869 | spapr->fdt_size = fdt_totalsize(fdt); | |
1870 | spapr->fdt_initial_size = spapr->fdt_size; | |
1871 | spapr->fdt_blob = fdt; | |
13db0cd9 CLG |
1872 | } |
1873 | ||
6787d27b | 1874 | if (spapr->cas_reboot) { |
9146206e | 1875 | qemu_system_reset_request(SHUTDOWN_CAUSE_SUBSYSTEM_RESET); |
2a6593cb AK |
1876 | } |
1877 | ||
1878 | return H_SUCCESS; | |
1879 | } | |
1880 | ||
c24ba3d0 | 1881 | static target_ulong h_home_node_associativity(PowerPCCPU *cpu, |
ce2918cb | 1882 | SpaprMachineState *spapr, |
c24ba3d0 LV |
1883 | target_ulong opcode, |
1884 | target_ulong *args) | |
1885 | { | |
1886 | target_ulong flags = args[0]; | |
1887 | target_ulong procno = args[1]; | |
1888 | PowerPCCPU *tcpu; | |
1889 | int idx; | |
1890 | ||
1891 | /* only support procno from H_REGISTER_VPA */ | |
1892 | if (flags != 0x1) { | |
1893 | return H_FUNCTION; | |
1894 | } | |
1895 | ||
1896 | tcpu = spapr_find_cpu(procno); | |
1897 | if (tcpu == NULL) { | |
1898 | return H_P2; | |
1899 | } | |
1900 | ||
1901 | /* sequence is the same as in the "ibm,associativity" property */ | |
1902 | ||
1903 | idx = 0; | |
1904 | #define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \ | |
1905 | ((uint64_t)(b) & 0xffffffff)) | |
1906 | args[idx++] = ASSOCIATIVITY(0, 0); | |
1907 | args[idx++] = ASSOCIATIVITY(0, tcpu->node_id); | |
1908 | args[idx++] = ASSOCIATIVITY(procno, -1); | |
1909 | for ( ; idx < 6; idx++) { | |
1910 | args[idx] = -1; | |
1911 | } | |
1912 | #undef ASSOCIATIVITY | |
1913 | ||
1914 | return H_SUCCESS; | |
1915 | } | |
1916 | ||
c59704b2 | 1917 | static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, |
ce2918cb | 1918 | SpaprMachineState *spapr, |
c59704b2 SJS |
1919 | target_ulong opcode, |
1920 | target_ulong *args) | |
1921 | { | |
1922 | uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & | |
1923 | ~H_CPU_CHAR_THR_RECONF_TRIG; | |
1924 | uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; | |
1925 | uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); | |
1926 | uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); | |
1927 | uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); | |
8ff43ee4 SJS |
1928 | uint8_t count_cache_flush_assist = spapr_get_cap(spapr, |
1929 | SPAPR_CAP_CCF_ASSIST); | |
c59704b2 SJS |
1930 | |
1931 | switch (safe_cache) { | |
1932 | case SPAPR_CAP_WORKAROUND: | |
1933 | characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; | |
1934 | characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; | |
1935 | characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; | |
1936 | behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; | |
1937 | break; | |
1938 | case SPAPR_CAP_FIXED: | |
1939 | break; | |
1940 | default: /* broken */ | |
1941 | assert(safe_cache == SPAPR_CAP_BROKEN); | |
1942 | behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; | |
1943 | break; | |
1944 | } | |
1945 | ||
1946 | switch (safe_bounds_check) { | |
1947 | case SPAPR_CAP_WORKAROUND: | |
1948 | characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; | |
1949 | behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; | |
1950 | break; | |
1951 | case SPAPR_CAP_FIXED: | |
1952 | break; | |
1953 | default: /* broken */ | |
1954 | assert(safe_bounds_check == SPAPR_CAP_BROKEN); | |
1955 | behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; | |
1956 | break; | |
1957 | } | |
1958 | ||
1959 | switch (safe_indirect_branch) { | |
399b2896 SJS |
1960 | case SPAPR_CAP_FIXED_NA: |
1961 | break; | |
c76c0d30 SJS |
1962 | case SPAPR_CAP_FIXED_CCD: |
1963 | characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; | |
1964 | break; | |
1965 | case SPAPR_CAP_FIXED_IBS: | |
c59704b2 | 1966 | characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; |
fa86f592 | 1967 | break; |
399b2896 SJS |
1968 | case SPAPR_CAP_WORKAROUND: |
1969 | behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; | |
8ff43ee4 SJS |
1970 | if (count_cache_flush_assist) { |
1971 | characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; | |
1972 | } | |
399b2896 | 1973 | break; |
c59704b2 SJS |
1974 | default: /* broken */ |
1975 | assert(safe_indirect_branch == SPAPR_CAP_BROKEN); | |
1976 | break; | |
1977 | } | |
1978 | ||
1979 | args[0] = characteristics; | |
1980 | args[1] = behaviour; | |
fea35ca4 AK |
1981 | return H_SUCCESS; |
1982 | } | |
1983 | ||
ce2918cb | 1984 | static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, |
fea35ca4 AK |
1985 | target_ulong opcode, target_ulong *args) |
1986 | { | |
1987 | target_ulong dt = ppc64_phys_to_real(args[0]); | |
1988 | struct fdt_header hdr = { 0 }; | |
1989 | unsigned cb; | |
ce2918cb | 1990 | SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
fea35ca4 AK |
1991 | void *fdt; |
1992 | ||
1993 | cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); | |
1994 | cb = fdt32_to_cpu(hdr.totalsize); | |
1995 | ||
1996 | if (!smc->update_dt_enabled) { | |
1997 | return H_SUCCESS; | |
1998 | } | |
1999 | ||
2000 | /* Check that the fdt did not grow out of proportion */ | |
2001 | if (cb > spapr->fdt_initial_size * 2) { | |
2002 | trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, | |
2003 | fdt32_to_cpu(hdr.magic)); | |
2004 | return H_PARAMETER; | |
2005 | } | |
2006 | ||
2007 | fdt = g_malloc0(cb); | |
2008 | cpu_physical_memory_read(dt, fdt, cb); | |
2009 | ||
2010 | /* Check the fdt consistency */ | |
2011 | if (fdt_check_full(fdt, cb)) { | |
2012 | trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, | |
2013 | fdt32_to_cpu(hdr.magic)); | |
2014 | return H_PARAMETER; | |
2015 | } | |
2016 | ||
2017 | g_free(spapr->fdt_blob); | |
2018 | spapr->fdt_size = cb; | |
2019 | spapr->fdt_blob = fdt; | |
2020 | trace_spapr_update_dt(cb); | |
c59704b2 SJS |
2021 | |
2022 | return H_SUCCESS; | |
2023 | } | |
2024 | ||
7d7ba3fe DG |
2025 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
2026 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; | |
0fb6bd07 | 2027 | static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; |
9fdf0c29 DG |
2028 | |
2029 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) | |
2030 | { | |
39ac8455 DG |
2031 | spapr_hcall_fn *slot; |
2032 | ||
2033 | if (opcode <= MAX_HCALL_OPCODE) { | |
2034 | assert((opcode & 0x3) == 0); | |
9fdf0c29 | 2035 | |
39ac8455 | 2036 | slot = &papr_hypercall_table[opcode / 4]; |
0fb6bd07 MR |
2037 | } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { |
2038 | /* we only have SVM-related hcall numbers assigned in multiples of 4 */ | |
2039 | assert((opcode & 0x3) == 0); | |
2040 | ||
2041 | slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; | |
39ac8455 DG |
2042 | } else { |
2043 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); | |
9fdf0c29 | 2044 | |
39ac8455 DG |
2045 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
2046 | } | |
9fdf0c29 | 2047 | |
c89d5299 | 2048 | assert(!(*slot)); |
39ac8455 | 2049 | *slot = fn; |
9fdf0c29 DG |
2050 | } |
2051 | ||
aa100fa4 | 2052 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
9fdf0c29 DG |
2053 | target_ulong *args) |
2054 | { | |
ce2918cb | 2055 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
28e02042 | 2056 | |
9fdf0c29 DG |
2057 | if ((opcode <= MAX_HCALL_OPCODE) |
2058 | && ((opcode & 0x3) == 0)) { | |
39ac8455 DG |
2059 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
2060 | ||
0fb6bd07 MR |
2061 | if (fn) { |
2062 | return fn(cpu, spapr, opcode, args); | |
2063 | } | |
2064 | } else if ((opcode >= SVM_HCALL_BASE) && | |
2065 | (opcode <= SVM_HCALL_MAX)) { | |
2066 | spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; | |
2067 | ||
39ac8455 | 2068 | if (fn) { |
b13ce26d | 2069 | return fn(cpu, spapr, opcode, args); |
39ac8455 DG |
2070 | } |
2071 | } else if ((opcode >= KVMPPC_HCALL_BASE) && | |
2072 | (opcode <= KVMPPC_HCALL_MAX)) { | |
2073 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
2074 | |
2075 | if (fn) { | |
b13ce26d | 2076 | return fn(cpu, spapr, opcode, args); |
9fdf0c29 DG |
2077 | } |
2078 | } | |
2079 | ||
aaf87c66 TH |
2080 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", |
2081 | opcode); | |
9fdf0c29 DG |
2082 | return H_FUNCTION; |
2083 | } | |
f43e3525 | 2084 | |
83f7d43a | 2085 | static void hypercall_register_types(void) |
f43e3525 DG |
2086 | { |
2087 | /* hcall-pft */ | |
2088 | spapr_register_hypercall(H_ENTER, h_enter); | |
2089 | spapr_register_hypercall(H_REMOVE, h_remove); | |
2090 | spapr_register_hypercall(H_PROTECT, h_protect); | |
6bbd5dde | 2091 | spapr_register_hypercall(H_READ, h_read); |
39ac8455 | 2092 | |
a3d0abae DG |
2093 | /* hcall-bulk */ |
2094 | spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); | |
2095 | ||
30f4b05b DG |
2096 | /* hcall-hpt-resize */ |
2097 | spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); | |
2098 | spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); | |
2099 | ||
ed120055 DG |
2100 | /* hcall-splpar */ |
2101 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); | |
2102 | spapr_register_hypercall(H_CEDE, h_cede); | |
e8ce0e40 | 2103 | spapr_register_hypercall(H_CONFER, h_confer); |
3a6e6224 NP |
2104 | spapr_register_hypercall(H_PROD, h_prod); |
2105 | ||
10741314 NP |
2106 | /* hcall-join */ |
2107 | spapr_register_hypercall(H_JOIN, h_join); | |
2108 | ||
1c7ad77e | 2109 | spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); |
ed120055 | 2110 | |
423576f7 TH |
2111 | /* processor register resource access h-calls */ |
2112 | spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); | |
af08a58f | 2113 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
e49ff266 | 2114 | spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); |
3240dd9a | 2115 | spapr_register_hypercall(H_PAGE_INIT, h_page_init); |
423576f7 TH |
2116 | spapr_register_hypercall(H_SET_MODE, h_set_mode); |
2117 | ||
d77a98b0 SJS |
2118 | /* In Memory Table MMU h-calls */ |
2119 | spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); | |
2120 | spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); | |
2121 | spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); | |
2122 | ||
c59704b2 SJS |
2123 | /* hcall-get-cpu-characteristics */ |
2124 | spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, | |
2125 | h_get_cpu_characteristics); | |
2126 | ||
827200a2 DG |
2127 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate |
2128 | * here between the "CI" and the "CACHE" variants, they will use whatever | |
2129 | * mapping attributes qemu is using. When using KVM, the kernel will | |
2130 | * enforce the attributes more strongly | |
2131 | */ | |
2132 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); | |
2133 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); | |
2134 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); | |
2135 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); | |
2136 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); | |
2137 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); | |
c73e3771 | 2138 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
827200a2 | 2139 | |
39ac8455 DG |
2140 | /* qemu/KVM-PPC specific hcalls */ |
2141 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); | |
42561bf2 | 2142 | |
2a6593cb AK |
2143 | /* ibm,client-architecture-support support */ |
2144 | spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); | |
c24ba3d0 | 2145 | |
fea35ca4 AK |
2146 | spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); |
2147 | ||
c24ba3d0 LV |
2148 | /* Virtual Processor Home Node */ |
2149 | spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY, | |
2150 | h_home_node_associativity); | |
f43e3525 | 2151 | } |
83f7d43a AF |
2152 | |
2153 | type_init(hypercall_register_types) |