[thirdparty/qemu.git] / hw / scsi / esp-pci.c

/*
 * QEMU ESP/NCR53C9x emulation
 *
 * Copyright (c) 2005-2006 Fabrice Bellard
 * Copyright (c) 2012 Herve Poussineau
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/nvram/eeprom93xx.h"
#include "hw/scsi/esp.h"
#include "trace.h"
#include "qapi/error.h"
#include "qemu/log.h"

#define TYPE_AM53C974_DEVICE "am53c974"

#define PCI_ESP(obj) \
    OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)

#define DMA_CMD   0x0
#define DMA_STC   0x1
#define DMA_SPA   0x2
#define DMA_WBC   0x3
#define DMA_WAC   0x4
#define DMA_STAT  0x5
#define DMA_SMDLA 0x6
#define DMA_WMAC  0x7

#define DMA_CMD_MASK   0x03
#define DMA_CMD_DIAG   0x04
#define DMA_CMD_MDL    0x10
#define DMA_CMD_INTE_P 0x20
#define DMA_CMD_INTE_D 0x40
#define DMA_CMD_DIR    0x80

#define DMA_STAT_PWDN    0x01
#define DMA_STAT_ERROR   0x02
#define DMA_STAT_ABORT   0x04
#define DMA_STAT_DONE    0x08
#define DMA_STAT_SCSIINT 0x10
#define DMA_STAT_BCMBLT  0x20

#define SBAC_STATUS 0x1000

typedef struct PCIESPState {
    /*< private >*/
    PCIDevice parent_obj;
    /*< public >*/

    MemoryRegion io;
    uint32_t dma_regs[8];
    uint32_t sbac;
    ESPState esp;
} PCIESPState;

static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_idle(val);
    esp_dma_enable(&pci->esp, 0, 0);
}

static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_blast(val);
    qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
}

static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_abort(val);
    if (pci->esp.current_req) {
        scsi_req_cancel(pci->esp.current_req);
    }
}

static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_start(val);

    pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
    pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
    pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];

    pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
                               | DMA_STAT_DONE | DMA_STAT_ABORT
                               | DMA_STAT_ERROR | DMA_STAT_PWDN);

    esp_dma_enable(&pci->esp, 0, 1);
}

static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
{
    trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
    switch (saddr) {
    case DMA_CMD:
        pci->dma_regs[saddr] = val;
        switch (val & DMA_CMD_MASK) {
        case 0x0: /* IDLE */
            esp_pci_handle_idle(pci, val);
            break;
        case 0x1: /* BLAST */
            esp_pci_handle_blast(pci, val);
            break;
        case 0x2: /* ABORT */
            esp_pci_handle_abort(pci, val);
            break;
        case 0x3: /* START */
            esp_pci_handle_start(pci, val);
            break;
        default: /* can't happen */
            abort();
        }
        break;
    case DMA_STC:
    case DMA_SPA:
    case DMA_SMDLA:
        pci->dma_regs[saddr] = val;
        break;
    case DMA_STAT:
        if (!(pci->sbac & SBAC_STATUS)) {
            /* clear some bits on write */
            uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
            pci->dma_regs[DMA_STAT] &= ~(val & mask);
        }
        break;
    default:
        trace_esp_pci_error_invalid_write_dma(val, saddr);
        return;
    }
}

static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
{
    uint32_t val;

    val = pci->dma_regs[saddr];
    if (saddr == DMA_STAT) {
        if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
            val |= DMA_STAT_SCSIINT;
        }
        if (pci->sbac & SBAC_STATUS) {
            pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
                                         DMA_STAT_DONE);
        }
    }

    trace_esp_pci_dma_read(saddr, val);
    return val;
}

static void esp_pci_io_write(void *opaque, hwaddr addr,
                             uint64_t val, unsigned int size)
{
    PCIESPState *pci = opaque;

    if (size < 4 || addr & 3) {
        /* need to upgrade request: we only support 4-bytes accesses */
        uint32_t current = 0, mask;
        int shift;

        if (addr < 0x40) {
            current = pci->esp.wregs[addr >> 2];
        } else if (addr < 0x60) {
            current = pci->dma_regs[(addr - 0x40) >> 2];
        } else if (addr < 0x74) {
            current = pci->sbac;
        }

        shift = (4 - size) * 8;
        mask = (~(uint32_t)0 << shift) >> shift;

        shift = ((4 - (addr & 3)) & 3) * 8;
        val <<= shift;
        val |= current & ~(mask << shift);
        addr &= ~3;
        size = 4;
    }

    if (addr < 0x40) {
        /* SCSI core reg */
        esp_reg_write(&pci->esp, addr >> 2, val);
    } else if (addr < 0x60) {
        /* PCI DMA CCB */
        esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
    } else if (addr == 0x70) {
        /* DMA SCSI Bus and control */
        trace_esp_pci_sbac_write(pci->sbac, val);
        pci->sbac = val;
    } else {
        trace_esp_pci_error_invalid_write((int)addr);
    }
}

static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
                                unsigned int size)
{
    PCIESPState *pci = opaque;
    uint32_t ret;

    if (addr < 0x40) {
        /* SCSI core reg */
        ret = esp_reg_read(&pci->esp, addr >> 2);
    } else if (addr < 0x60) {
        /* PCI DMA CCB */
        ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
    } else if (addr == 0x70) {
        /* DMA SCSI Bus and control */
        trace_esp_pci_sbac_read(pci->sbac);
        ret = pci->sbac;
    } else {
        /* Invalid region */
        trace_esp_pci_error_invalid_read((int)addr);
        ret = 0;
    }

    /* give only requested data */
    ret >>= (addr & 3) * 8;
    ret &= ~(~(uint64_t)0 << (8 * size));

    return ret;
}

static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
                                  DMADirection dir)
{
    dma_addr_t addr;
    DMADirection expected_dir;

    if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
        expected_dir = DMA_DIRECTION_FROM_DEVICE;
    } else {
        expected_dir = DMA_DIRECTION_TO_DEVICE;
    }

    if (dir != expected_dir) {
        trace_esp_pci_error_invalid_dma_direction();
        return;
    }

    if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
        qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
    }

    addr = pci->dma_regs[DMA_SPA];
    if (pci->dma_regs[DMA_WBC] < len) {
        len = pci->dma_regs[DMA_WBC];
    }

    pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);

    /* update status registers */
    pci->dma_regs[DMA_WBC] -= len;
    pci->dma_regs[DMA_WAC] += len;
    if (pci->dma_regs[DMA_WBC] == 0) {
        pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
    }
}

static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
{
    PCIESPState *pci = opaque;
    esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
}

static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
{
    PCIESPState *pci = opaque;
    esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
}

static const MemoryRegionOps esp_pci_io_ops = {
    .read = esp_pci_io_read,
    .write = esp_pci_io_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 4,
    },
};

static void esp_pci_hard_reset(DeviceState *dev)
{
    PCIESPState *pci = PCI_ESP(dev);
    esp_hard_reset(&pci->esp);
    pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
                              | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
    pci->dma_regs[DMA_WBC] &= ~0xffff;
    pci->dma_regs[DMA_WAC] = 0xffffffff;
    pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
                               | DMA_STAT_DONE | DMA_STAT_ABORT
                               | DMA_STAT_ERROR);
    pci->dma_regs[DMA_WMAC] = 0xfffffffd;
}

static const VMStateDescription vmstate_esp_pci_scsi = {
    .name = "pciespscsi",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
        VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
        VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
        VMSTATE_END_OF_LIST()
    }
};

static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
                                     size_t resid)
{
    ESPState *s = req->hba_private;
    PCIESPState *pci = container_of(s, PCIESPState, esp);

    esp_command_complete(req, status, resid);
    pci->dma_regs[DMA_WBC] = 0;
    pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
}

static const struct SCSIBusInfo esp_pci_scsi_info = {
    .tcq = false,
    .max_target = ESP_MAX_DEVS,
    .max_lun = 7,

    .transfer_data = esp_transfer_data,
    .complete = esp_pci_command_complete,
    .cancel = esp_request_cancelled,
};

static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
{
    PCIESPState *pci = PCI_ESP(dev);
    DeviceState *d = DEVICE(dev);
    ESPState *s = &pci->esp;
    uint8_t *pci_conf;

    pci_conf = dev->config;

    /* Interrupt pin A */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01;

    s->dma_memory_read = esp_pci_dma_memory_read;
    s->dma_memory_write = esp_pci_dma_memory_write;
    s->dma_opaque = pci;
    s->chip_id = TCHI_AM53C974;
    memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
                          "esp-io", 0x80);

    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
    s->irq = pci_allocate_irq(dev);

    scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
    if (!d->hotplugged) {
        scsi_bus_legacy_handle_cmdline(&s->bus, errp);
    }
}

static void esp_pci_scsi_uninit(PCIDevice *d)
{
    PCIESPState *pci = PCI_ESP(d);

    qemu_free_irq(pci->esp.irq);
}

static void esp_pci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = esp_pci_scsi_realize;
    k->exit = esp_pci_scsi_uninit;
    k->vendor_id = PCI_VENDOR_ID_AMD;
    k->device_id = PCI_DEVICE_ID_AMD_SCSI;
    k->revision = 0x10;
    k->class_id = PCI_CLASS_STORAGE_SCSI;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
    dc->reset = esp_pci_hard_reset;
    dc->vmsd = &vmstate_esp_pci_scsi;
}

static const TypeInfo esp_pci_info = {
    .name = TYPE_AM53C974_DEVICE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIESPState),
    .class_init = esp_pci_class_init,
};

typedef struct {
    PCIESPState pci;
    eeprom_t *eeprom;
} DC390State;

#define TYPE_DC390_DEVICE "dc390"
#define DC390(obj) \
    OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)

#define EE_ADAPT_SCSI_ID 64
#define EE_MODE2         65
#define EE_DELAY         66
#define EE_TAG_CMD_NUM   67
#define EE_ADAPT_OPTIONS 68
#define EE_BOOT_SCSI_ID  69
#define EE_BOOT_SCSI_LUN 70
#define EE_CHKSUM1       126
#define EE_CHKSUM2       127

#define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
#define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
#define EE_ADAPT_OPTION_INT13           0x04
#define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08


static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
{
    DC390State *pci = DC390(dev);
    uint32_t val;

    val = pci_default_read_config(dev, addr, l);

    if (addr == 0x00 && l == 1) {
        /* First byte of address space is AND-ed with EEPROM DO line */
        if (!eeprom93xx_read(pci->eeprom)) {
            val &= ~0xff;
        }
    }

    return val;
}

static void dc390_write_config(PCIDevice *dev,
                               uint32_t addr, uint32_t val, int l)
{
    DC390State *pci = DC390(dev);
    if (addr == 0x80) {
        /* EEPROM write */
        int eesk = val & 0x80 ? 1 : 0;
        int eedi = val & 0x40 ? 1 : 0;
        eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
    } else if (addr == 0xc0) {
        /* EEPROM CS low */
        eeprom93xx_write(pci->eeprom, 0, 0, 0);
    } else {
        pci_default_write_config(dev, addr, val, l);
    }
}

static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
{
    DC390State *pci = DC390(dev);
    Error *err = NULL;
    uint8_t *contents;
    uint16_t chksum = 0;
    int i;

    /* init base class */
    esp_pci_scsi_realize(dev, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    /* EEPROM */
    pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);

    /* set default eeprom values */
    contents = (uint8_t *)eeprom93xx_data(pci->eeprom);

    for (i = 0; i < 16; i++) {
        contents[i * 2] = 0x57;
        contents[i * 2 + 1] = 0x00;
    }
    contents[EE_ADAPT_SCSI_ID] = 7;
    contents[EE_MODE2] = 0x0f;
    contents[EE_TAG_CMD_NUM] = 0x04;
    contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
                               | EE_ADAPT_OPTION_BOOT_FROM_CDROM
                               | EE_ADAPT_OPTION_INT13;

    /* update eeprom checksum */
    for (i = 0; i < EE_CHKSUM1; i += 2) {
        chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
    }
    chksum = 0x1234 - chksum;
    contents[EE_CHKSUM1] = chksum & 0xff;
    contents[EE_CHKSUM2] = chksum >> 8;
}

static void dc390_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = dc390_scsi_realize;
    k->config_read = dc390_read_config;
    k->config_write = dc390_write_config;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->desc = "Tekram DC-390 SCSI adapter";
}

static const TypeInfo dc390_info = {
    .name = "dc390",
    .parent = TYPE_AM53C974_DEVICE,
    .instance_size = sizeof(DC390State),
    .class_init = dc390_class_init,
};

static void esp_pci_register_types(void)
{
    type_register_static(&esp_pci_info);
    type_register_static(&dc390_info);
}

type_init(esp_pci_register_types)
Commit	Line	Data
aebcf56f HP	1	/*
	2	* QEMU ESP/NCR53C9x emulation
	3	*
	4	* Copyright (c) 2005-2006 Fabrice Bellard
	5	* Copyright (c) 2012 Herve Poussineau
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
a4ab4792	26	#include "qemu/osdep.h"
83c9f4ca	27	#include "hw/pci/pci.h"
0d09e41a PB	28	#include "hw/nvram/eeprom93xx.h"
0d09e41a PB	29	#include "hw/scsi/esp.h"
aebcf56f	30	#include "trace.h"
da34e65c	31	#include "qapi/error.h"
1de7afc9	32	#include "qemu/log.h"
aebcf56f	33
cea936b1 HP	34	#define TYPE_AM53C974_DEVICE "am53c974"
cea936b1 HP	35
3a15effe PC	36	#define PCI_ESP(obj) \
	37	OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
	38
aebcf56f HP	39	#define DMA_CMD 0x0
	40	#define DMA_STC 0x1
	41	#define DMA_SPA 0x2
	42	#define DMA_WBC 0x3
	43	#define DMA_WAC 0x4
	44	#define DMA_STAT 0x5
	45	#define DMA_SMDLA 0x6
	46	#define DMA_WMAC 0x7
	47
	48	#define DMA_CMD_MASK 0x03
	49	#define DMA_CMD_DIAG 0x04
	50	#define DMA_CMD_MDL 0x10
	51	#define DMA_CMD_INTE_P 0x20
	52	#define DMA_CMD_INTE_D 0x40
	53	#define DMA_CMD_DIR 0x80
	54
	55	#define DMA_STAT_PWDN 0x01
	56	#define DMA_STAT_ERROR 0x02
	57	#define DMA_STAT_ABORT 0x04
	58	#define DMA_STAT_DONE 0x08
	59	#define DMA_STAT_SCSIINT 0x10
	60	#define DMA_STAT_BCMBLT 0x20
	61
	62	#define SBAC_STATUS 0x1000
	63
	64	typedef struct PCIESPState {
4e5dcc77 AF	65	/< private >/
	66	PCIDevice parent_obj;
	67	/< public >/
	68
aebcf56f HP	69	MemoryRegion io;
	70	uint32_t dma_regs[8];
	71	uint32_t sbac;
	72	ESPState esp;
	73	} PCIESPState;
	74
	75	static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
	76	{
	77	trace_esp_pci_dma_idle(val);
	78	esp_dma_enable(&pci->esp, 0, 0);
	79	}
	80
	81	static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
	82	{
	83	trace_esp_pci_dma_blast(val);
	84	qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
	85	}
	86
	87	static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
	88	{
	89	trace_esp_pci_dma_abort(val);
	90	if (pci->esp.current_req) {
	91	scsi_req_cancel(pci->esp.current_req);
	92	}
	93	}
	94
	95	static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
	96	{
	97	trace_esp_pci_dma_start(val);
	98
	99	pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
	100	pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
	101	pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
	102
	103	pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT \| DMA_STAT_SCSIINT
	104	\| DMA_STAT_DONE \| DMA_STAT_ABORT
	105	\| DMA_STAT_ERROR \| DMA_STAT_PWDN);
	106
	107	esp_dma_enable(&pci->esp, 0, 1);
	108	}
	109
	110	static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
	111	{
	112	trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
	113	switch (saddr) {
	114	case DMA_CMD:
	115	pci->dma_regs[saddr] = val;
	116	switch (val & DMA_CMD_MASK) {
	117	case 0x0: /* IDLE */
	118	esp_pci_handle_idle(pci, val);
	119	break;
	120	case 0x1: /* BLAST */
	121	esp_pci_handle_blast(pci, val);
	122	break;
	123	case 0x2: /* ABORT */
	124	esp_pci_handle_abort(pci, val);
	125	break;
	126	case 0x3: /* START */
	127	esp_pci_handle_start(pci, val);
	128	break;
	129	default: /* can't happen */
	130	abort();
	131	}
	132	break;
133	case DMA_STC:
134	case DMA_SPA:
135	case DMA_SMDLA:
136	pci->dma_regs[saddr] = val;
137	break;
138	case DMA_STAT:
139	if (!(pci->sbac & SBAC_STATUS)) {
140	/* clear some bits on write */
141	uint32_t mask = DMA_STAT_ERROR \| DMA_STAT_ABORT \| DMA_STAT_DONE;
142	pci->dma_regs[DMA_STAT] &= ~(val & mask);
143	}
144	break;
145	default:
146	trace_esp_pci_error_invalid_write_dma(val, saddr);
147	return;
148	}
149	}
150
151	static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
152	{
153	uint32_t val;
154
155	val = pci->dma_regs[saddr];
156	if (saddr == DMA_STAT) {
157	if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
158	val \|= DMA_STAT_SCSIINT;
159	}
160	if (pci->sbac & SBAC_STATUS) {
161	pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR \| DMA_STAT_ABORT \|
162	DMA_STAT_DONE);
163	}
164	}
165
166	trace_esp_pci_dma_read(saddr, val);
167	return val;
168	}
169
a8170e5e	170	static void esp_pci_io_write(void *opaque, hwaddr addr,
aebcf56f HP	171	uint64_t val, unsigned int size)
	172	{
	173	PCIESPState *pci = opaque;
	174
	175	if (size < 4 \|\| addr & 3) {
	176	/* need to upgrade request: we only support 4-bytes accesses */
	177	uint32_t current = 0, mask;
	178	int shift;
	179
	180	if (addr < 0x40) {
	181	current = pci->esp.wregs[addr >> 2];
	182	} else if (addr < 0x60) {
	183	current = pci->dma_regs[(addr - 0x40) >> 2];
	184	} else if (addr < 0x74) {
	185	current = pci->sbac;
	186	}
	187
	188	shift = (4 - size) * 8;
	189	mask = (~(uint32_t)0 << shift) >> shift;
	190
	191	shift = ((4 - (addr & 3)) & 3) * 8;
	192	val <<= shift;
	193	val \|= current & ~(mask << shift);
	194	addr &= ~3;
	195	size = 4;
	196	}
	197
	198	if (addr < 0x40) {
	199	/* SCSI core reg */
	200	esp_reg_write(&pci->esp, addr >> 2, val);
	201	} else if (addr < 0x60) {
	202	/* PCI DMA CCB */
	203	esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
	204	} else if (addr == 0x70) {
	205	/* DMA SCSI Bus and control */
	206	trace_esp_pci_sbac_write(pci->sbac, val);
	207	pci->sbac = val;
	208	} else {
	209	trace_esp_pci_error_invalid_write((int)addr);
	210	}
	211	}
	212
a8170e5e	213	static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
aebcf56f HP	214	unsigned int size)
	215	{
	216	PCIESPState *pci = opaque;
	217	uint32_t ret;
	218
	219	if (addr < 0x40) {
	220	/* SCSI core reg */
	221	ret = esp_reg_read(&pci->esp, addr >> 2);
	222	} else if (addr < 0x60) {
	223	/* PCI DMA CCB */
	224	ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
	225	} else if (addr == 0x70) {
	226	/* DMA SCSI Bus and control */
	227	trace_esp_pci_sbac_read(pci->sbac);
	228	ret = pci->sbac;
	229	} else {
	230	/* Invalid region */
	231	trace_esp_pci_error_invalid_read((int)addr);
	232	ret = 0;
	233	}
	234
	235	/* give only requested data */
	236	ret >>= (addr & 3) * 8;
	237	ret &= ~(~(uint64_t)0 << (8 * size));
	238
	239	return ret;
	240	}
	241
	242	static void esp_pci_dma_memory_rw(PCIESPState pci, uint8_t buf, int len,
	243	DMADirection dir)
	244	{
	245	dma_addr_t addr;
	246	DMADirection expected_dir;
	247
	248	if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
	249	expected_dir = DMA_DIRECTION_FROM_DEVICE;
	250	} else {
	251	expected_dir = DMA_DIRECTION_TO_DEVICE;
	252	}
	253
	254	if (dir != expected_dir) {
	255	trace_esp_pci_error_invalid_dma_direction();
	256	return;
	257	}
	258
	259	if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
	260	qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
	261	}
	262
	263	addr = pci->dma_regs[DMA_SPA];
	264	if (pci->dma_regs[DMA_WBC] < len) {
	265	len = pci->dma_regs[DMA_WBC];
	266	}
	267
4e5dcc77	268	pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
aebcf56f HP	269
	270	/* update status registers */
	271	pci->dma_regs[DMA_WBC] -= len;
	272	pci->dma_regs[DMA_WAC] += len;
25aaa2c5	273	if (pci->dma_regs[DMA_WBC] == 0) {
c3543fb5	274	pci->dma_regs[DMA_STAT] \|= DMA_STAT_DONE;
25aaa2c5	275	}
aebcf56f HP	276	}
	277
	278	static void esp_pci_dma_memory_read(void opaque, uint8_t buf, int len)
	279	{
	280	PCIESPState *pci = opaque;
	281	esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
	282	}
	283
	284	static void esp_pci_dma_memory_write(void opaque, uint8_t buf, int len)
	285	{
	286	PCIESPState *pci = opaque;
	287	esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
	288	}
	289
	290	static const MemoryRegionOps esp_pci_io_ops = {
	291	.read = esp_pci_io_read,
	292	.write = esp_pci_io_write,
	293	.endianness = DEVICE_LITTLE_ENDIAN,
	294	.impl = {
	295	.min_access_size = 1,
	296	.max_access_size = 4,
	297	},
	298	};
	299
	300	static void esp_pci_hard_reset(DeviceState *dev)
	301	{
3a15effe	302	PCIESPState *pci = PCI_ESP(dev);
aebcf56f HP	303	esp_hard_reset(&pci->esp);
	304	pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR \| DMA_CMD_INTE_D \| DMA_CMD_INTE_P
	305	\| DMA_CMD_MDL \| DMA_CMD_DIAG \| DMA_CMD_MASK);
	306	pci->dma_regs[DMA_WBC] &= ~0xffff;
	307	pci->dma_regs[DMA_WAC] = 0xffffffff;
	308	pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT \| DMA_STAT_SCSIINT
	309	\| DMA_STAT_DONE \| DMA_STAT_ABORT
	310	\| DMA_STAT_ERROR);
	311	pci->dma_regs[DMA_WMAC] = 0xfffffffd;
	312	}
	313
	314	static const VMStateDescription vmstate_esp_pci_scsi = {
	315	.name = "pciespscsi",
	316	.version_id = 0,
	317	.minimum_version_id = 0,
aebcf56f	318	.fields = (VMStateField[]) {
4e5dcc77	319	VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
aebcf56f HP	320	VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
	321	VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
	322	VMSTATE_END_OF_LIST()
	323	}
	324	};
	325
	326	static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
	327	size_t resid)
	328	{
	329	ESPState *s = req->hba_private;
	330	PCIESPState *pci = container_of(s, PCIESPState, esp);
	331
	332	esp_command_complete(req, status, resid);
	333	pci->dma_regs[DMA_WBC] = 0;
	334	pci->dma_regs[DMA_STAT] \|= DMA_STAT_DONE;
	335	}
	336
	337	static const struct SCSIBusInfo esp_pci_scsi_info = {
	338	.tcq = false,
	339	.max_target = ESP_MAX_DEVS,
	340	.max_lun = 7,
	341
	342	.transfer_data = esp_transfer_data,
	343	.complete = esp_pci_command_complete,
	344	.cancel = esp_request_cancelled,
	345	};
	346
ae071cc8	347	static void esp_pci_scsi_realize(PCIDevice dev, Error *errp)
aebcf56f	348	{
3a15effe PC	349	PCIESPState *pci = PCI_ESP(dev);
3a15effe PC	350	DeviceState *d = DEVICE(dev);
aebcf56f HP	351	ESPState *s = &pci->esp;
	352	uint8_t *pci_conf;
	353
4e5dcc77	354	pci_conf = dev->config;
aebcf56f HP	355
	356	/* Interrupt pin A */
	357	pci_conf[PCI_INTERRUPT_PIN] = 0x01;
	358
	359	s->dma_memory_read = esp_pci_dma_memory_read;
	360	s->dma_memory_write = esp_pci_dma_memory_write;
	361	s->dma_opaque = pci;
	362	s->chip_id = TCHI_AM53C974;
29776739 PB	363	memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
29776739 PB	364	"esp-io", 0x80);
aebcf56f	365
4e5dcc77	366	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
9e64f8a3	367	s->irq = pci_allocate_irq(dev);
aebcf56f	368
b1187b51	369	scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
3a15effe	370	if (!d->hotplugged) {
ae071cc8	371	scsi_bus_legacy_handle_cmdline(&s->bus, errp);
aebcf56f	372	}
aebcf56f HP	373	}
	374
	375	static void esp_pci_scsi_uninit(PCIDevice *d)
	376	{
3a15effe	377	PCIESPState *pci = PCI_ESP(d);
aebcf56f	378
9e64f8a3	379	qemu_free_irq(pci->esp.irq);
aebcf56f HP	380	}
	381
	382	static void esp_pci_class_init(ObjectClass klass, void data)
	383	{
	384	DeviceClass *dc = DEVICE_CLASS(klass);
	385	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	386
ae071cc8	387	k->realize = esp_pci_scsi_realize;
aebcf56f HP	388	k->exit = esp_pci_scsi_uninit;
	389	k->vendor_id = PCI_VENDOR_ID_AMD;
	390	k->device_id = PCI_DEVICE_ID_AMD_SCSI;
	391	k->revision = 0x10;
	392	k->class_id = PCI_CLASS_STORAGE_SCSI;
125ee0ed	393	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
aebcf56f HP	394	dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
	395	dc->reset = esp_pci_hard_reset;
	396	dc->vmsd = &vmstate_esp_pci_scsi;
	397	}
	398
	399	static const TypeInfo esp_pci_info = {
cea936b1	400	.name = TYPE_AM53C974_DEVICE,
aebcf56f HP	401	.parent = TYPE_PCI_DEVICE,
	402	.instance_size = sizeof(PCIESPState),
	403	.class_init = esp_pci_class_init,
	404	};
	405
cea936b1 HP	406	typedef struct {
	407	PCIESPState pci;
	408	eeprom_t *eeprom;
	409	} DC390State;
	410
	411	#define TYPE_DC390_DEVICE "dc390"
	412	#define DC390(obj) \
	413	OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
	414
	415	#define EE_ADAPT_SCSI_ID 64
	416	#define EE_MODE2 65
	417	#define EE_DELAY 66
	418	#define EE_TAG_CMD_NUM 67
	419	#define EE_ADAPT_OPTIONS 68
	420	#define EE_BOOT_SCSI_ID 69
	421	#define EE_BOOT_SCSI_LUN 70
	422	#define EE_CHKSUM1 126
	423	#define EE_CHKSUM2 127
	424
	425	#define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01
	426	#define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
	427	#define EE_ADAPT_OPTION_INT13 0x04
	428	#define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
	429
	430
	431	static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
	432	{
	433	DC390State *pci = DC390(dev);
	434	uint32_t val;
	435
	436	val = pci_default_read_config(dev, addr, l);
	437
	438	if (addr == 0x00 && l == 1) {
	439	/* First byte of address space is AND-ed with EEPROM DO line */
	440	if (!eeprom93xx_read(pci->eeprom)) {
	441	val &= ~0xff;
	442	}
	443	}
	444
	445	return val;
	446	}
	447
	448	static void dc390_write_config(PCIDevice *dev,
	449	uint32_t addr, uint32_t val, int l)
	450	{
	451	DC390State *pci = DC390(dev);
	452	if (addr == 0x80) {
	453	/* EEPROM write */
	454	int eesk = val & 0x80 ? 1 : 0;
	455	int eedi = val & 0x40 ? 1 : 0;
	456	eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
	457	} else if (addr == 0xc0) {
	458	/* EEPROM CS low */
	459	eeprom93xx_write(pci->eeprom, 0, 0, 0);
	460	} else {
	461	pci_default_write_config(dev, addr, val, l);
	462	}
	463	}
	464
ae071cc8	465	static void dc390_scsi_realize(PCIDevice dev, Error *errp)
cea936b1 HP	466	{
cea936b1 HP	467	DC390State *pci = DC390(dev);
ae071cc8	468	Error *err = NULL;
cea936b1 HP	469	uint8_t *contents;
cea936b1 HP	470	uint16_t chksum = 0;
ae071cc8	471	int i;
cea936b1 HP	472
cea936b1 HP	473	/* init base class */
ae071cc8 MA	474	esp_pci_scsi_realize(dev, &err);
	475	if (err) {
	476	error_propagate(errp, err);
	477	return;
cea936b1 HP	478	}
	479
	480	/* EEPROM */
	481	pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
	482
	483	/* set default eeprom values */
	484	contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
	485
	486	for (i = 0; i < 16; i++) {
	487	contents[i * 2] = 0x57;
	488	contents[i * 2 + 1] = 0x00;
	489	}
	490	contents[EE_ADAPT_SCSI_ID] = 7;
	491	contents[EE_MODE2] = 0x0f;
	492	contents[EE_TAG_CMD_NUM] = 0x04;
	493	contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
	494	\| EE_ADAPT_OPTION_BOOT_FROM_CDROM
	495	\| EE_ADAPT_OPTION_INT13;
	496
	497	/* update eeprom checksum */
	498	for (i = 0; i < EE_CHKSUM1; i += 2) {
	499	chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
	500	}
	501	chksum = 0x1234 - chksum;
	502	contents[EE_CHKSUM1] = chksum & 0xff;
	503	contents[EE_CHKSUM2] = chksum >> 8;
cea936b1 HP	504	}
	505
	506	static void dc390_class_init(ObjectClass klass, void data)
	507	{
	508	DeviceClass *dc = DEVICE_CLASS(klass);
	509	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	510
ae071cc8	511	k->realize = dc390_scsi_realize;
cea936b1 HP	512	k->config_read = dc390_read_config;
cea936b1 HP	513	k->config_write = dc390_write_config;
125ee0ed	514	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
cea936b1 HP	515	dc->desc = "Tekram DC-390 SCSI adapter";
	516	}
	517
	518	static const TypeInfo dc390_info = {
	519	.name = "dc390",
	520	.parent = TYPE_AM53C974_DEVICE,
	521	.instance_size = sizeof(DC390State),
	522	.class_init = dc390_class_init,
	523	};
	524
aebcf56f HP	525	static void esp_pci_register_types(void)
	526	{
	527	type_register_static(&esp_pci_info);
cea936b1	528	type_register_static(&dc390_info);
aebcf56f HP	529	}
	530
	531	type_init(esp_pci_register_types)