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Commit | Line | Data |
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bb36d470 FB |
1 | /* |
2 | * USB UHCI controller emulation | |
5fafdf24 | 3 | * |
bb36d470 | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
54f254f9 AL |
6 | * Copyright (c) 2008 Max Krasnyansky |
7 | * Magor rewrite of the UHCI data structures parser and frame processor | |
8 | * Support for fully async operation and multiple outstanding transactions | |
9 | * | |
bb36d470 FB |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | */ | |
e532b2e0 | 28 | #include "qemu/osdep.h" |
f1ae32a1 GH |
29 | #include "hw/hw.h" |
30 | #include "hw/usb.h" | |
9a1d111e | 31 | #include "hw/usb/uhci-regs.h" |
a2cb15b0 | 32 | #include "hw/pci/pci.h" |
da34e65c | 33 | #include "qapi/error.h" |
1de7afc9 PB |
34 | #include "qemu/timer.h" |
35 | #include "qemu/iov.h" | |
9c17d615 | 36 | #include "sysemu/dma.h" |
50dcc0f8 | 37 | #include "trace.h" |
6a1751b7 | 38 | #include "qemu/main-loop.h" |
bb36d470 | 39 | |
bb36d470 FB |
40 | #define FRAME_TIMER_FREQ 1000 |
41 | ||
3200d108 | 42 | #define FRAME_MAX_LOOPS 256 |
bb36d470 | 43 | |
475443cf HG |
44 | /* Must be large enough to handle 10 frame delay for initial isoc requests */ |
45 | #define QH_VALID 32 | |
46 | ||
f8f48b69 HG |
47 | #define MAX_FRAMES_PER_TICK (QH_VALID / 2) |
48 | ||
bb36d470 FB |
49 | #define NB_PORTS 2 |
50 | ||
60e1b2a6 | 51 | enum { |
0cd178ca GH |
52 | TD_RESULT_STOP_FRAME = 10, |
53 | TD_RESULT_COMPLETE, | |
54 | TD_RESULT_NEXT_QH, | |
4efe4ef3 GH |
55 | TD_RESULT_ASYNC_START, |
56 | TD_RESULT_ASYNC_CONT, | |
60e1b2a6 GH |
57 | }; |
58 | ||
7b5a44c5 | 59 | typedef struct UHCIState UHCIState; |
f8af1e88 GH |
60 | typedef struct UHCIAsync UHCIAsync; |
61 | typedef struct UHCIQueue UHCIQueue; | |
2c2e8525 | 62 | typedef struct UHCIInfo UHCIInfo; |
8f3f90b0 | 63 | typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; |
2c2e8525 GH |
64 | |
65 | struct UHCIInfo { | |
66 | const char *name; | |
67 | uint16_t vendor_id; | |
68 | uint16_t device_id; | |
69 | uint8_t revision; | |
8f3f90b0 | 70 | uint8_t irq_pin; |
63216dc7 | 71 | void (*realize)(PCIDevice *dev, Error **errp); |
2c2e8525 GH |
72 | bool unplug; |
73 | }; | |
7b5a44c5 | 74 | |
8f3f90b0 GH |
75 | struct UHCIPCIDeviceClass { |
76 | PCIDeviceClass parent_class; | |
77 | UHCIInfo info; | |
78 | }; | |
79 | ||
54f254f9 AL |
80 | /* |
81 | * Pending async transaction. | |
82 | * 'packet' must be the first field because completion | |
83 | * handler does "(UHCIAsync *) pkt" cast. | |
84 | */ | |
f8af1e88 GH |
85 | |
86 | struct UHCIAsync { | |
54f254f9 | 87 | USBPacket packet; |
9822261c HG |
88 | uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ |
89 | uint8_t *buf; | |
f8af1e88 | 90 | UHCIQueue *queue; |
ddf6583f | 91 | QTAILQ_ENTRY(UHCIAsync) next; |
1f250cc7 | 92 | uint32_t td_addr; |
54f254f9 | 93 | uint8_t done; |
f8af1e88 GH |
94 | }; |
95 | ||
96 | struct UHCIQueue { | |
66a08cbe | 97 | uint32_t qh_addr; |
f8af1e88 GH |
98 | uint32_t token; |
99 | UHCIState *uhci; | |
11d15e40 | 100 | USBEndpoint *ep; |
f8af1e88 | 101 | QTAILQ_ENTRY(UHCIQueue) next; |
8928c9c4 | 102 | QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; |
f8af1e88 GH |
103 | int8_t valid; |
104 | }; | |
54f254f9 | 105 | |
bb36d470 FB |
106 | typedef struct UHCIPort { |
107 | USBPort port; | |
108 | uint16_t ctrl; | |
bb36d470 FB |
109 | } UHCIPort; |
110 | ||
7b5a44c5 | 111 | struct UHCIState { |
bb36d470 | 112 | PCIDevice dev; |
a03f66e4 | 113 | MemoryRegion io_bar; |
35e4977f | 114 | USBBus bus; /* Note unused when we're a companion controller */ |
bb36d470 FB |
115 | uint16_t cmd; /* cmd register */ |
116 | uint16_t status; | |
117 | uint16_t intr; /* interrupt enable register */ | |
118 | uint16_t frnum; /* frame number */ | |
119 | uint32_t fl_base_addr; /* frame list base address */ | |
120 | uint8_t sof_timing; | |
121 | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ | |
8e65b7c0 | 122 | int64_t expire_time; |
bb36d470 | 123 | QEMUTimer *frame_timer; |
9a16c595 | 124 | QEMUBH *bh; |
4aed20e2 | 125 | uint32_t frame_bytes; |
40141d12 | 126 | uint32_t frame_bandwidth; |
88793816 | 127 | bool completions_only; |
bb36d470 | 128 | UHCIPort ports[NB_PORTS]; |
4d611c9a PB |
129 | |
130 | /* Interrupts that should be raised at the end of the current frame. */ | |
131 | uint32_t pending_int_mask; | |
54f254f9 AL |
132 | |
133 | /* Active packets */ | |
f8af1e88 | 134 | QTAILQ_HEAD(, UHCIQueue) queues; |
64e58fe5 | 135 | uint8_t num_ports_vmstate; |
35e4977f HG |
136 | |
137 | /* Properties */ | |
138 | char *masterbus; | |
139 | uint32_t firstport; | |
9fdf7027 | 140 | uint32_t maxframes; |
7b5a44c5 | 141 | }; |
bb36d470 FB |
142 | |
143 | typedef struct UHCI_TD { | |
144 | uint32_t link; | |
145 | uint32_t ctrl; /* see TD_CTRL_xxx */ | |
146 | uint32_t token; | |
147 | uint32_t buffer; | |
148 | } UHCI_TD; | |
149 | ||
150 | typedef struct UHCI_QH { | |
151 | uint32_t link; | |
152 | uint32_t el_link; | |
153 | } UHCI_QH; | |
154 | ||
40507377 | 155 | static void uhci_async_cancel(UHCIAsync *async); |
11d15e40 | 156 | static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); |
9f0f1a0c | 157 | static void uhci_resume(void *opaque); |
40507377 | 158 | |
49184b62 GA |
159 | #define TYPE_UHCI "pci-uhci-usb" |
160 | #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI) | |
161 | ||
f8af1e88 GH |
162 | static inline int32_t uhci_queue_token(UHCI_TD *td) |
163 | { | |
6fe30910 HG |
164 | if ((td->token & (0xf << 15)) == 0) { |
165 | /* ctrl ep, cover ep and dev, not pid! */ | |
166 | return td->token & 0x7ff00; | |
167 | } else { | |
168 | /* covers ep, dev, pid -> identifies the endpoint */ | |
169 | return td->token & 0x7ffff; | |
170 | } | |
f8af1e88 GH |
171 | } |
172 | ||
66a08cbe HG |
173 | static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, |
174 | USBEndpoint *ep) | |
f8af1e88 | 175 | { |
f8af1e88 GH |
176 | UHCIQueue *queue; |
177 | ||
f8af1e88 GH |
178 | queue = g_new0(UHCIQueue, 1); |
179 | queue->uhci = s; | |
66a08cbe HG |
180 | queue->qh_addr = qh_addr; |
181 | queue->token = uhci_queue_token(td); | |
11d15e40 | 182 | queue->ep = ep; |
f8af1e88 GH |
183 | QTAILQ_INIT(&queue->asyncs); |
184 | QTAILQ_INSERT_HEAD(&s->queues, queue, next); | |
475443cf | 185 | queue->valid = QH_VALID; |
50dcc0f8 | 186 | trace_usb_uhci_queue_add(queue->token); |
f8af1e88 GH |
187 | return queue; |
188 | } | |
189 | ||
66a08cbe | 190 | static void uhci_queue_free(UHCIQueue *queue, const char *reason) |
f8af1e88 GH |
191 | { |
192 | UHCIState *s = queue->uhci; | |
40507377 HG |
193 | UHCIAsync *async; |
194 | ||
195 | while (!QTAILQ_EMPTY(&queue->asyncs)) { | |
196 | async = QTAILQ_FIRST(&queue->asyncs); | |
197 | uhci_async_cancel(async); | |
198 | } | |
f79738b0 | 199 | usb_device_ep_stopped(queue->ep->dev, queue->ep); |
f8af1e88 | 200 | |
66a08cbe | 201 | trace_usb_uhci_queue_del(queue->token, reason); |
f8af1e88 GH |
202 | QTAILQ_REMOVE(&s->queues, queue, next); |
203 | g_free(queue); | |
204 | } | |
205 | ||
66a08cbe HG |
206 | static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) |
207 | { | |
208 | uint32_t token = uhci_queue_token(td); | |
209 | UHCIQueue *queue; | |
210 | ||
211 | QTAILQ_FOREACH(queue, &s->queues, next) { | |
212 | if (queue->token == token) { | |
213 | return queue; | |
214 | } | |
215 | } | |
216 | return NULL; | |
217 | } | |
218 | ||
219 | static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, | |
220 | uint32_t td_addr, bool queuing) | |
221 | { | |
222 | UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); | |
c348e481 | 223 | uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; |
66a08cbe HG |
224 | |
225 | return queue->qh_addr == qh_addr && | |
226 | queue->token == uhci_queue_token(td) && | |
c348e481 | 227 | queue_token_addr == queue->ep->dev->addr && |
66a08cbe HG |
228 | (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || |
229 | first->td_addr == td_addr); | |
230 | } | |
231 | ||
1f250cc7 | 232 | static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) |
54f254f9 | 233 | { |
326700e3 | 234 | UHCIAsync *async = g_new0(UHCIAsync, 1); |
487414f1 | 235 | |
f8af1e88 | 236 | async->queue = queue; |
1f250cc7 | 237 | async->td_addr = td_addr; |
4f4321c1 | 238 | usb_packet_init(&async->packet); |
1f250cc7 | 239 | trace_usb_uhci_packet_add(async->queue->token, async->td_addr); |
54f254f9 AL |
240 | |
241 | return async; | |
242 | } | |
243 | ||
f8af1e88 | 244 | static void uhci_async_free(UHCIAsync *async) |
54f254f9 | 245 | { |
1f250cc7 | 246 | trace_usb_uhci_packet_del(async->queue->token, async->td_addr); |
4f4321c1 | 247 | usb_packet_cleanup(&async->packet); |
9822261c HG |
248 | if (async->buf != async->static_buf) { |
249 | g_free(async->buf); | |
250 | } | |
7267c094 | 251 | g_free(async); |
54f254f9 AL |
252 | } |
253 | ||
f8af1e88 | 254 | static void uhci_async_link(UHCIAsync *async) |
54f254f9 | 255 | { |
f8af1e88 GH |
256 | UHCIQueue *queue = async->queue; |
257 | QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); | |
1f250cc7 | 258 | trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); |
54f254f9 AL |
259 | } |
260 | ||
f8af1e88 | 261 | static void uhci_async_unlink(UHCIAsync *async) |
54f254f9 | 262 | { |
f8af1e88 GH |
263 | UHCIQueue *queue = async->queue; |
264 | QTAILQ_REMOVE(&queue->asyncs, async, next); | |
1f250cc7 | 265 | trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); |
54f254f9 AL |
266 | } |
267 | ||
f8af1e88 | 268 | static void uhci_async_cancel(UHCIAsync *async) |
54f254f9 | 269 | { |
2f2ee268 | 270 | uhci_async_unlink(async); |
1f250cc7 HG |
271 | trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, |
272 | async->done); | |
54f254f9 AL |
273 | if (!async->done) |
274 | usb_cancel_packet(&async->packet); | |
f8af1e88 | 275 | uhci_async_free(async); |
54f254f9 AL |
276 | } |
277 | ||
278 | /* | |
279 | * Mark all outstanding async packets as invalid. | |
280 | * This is used for canceling them when TDs are removed by the HCD. | |
281 | */ | |
f8af1e88 | 282 | static void uhci_async_validate_begin(UHCIState *s) |
54f254f9 | 283 | { |
f8af1e88 | 284 | UHCIQueue *queue; |
54f254f9 | 285 | |
f8af1e88 GH |
286 | QTAILQ_FOREACH(queue, &s->queues, next) { |
287 | queue->valid--; | |
54f254f9 | 288 | } |
54f254f9 AL |
289 | } |
290 | ||
291 | /* | |
292 | * Cancel async packets that are no longer valid | |
293 | */ | |
294 | static void uhci_async_validate_end(UHCIState *s) | |
295 | { | |
f8af1e88 | 296 | UHCIQueue *queue, *n; |
54f254f9 | 297 | |
f8af1e88 | 298 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { |
40507377 | 299 | if (!queue->valid) { |
66a08cbe | 300 | uhci_queue_free(queue, "validate-end"); |
f8af1e88 | 301 | } |
54f254f9 AL |
302 | } |
303 | } | |
304 | ||
07771f6f GH |
305 | static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
306 | { | |
5ad23e87 | 307 | UHCIQueue *queue, *n; |
07771f6f | 308 | |
5ad23e87 HG |
309 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { |
310 | if (queue->ep->dev == dev) { | |
311 | uhci_queue_free(queue, "cancel-device"); | |
07771f6f | 312 | } |
07771f6f GH |
313 | } |
314 | } | |
315 | ||
54f254f9 AL |
316 | static void uhci_async_cancel_all(UHCIState *s) |
317 | { | |
77fa9aee | 318 | UHCIQueue *queue, *nq; |
54f254f9 | 319 | |
77fa9aee | 320 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { |
66a08cbe | 321 | uhci_queue_free(queue, "cancel-all"); |
54f254f9 | 322 | } |
54f254f9 AL |
323 | } |
324 | ||
8c75a899 | 325 | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) |
54f254f9 | 326 | { |
f8af1e88 | 327 | UHCIQueue *queue; |
ddf6583f | 328 | UHCIAsync *async; |
e8ee3c72 | 329 | |
f8af1e88 | 330 | QTAILQ_FOREACH(queue, &s->queues, next) { |
8c75a899 HG |
331 | QTAILQ_FOREACH(async, &queue->asyncs, next) { |
332 | if (async->td_addr == td_addr) { | |
333 | return async; | |
334 | } | |
f8af1e88 GH |
335 | } |
336 | } | |
f8af1e88 | 337 | return NULL; |
54f254f9 AL |
338 | } |
339 | ||
bb36d470 FB |
340 | static void uhci_update_irq(UHCIState *s) |
341 | { | |
342 | int level; | |
343 | if (((s->status2 & 1) && (s->intr & (1 << 2))) || | |
344 | ((s->status2 & 2) && (s->intr & (1 << 3))) || | |
345 | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || | |
346 | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || | |
347 | (s->status & UHCI_STS_HSERR) || | |
348 | (s->status & UHCI_STS_HCPERR)) { | |
349 | level = 1; | |
350 | } else { | |
351 | level = 0; | |
352 | } | |
9e64f8a3 | 353 | pci_set_irq(&s->dev, level); |
bb36d470 FB |
354 | } |
355 | ||
537e572a | 356 | static void uhci_reset(DeviceState *dev) |
bb36d470 | 357 | { |
537e572a | 358 | PCIDevice *d = PCI_DEVICE(dev); |
49184b62 | 359 | UHCIState *s = UHCI(d); |
bb36d470 FB |
360 | uint8_t *pci_conf; |
361 | int i; | |
362 | UHCIPort *port; | |
363 | ||
50dcc0f8 | 364 | trace_usb_uhci_reset(); |
6f382b5e | 365 | |
bb36d470 FB |
366 | pci_conf = s->dev.config; |
367 | ||
368 | pci_conf[0x6a] = 0x01; /* usb clock */ | |
369 | pci_conf[0x6b] = 0x00; | |
370 | s->cmd = 0; | |
ca5a21c4 | 371 | s->status = UHCI_STS_HCHALTED; |
bb36d470 FB |
372 | s->status2 = 0; |
373 | s->intr = 0; | |
374 | s->fl_base_addr = 0; | |
375 | s->sof_timing = 64; | |
54f254f9 | 376 | |
bb36d470 FB |
377 | for(i = 0; i < NB_PORTS; i++) { |
378 | port = &s->ports[i]; | |
379 | port->ctrl = 0x0080; | |
891fb2cd | 380 | if (port->port.dev && port->port.dev->attached) { |
d28f4e2d | 381 | usb_port_reset(&port->port); |
618c169b | 382 | } |
bb36d470 | 383 | } |
54f254f9 AL |
384 | |
385 | uhci_async_cancel_all(s); | |
9a16c595 | 386 | qemu_bh_cancel(s->bh); |
aba1f242 | 387 | uhci_update_irq(s); |
bb36d470 FB |
388 | } |
389 | ||
817afc61 JQ |
390 | static const VMStateDescription vmstate_uhci_port = { |
391 | .name = "uhci port", | |
392 | .version_id = 1, | |
393 | .minimum_version_id = 1, | |
6e3d652a | 394 | .fields = (VMStateField[]) { |
817afc61 JQ |
395 | VMSTATE_UINT16(ctrl, UHCIPort), |
396 | VMSTATE_END_OF_LIST() | |
397 | } | |
398 | }; | |
399 | ||
75f151cd GH |
400 | static int uhci_post_load(void *opaque, int version_id) |
401 | { | |
402 | UHCIState *s = opaque; | |
403 | ||
404 | if (version_id < 2) { | |
bc72ad67 | 405 | s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
75f151cd GH |
406 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
407 | } | |
408 | return 0; | |
409 | } | |
410 | ||
817afc61 JQ |
411 | static const VMStateDescription vmstate_uhci = { |
412 | .name = "uhci", | |
ecfdc15f | 413 | .version_id = 3, |
817afc61 | 414 | .minimum_version_id = 1, |
75f151cd | 415 | .post_load = uhci_post_load, |
6e3d652a | 416 | .fields = (VMStateField[]) { |
817afc61 JQ |
417 | VMSTATE_PCI_DEVICE(dev, UHCIState), |
418 | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), | |
419 | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, | |
420 | vmstate_uhci_port, UHCIPort), | |
421 | VMSTATE_UINT16(cmd, UHCIState), | |
422 | VMSTATE_UINT16(status, UHCIState), | |
423 | VMSTATE_UINT16(intr, UHCIState), | |
424 | VMSTATE_UINT16(frnum, UHCIState), | |
425 | VMSTATE_UINT32(fl_base_addr, UHCIState), | |
426 | VMSTATE_UINT8(sof_timing, UHCIState), | |
427 | VMSTATE_UINT8(status2, UHCIState), | |
e720677e | 428 | VMSTATE_TIMER_PTR(frame_timer, UHCIState), |
6881dd5f | 429 | VMSTATE_INT64_V(expire_time, UHCIState, 2), |
ecfdc15f | 430 | VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), |
817afc61 JQ |
431 | VMSTATE_END_OF_LIST() |
432 | } | |
433 | }; | |
b9dc033c | 434 | |
89eb147c GH |
435 | static void uhci_port_write(void *opaque, hwaddr addr, |
436 | uint64_t val, unsigned size) | |
bb36d470 FB |
437 | { |
438 | UHCIState *s = opaque; | |
3b46e624 | 439 | |
50dcc0f8 | 440 | trace_usb_uhci_mmio_writew(addr, val); |
54f254f9 | 441 | |
bb36d470 FB |
442 | switch(addr) { |
443 | case 0x00: | |
444 | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { | |
445 | /* start frame processing */ | |
50dcc0f8 | 446 | trace_usb_uhci_schedule_start(); |
bc72ad67 | 447 | s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
94cc916a | 448 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
bc72ad67 | 449 | timer_mod(s->frame_timer, s->expire_time); |
52328140 | 450 | s->status &= ~UHCI_STS_HCHALTED; |
467d409f | 451 | } else if (!(val & UHCI_CMD_RS)) { |
52328140 | 452 | s->status |= UHCI_STS_HCHALTED; |
bb36d470 FB |
453 | } |
454 | if (val & UHCI_CMD_GRESET) { | |
455 | UHCIPort *port; | |
bb36d470 FB |
456 | int i; |
457 | ||
458 | /* send reset on the USB bus */ | |
459 | for(i = 0; i < NB_PORTS; i++) { | |
460 | port = &s->ports[i]; | |
d28f4e2d | 461 | usb_device_reset(port->port.dev); |
bb36d470 | 462 | } |
537e572a | 463 | uhci_reset(DEVICE(s)); |
bb36d470 FB |
464 | return; |
465 | } | |
5e9ab4c4 | 466 | if (val & UHCI_CMD_HCRESET) { |
537e572a | 467 | uhci_reset(DEVICE(s)); |
bb36d470 FB |
468 | return; |
469 | } | |
470 | s->cmd = val; | |
9f0f1a0c GH |
471 | if (val & UHCI_CMD_EGSM) { |
472 | if ((s->ports[0].ctrl & UHCI_PORT_RD) || | |
473 | (s->ports[1].ctrl & UHCI_PORT_RD)) { | |
474 | uhci_resume(s); | |
475 | } | |
476 | } | |
bb36d470 FB |
477 | break; |
478 | case 0x02: | |
479 | s->status &= ~val; | |
480 | /* XXX: the chip spec is not coherent, so we add a hidden | |
481 | register to distinguish between IOC and SPD */ | |
482 | if (val & UHCI_STS_USBINT) | |
483 | s->status2 = 0; | |
484 | uhci_update_irq(s); | |
485 | break; | |
486 | case 0x04: | |
487 | s->intr = val; | |
488 | uhci_update_irq(s); | |
489 | break; | |
490 | case 0x06: | |
491 | if (s->status & UHCI_STS_HCHALTED) | |
492 | s->frnum = val & 0x7ff; | |
493 | break; | |
89eb147c GH |
494 | case 0x08: |
495 | s->fl_base_addr &= 0xffff0000; | |
496 | s->fl_base_addr |= val & ~0xfff; | |
497 | break; | |
498 | case 0x0a: | |
499 | s->fl_base_addr &= 0x0000ffff; | |
500 | s->fl_base_addr |= (val << 16); | |
501 | break; | |
502 | case 0x0c: | |
503 | s->sof_timing = val & 0xff; | |
504 | break; | |
bb36d470 FB |
505 | case 0x10 ... 0x1f: |
506 | { | |
507 | UHCIPort *port; | |
508 | USBDevice *dev; | |
509 | int n; | |
510 | ||
511 | n = (addr >> 1) & 7; | |
512 | if (n >= NB_PORTS) | |
513 | return; | |
514 | port = &s->ports[n]; | |
a594cfbf | 515 | dev = port->port.dev; |
891fb2cd | 516 | if (dev && dev->attached) { |
bb36d470 | 517 | /* port reset */ |
5fafdf24 | 518 | if ( (val & UHCI_PORT_RESET) && |
bb36d470 | 519 | !(port->ctrl & UHCI_PORT_RESET) ) { |
d28f4e2d | 520 | usb_device_reset(dev); |
bb36d470 FB |
521 | } |
522 | } | |
9159f679 | 523 | port->ctrl &= UHCI_PORT_READ_ONLY; |
1cbdde90 HG |
524 | /* enabled may only be set if a device is connected */ |
525 | if (!(port->ctrl & UHCI_PORT_CCS)) { | |
526 | val &= ~UHCI_PORT_EN; | |
527 | } | |
9159f679 | 528 | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); |
bb36d470 | 529 | /* some bits are reset when a '1' is written to them */ |
9159f679 | 530 | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
bb36d470 FB |
531 | } |
532 | break; | |
533 | } | |
534 | } | |
535 | ||
89eb147c | 536 | static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) |
bb36d470 FB |
537 | { |
538 | UHCIState *s = opaque; | |
539 | uint32_t val; | |
540 | ||
bb36d470 FB |
541 | switch(addr) { |
542 | case 0x00: | |
543 | val = s->cmd; | |
544 | break; | |
545 | case 0x02: | |
546 | val = s->status; | |
547 | break; | |
548 | case 0x04: | |
549 | val = s->intr; | |
550 | break; | |
551 | case 0x06: | |
552 | val = s->frnum; | |
553 | break; | |
89eb147c GH |
554 | case 0x08: |
555 | val = s->fl_base_addr & 0xffff; | |
556 | break; | |
557 | case 0x0a: | |
558 | val = (s->fl_base_addr >> 16) & 0xffff; | |
559 | break; | |
560 | case 0x0c: | |
561 | val = s->sof_timing; | |
562 | break; | |
bb36d470 FB |
563 | case 0x10 ... 0x1f: |
564 | { | |
565 | UHCIPort *port; | |
566 | int n; | |
567 | n = (addr >> 1) & 7; | |
5fafdf24 | 568 | if (n >= NB_PORTS) |
bb36d470 FB |
569 | goto read_default; |
570 | port = &s->ports[n]; | |
571 | val = port->ctrl; | |
572 | } | |
573 | break; | |
574 | default: | |
575 | read_default: | |
576 | val = 0xff7f; /* disabled port */ | |
577 | break; | |
578 | } | |
54f254f9 | 579 | |
50dcc0f8 | 580 | trace_usb_uhci_mmio_readw(addr, val); |
54f254f9 | 581 | |
bb36d470 FB |
582 | return val; |
583 | } | |
584 | ||
96217e31 TS |
585 | /* signal resume if controller suspended */ |
586 | static void uhci_resume (void *opaque) | |
587 | { | |
588 | UHCIState *s = (UHCIState *)opaque; | |
589 | ||
590 | if (!s) | |
591 | return; | |
592 | ||
593 | if (s->cmd & UHCI_CMD_EGSM) { | |
594 | s->cmd |= UHCI_CMD_FGR; | |
595 | s->status |= UHCI_STS_RD; | |
596 | uhci_update_irq(s); | |
597 | } | |
598 | } | |
599 | ||
618c169b | 600 | static void uhci_attach(USBPort *port1) |
bb36d470 FB |
601 | { |
602 | UHCIState *s = port1->opaque; | |
603 | UHCIPort *port = &s->ports[port1->index]; | |
604 | ||
618c169b GH |
605 | /* set connect status */ |
606 | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; | |
61064870 | 607 | |
618c169b GH |
608 | /* update speed */ |
609 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
610 | port->ctrl |= UHCI_PORT_LSDA; | |
bb36d470 | 611 | } else { |
618c169b GH |
612 | port->ctrl &= ~UHCI_PORT_LSDA; |
613 | } | |
96217e31 | 614 | |
618c169b GH |
615 | uhci_resume(s); |
616 | } | |
96217e31 | 617 | |
618c169b GH |
618 | static void uhci_detach(USBPort *port1) |
619 | { | |
620 | UHCIState *s = port1->opaque; | |
621 | UHCIPort *port = &s->ports[port1->index]; | |
622 | ||
4706ab6c HG |
623 | uhci_async_cancel_device(s, port1->dev); |
624 | ||
618c169b GH |
625 | /* set connect status */ |
626 | if (port->ctrl & UHCI_PORT_CCS) { | |
627 | port->ctrl &= ~UHCI_PORT_CCS; | |
628 | port->ctrl |= UHCI_PORT_CSC; | |
bb36d470 | 629 | } |
618c169b GH |
630 | /* disable port */ |
631 | if (port->ctrl & UHCI_PORT_EN) { | |
632 | port->ctrl &= ~UHCI_PORT_EN; | |
633 | port->ctrl |= UHCI_PORT_ENC; | |
634 | } | |
635 | ||
636 | uhci_resume(s); | |
bb36d470 FB |
637 | } |
638 | ||
4706ab6c HG |
639 | static void uhci_child_detach(USBPort *port1, USBDevice *child) |
640 | { | |
641 | UHCIState *s = port1->opaque; | |
642 | ||
643 | uhci_async_cancel_device(s, child); | |
644 | } | |
645 | ||
d47e59b8 | 646 | static void uhci_wakeup(USBPort *port1) |
9159f679 | 647 | { |
d47e59b8 HG |
648 | UHCIState *s = port1->opaque; |
649 | UHCIPort *port = &s->ports[port1->index]; | |
9159f679 GH |
650 | |
651 | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { | |
652 | port->ctrl |= UHCI_PORT_RD; | |
653 | uhci_resume(s); | |
654 | } | |
655 | } | |
656 | ||
461700c1 | 657 | static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) |
bb36d470 | 658 | { |
461700c1 GH |
659 | USBDevice *dev; |
660 | int i; | |
54f254f9 | 661 | |
461700c1 | 662 | for (i = 0; i < NB_PORTS; i++) { |
54f254f9 | 663 | UHCIPort *port = &s->ports[i]; |
461700c1 GH |
664 | if (!(port->ctrl & UHCI_PORT_EN)) { |
665 | continue; | |
666 | } | |
667 | dev = usb_find_device(&port->port, addr); | |
668 | if (dev != NULL) { | |
669 | return dev; | |
891fb2cd | 670 | } |
bb36d470 | 671 | } |
461700c1 | 672 | return NULL; |
bb36d470 FB |
673 | } |
674 | ||
963a68b5 HG |
675 | static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) |
676 | { | |
677 | pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); | |
678 | le32_to_cpus(&td->link); | |
679 | le32_to_cpus(&td->ctrl); | |
680 | le32_to_cpus(&td->token); | |
681 | le32_to_cpus(&td->buffer); | |
682 | } | |
683 | ||
faccca00 HG |
684 | static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, |
685 | int status, uint32_t *int_mask) | |
686 | { | |
687 | uint32_t queue_token = uhci_queue_token(td); | |
688 | int ret; | |
689 | ||
690 | switch (status) { | |
691 | case USB_RET_NAK: | |
692 | td->ctrl |= TD_CTRL_NAK; | |
693 | return TD_RESULT_NEXT_QH; | |
694 | ||
695 | case USB_RET_STALL: | |
696 | td->ctrl |= TD_CTRL_STALL; | |
697 | trace_usb_uhci_packet_complete_stall(queue_token, td_addr); | |
698 | ret = TD_RESULT_NEXT_QH; | |
699 | break; | |
700 | ||
701 | case USB_RET_BABBLE: | |
702 | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; | |
703 | /* frame interrupted */ | |
704 | trace_usb_uhci_packet_complete_babble(queue_token, td_addr); | |
705 | ret = TD_RESULT_STOP_FRAME; | |
706 | break; | |
707 | ||
708 | case USB_RET_IOERROR: | |
709 | case USB_RET_NODEV: | |
710 | default: | |
711 | td->ctrl |= TD_CTRL_TIMEOUT; | |
712 | td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); | |
713 | trace_usb_uhci_packet_complete_error(queue_token, td_addr); | |
714 | ret = TD_RESULT_NEXT_QH; | |
715 | break; | |
716 | } | |
717 | ||
718 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
719 | s->status |= UHCI_STS_USBERR; | |
720 | if (td->ctrl & TD_CTRL_IOC) { | |
721 | *int_mask |= 0x01; | |
722 | } | |
723 | uhci_update_irq(s); | |
724 | return ret; | |
725 | } | |
726 | ||
54f254f9 | 727 | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
bb36d470 | 728 | { |
9a77a0f5 | 729 | int len = 0, max_len; |
bb36d470 | 730 | uint8_t pid; |
bb36d470 | 731 | |
54f254f9 AL |
732 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
733 | pid = td->token & 0xff; | |
734 | ||
54f254f9 AL |
735 | if (td->ctrl & TD_CTRL_IOS) |
736 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
bb36d470 | 737 | |
9a77a0f5 HG |
738 | if (async->packet.status != USB_RET_SUCCESS) { |
739 | return uhci_handle_td_error(s, td, async->td_addr, | |
740 | async->packet.status, int_mask); | |
faccca00 | 741 | } |
b9dc033c | 742 | |
9a77a0f5 | 743 | len = async->packet.actual_length; |
54f254f9 AL |
744 | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
745 | ||
746 | /* The NAK bit may have been set by a previous frame, so clear it | |
747 | here. The docs are somewhat unclear, but win2k relies on this | |
748 | behavior. */ | |
749 | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); | |
5bd2c0d7 PB |
750 | if (td->ctrl & TD_CTRL_IOC) |
751 | *int_mask |= 0x01; | |
54f254f9 AL |
752 | |
753 | if (pid == USB_TOKEN_IN) { | |
9822261c | 754 | pci_dma_write(&s->dev, td->buffer, async->buf, len); |
54f254f9 | 755 | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { |
bb36d470 FB |
756 | *int_mask |= 0x02; |
757 | /* short packet: do not update QH */ | |
50dcc0f8 | 758 | trace_usb_uhci_packet_complete_shortxfer(async->queue->token, |
1f250cc7 | 759 | async->td_addr); |
60e1b2a6 | 760 | return TD_RESULT_NEXT_QH; |
bb36d470 | 761 | } |
54f254f9 AL |
762 | } |
763 | ||
764 | /* success */ | |
1f250cc7 HG |
765 | trace_usb_uhci_packet_complete_success(async->queue->token, |
766 | async->td_addr); | |
60e1b2a6 | 767 | return TD_RESULT_COMPLETE; |
bb36d470 FB |
768 | } |
769 | ||
66a08cbe | 770 | static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, |
a4f30cd7 | 771 | UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) |
54f254f9 | 772 | { |
9a77a0f5 | 773 | int ret, max_len; |
6ba43f1f | 774 | bool spd; |
a4f30cd7 | 775 | bool queuing = (q != NULL); |
11d15e40 | 776 | uint8_t pid = td->token & 0xff; |
5f77e06b GA |
777 | UHCIAsync *async; |
778 | ||
779 | switch (pid) { | |
780 | case USB_TOKEN_OUT: | |
781 | case USB_TOKEN_SETUP: | |
782 | case USB_TOKEN_IN: | |
783 | break; | |
784 | default: | |
785 | /* invalid pid : frame interrupted */ | |
786 | s->status |= UHCI_STS_HCPERR; | |
787 | s->cmd &= ~UHCI_CMD_RS; | |
788 | uhci_update_irq(s); | |
789 | return TD_RESULT_STOP_FRAME; | |
790 | } | |
8c75a899 | 791 | |
5f77e06b | 792 | async = uhci_async_find_td(s, td_addr); |
8c75a899 HG |
793 | if (async) { |
794 | if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { | |
795 | assert(q == NULL || q == async->queue); | |
796 | q = async->queue; | |
797 | } else { | |
798 | uhci_queue_free(async->queue, "guest re-used pending td"); | |
799 | async = NULL; | |
800 | } | |
801 | } | |
54f254f9 | 802 | |
66a08cbe HG |
803 | if (q == NULL) { |
804 | q = uhci_queue_find(s, td); | |
805 | if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { | |
806 | uhci_queue_free(q, "guest re-used qh"); | |
807 | q = NULL; | |
808 | } | |
809 | } | |
810 | ||
3905097e | 811 | if (q) { |
475443cf | 812 | q->valid = QH_VALID; |
3905097e HG |
813 | } |
814 | ||
54f254f9 | 815 | /* Is active ? */ |
883bca77 | 816 | if (!(td->ctrl & TD_CTRL_ACTIVE)) { |
420ca987 HG |
817 | if (async) { |
818 | /* Guest marked a pending td non-active, cancel the queue */ | |
819 | uhci_queue_free(async->queue, "pending td non-active"); | |
820 | } | |
883bca77 HG |
821 | /* |
822 | * ehci11d spec page 22: "Even if the Active bit in the TD is already | |
823 | * cleared when the TD is fetched ... an IOC interrupt is generated" | |
824 | */ | |
825 | if (td->ctrl & TD_CTRL_IOC) { | |
826 | *int_mask |= 0x01; | |
827 | } | |
60e1b2a6 | 828 | return TD_RESULT_NEXT_QH; |
883bca77 | 829 | } |
54f254f9 | 830 | |
54f254f9 | 831 | if (async) { |
ee008ba6 GH |
832 | if (queuing) { |
833 | /* we are busy filling the queue, we are not prepared | |
834 | to consume completed packages then, just leave them | |
835 | in async state */ | |
836 | return TD_RESULT_ASYNC_CONT; | |
837 | } | |
8928c9c4 HG |
838 | if (!async->done) { |
839 | UHCI_TD last_td; | |
840 | UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); | |
841 | /* | |
842 | * While we are waiting for the current td to complete, the guest | |
843 | * may have added more tds to the queue. Note we re-read the td | |
844 | * rather then caching it, as we want to see guest made changes! | |
845 | */ | |
846 | uhci_read_td(s, &last_td, last->td_addr); | |
847 | uhci_queue_fill(async->queue, &last_td); | |
54f254f9 | 848 | |
8928c9c4 HG |
849 | return TD_RESULT_ASYNC_CONT; |
850 | } | |
f8af1e88 | 851 | uhci_async_unlink(async); |
54f254f9 AL |
852 | goto done; |
853 | } | |
854 | ||
88793816 HG |
855 | if (s->completions_only) { |
856 | return TD_RESULT_ASYNC_CONT; | |
857 | } | |
858 | ||
54f254f9 | 859 | /* Allocate new packet */ |
a4f30cd7 | 860 | if (q == NULL) { |
11d15e40 HG |
861 | USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); |
862 | USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); | |
7f102ebe HG |
863 | |
864 | if (ep == NULL) { | |
865 | return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, | |
866 | int_mask); | |
867 | } | |
66a08cbe | 868 | q = uhci_queue_new(s, qh_addr, td, ep); |
a4f30cd7 HG |
869 | } |
870 | async = uhci_async_alloc(q, td_addr); | |
54f254f9 | 871 | |
54f254f9 | 872 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
6ba43f1f | 873 | spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); |
8550a02d | 874 | usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, |
a6fb2ddb | 875 | (td->ctrl & TD_CTRL_IOC) != 0); |
9822261c HG |
876 | if (max_len <= sizeof(async->static_buf)) { |
877 | async->buf = async->static_buf; | |
878 | } else { | |
879 | async->buf = g_malloc(max_len); | |
880 | } | |
881 | usb_packet_addbuf(&async->packet, async->buf, max_len); | |
54f254f9 AL |
882 | |
883 | switch(pid) { | |
884 | case USB_TOKEN_OUT: | |
885 | case USB_TOKEN_SETUP: | |
9822261c | 886 | pci_dma_read(&s->dev, td->buffer, async->buf, max_len); |
9a77a0f5 HG |
887 | usb_handle_packet(q->ep->dev, &async->packet); |
888 | if (async->packet.status == USB_RET_SUCCESS) { | |
889 | async->packet.actual_length = max_len; | |
890 | } | |
54f254f9 AL |
891 | break; |
892 | ||
893 | case USB_TOKEN_IN: | |
9a77a0f5 | 894 | usb_handle_packet(q->ep->dev, &async->packet); |
54f254f9 AL |
895 | break; |
896 | ||
897 | default: | |
5f77e06b | 898 | abort(); /* Never to execute */ |
54f254f9 | 899 | } |
9a77a0f5 HG |
900 | |
901 | if (async->packet.status == USB_RET_ASYNC) { | |
f8af1e88 | 902 | uhci_async_link(async); |
a4f30cd7 | 903 | if (!queuing) { |
11d15e40 | 904 | uhci_queue_fill(q, td); |
a4f30cd7 | 905 | } |
4efe4ef3 | 906 | return TD_RESULT_ASYNC_START; |
54f254f9 AL |
907 | } |
908 | ||
54f254f9 | 909 | done: |
9a77a0f5 | 910 | ret = uhci_complete_td(s, td, async, int_mask); |
f8af1e88 | 911 | uhci_async_free(async); |
9a77a0f5 | 912 | return ret; |
54f254f9 AL |
913 | } |
914 | ||
d47e59b8 | 915 | static void uhci_async_complete(USBPort *port, USBPacket *packet) |
4d611c9a | 916 | { |
7b5a44c5 | 917 | UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
f8af1e88 | 918 | UHCIState *s = async->queue->uhci; |
54f254f9 | 919 | |
9a77a0f5 | 920 | if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { |
0cae7b1a HG |
921 | uhci_async_cancel(async); |
922 | return; | |
923 | } | |
924 | ||
5b352ed5 | 925 | async->done = 1; |
88793816 HG |
926 | /* Force processing of this packet *now*, needed for migration */ |
927 | s->completions_only = true; | |
928 | qemu_bh_schedule(s->bh); | |
54f254f9 AL |
929 | } |
930 | ||
931 | static int is_valid(uint32_t link) | |
932 | { | |
933 | return (link & 1) == 0; | |
934 | } | |
935 | ||
936 | static int is_qh(uint32_t link) | |
937 | { | |
938 | return (link & 2) != 0; | |
939 | } | |
940 | ||
941 | static int depth_first(uint32_t link) | |
942 | { | |
943 | return (link & 4) != 0; | |
944 | } | |
945 | ||
946 | /* QH DB used for detecting QH loops */ | |
947 | #define UHCI_MAX_QUEUES 128 | |
948 | typedef struct { | |
949 | uint32_t addr[UHCI_MAX_QUEUES]; | |
950 | int count; | |
951 | } QhDb; | |
952 | ||
953 | static void qhdb_reset(QhDb *db) | |
954 | { | |
955 | db->count = 0; | |
956 | } | |
957 | ||
958 | /* Add QH to DB. Returns 1 if already present or DB is full. */ | |
959 | static int qhdb_insert(QhDb *db, uint32_t addr) | |
960 | { | |
961 | int i; | |
962 | for (i = 0; i < db->count; i++) | |
963 | if (db->addr[i] == addr) | |
964 | return 1; | |
965 | ||
966 | if (db->count >= UHCI_MAX_QUEUES) | |
967 | return 1; | |
968 | ||
969 | db->addr[db->count++] = addr; | |
970 | return 0; | |
971 | } | |
972 | ||
11d15e40 | 973 | static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) |
5a248289 GH |
974 | { |
975 | uint32_t int_mask = 0; | |
976 | uint32_t plink = td->link; | |
5a248289 GH |
977 | UHCI_TD ptd; |
978 | int ret; | |
979 | ||
6ba43f1f | 980 | while (is_valid(plink)) { |
a4f30cd7 | 981 | uhci_read_td(q->uhci, &ptd, plink); |
5a248289 GH |
982 | if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { |
983 | break; | |
984 | } | |
a4f30cd7 | 985 | if (uhci_queue_token(&ptd) != q->token) { |
5a248289 GH |
986 | break; |
987 | } | |
50dcc0f8 | 988 | trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); |
66a08cbe | 989 | ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); |
52b0fecd GH |
990 | if (ret == TD_RESULT_ASYNC_CONT) { |
991 | break; | |
992 | } | |
4efe4ef3 | 993 | assert(ret == TD_RESULT_ASYNC_START); |
5a248289 GH |
994 | assert(int_mask == 0); |
995 | plink = ptd.link; | |
996 | } | |
11d15e40 | 997 | usb_device_flush_ep_queue(q->ep->dev, q->ep); |
5a248289 GH |
998 | } |
999 | ||
54f254f9 AL |
1000 | static void uhci_process_frame(UHCIState *s) |
1001 | { | |
1002 | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; | |
4aed20e2 | 1003 | uint32_t curr_qh, td_count = 0; |
54f254f9 | 1004 | int cnt, ret; |
4d611c9a | 1005 | UHCI_TD td; |
54f254f9 AL |
1006 | UHCI_QH qh; |
1007 | QhDb qhdb; | |
4d611c9a | 1008 | |
54f254f9 AL |
1009 | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
1010 | ||
9fe2fd67 | 1011 | pci_dma_read(&s->dev, frame_addr, &link, 4); |
54f254f9 | 1012 | le32_to_cpus(&link); |
b9dc033c | 1013 | |
54f254f9 AL |
1014 | int_mask = 0; |
1015 | curr_qh = 0; | |
1016 | ||
1017 | qhdb_reset(&qhdb); | |
1018 | ||
1019 | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { | |
88793816 | 1020 | if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { |
4aed20e2 GH |
1021 | /* We've reached the usb 1.1 bandwidth, which is |
1022 | 1280 bytes/frame, stop processing */ | |
1023 | trace_usb_uhci_frame_stop_bandwidth(); | |
1024 | break; | |
1025 | } | |
54f254f9 AL |
1026 | if (is_qh(link)) { |
1027 | /* QH */ | |
50dcc0f8 | 1028 | trace_usb_uhci_qh_load(link & ~0xf); |
54f254f9 AL |
1029 | |
1030 | if (qhdb_insert(&qhdb, link)) { | |
1031 | /* | |
1032 | * We're going in circles. Which is not a bug because | |
3200d108 GH |
1033 | * HCD is allowed to do that as part of the BW management. |
1034 | * | |
4aed20e2 GH |
1035 | * Stop processing here if no transaction has been done |
1036 | * since we've been here last time. | |
54f254f9 | 1037 | */ |
3200d108 | 1038 | if (td_count == 0) { |
50dcc0f8 | 1039 | trace_usb_uhci_frame_loop_stop_idle(); |
3200d108 | 1040 | break; |
3200d108 | 1041 | } else { |
50dcc0f8 | 1042 | trace_usb_uhci_frame_loop_continue(); |
3200d108 GH |
1043 | td_count = 0; |
1044 | qhdb_reset(&qhdb); | |
1045 | qhdb_insert(&qhdb, link); | |
1046 | } | |
54f254f9 AL |
1047 | } |
1048 | ||
9fe2fd67 | 1049 | pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); |
54f254f9 AL |
1050 | le32_to_cpus(&qh.link); |
1051 | le32_to_cpus(&qh.el_link); | |
1052 | ||
54f254f9 AL |
1053 | if (!is_valid(qh.el_link)) { |
1054 | /* QH w/o elements */ | |
1055 | curr_qh = 0; | |
1056 | link = qh.link; | |
1057 | } else { | |
1058 | /* QH with elements */ | |
1059 | curr_qh = link; | |
1060 | link = qh.el_link; | |
1061 | } | |
1062 | continue; | |
1063 | } | |
1064 | ||
1065 | /* TD */ | |
963a68b5 | 1066 | uhci_read_td(s, &td, link); |
50dcc0f8 | 1067 | trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); |
54f254f9 AL |
1068 | |
1069 | old_td_ctrl = td.ctrl; | |
66a08cbe | 1070 | ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); |
b9dc033c | 1071 | if (old_td_ctrl != td.ctrl) { |
54f254f9 | 1072 | /* update the status bits of the TD */ |
b9dc033c | 1073 | val = cpu_to_le32(td.ctrl); |
9fe2fd67 | 1074 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
b9dc033c | 1075 | } |
54f254f9 | 1076 | |
971a5a40 | 1077 | switch (ret) { |
60e1b2a6 | 1078 | case TD_RESULT_STOP_FRAME: /* interrupted frame */ |
971a5a40 | 1079 | goto out; |
b9dc033c | 1080 | |
60e1b2a6 | 1081 | case TD_RESULT_NEXT_QH: |
4efe4ef3 | 1082 | case TD_RESULT_ASYNC_CONT: |
50dcc0f8 | 1083 | trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); |
54f254f9 AL |
1084 | link = curr_qh ? qh.link : td.link; |
1085 | continue; | |
54f254f9 | 1086 | |
4efe4ef3 | 1087 | case TD_RESULT_ASYNC_START: |
50dcc0f8 | 1088 | trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); |
971a5a40 GH |
1089 | link = curr_qh ? qh.link : td.link; |
1090 | continue; | |
54f254f9 | 1091 | |
60e1b2a6 | 1092 | case TD_RESULT_COMPLETE: |
50dcc0f8 | 1093 | trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); |
971a5a40 GH |
1094 | link = td.link; |
1095 | td_count++; | |
4aed20e2 | 1096 | s->frame_bytes += (td.ctrl & 0x7ff) + 1; |
54f254f9 | 1097 | |
971a5a40 GH |
1098 | if (curr_qh) { |
1099 | /* update QH element link */ | |
1100 | qh.el_link = link; | |
1101 | val = cpu_to_le32(qh.el_link); | |
1102 | pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); | |
54f254f9 | 1103 | |
971a5a40 GH |
1104 | if (!depth_first(link)) { |
1105 | /* done with this QH */ | |
971a5a40 GH |
1106 | curr_qh = 0; |
1107 | link = qh.link; | |
1108 | } | |
54f254f9 | 1109 | } |
971a5a40 GH |
1110 | break; |
1111 | ||
1112 | default: | |
1113 | assert(!"unknown return code"); | |
4d611c9a | 1114 | } |
54f254f9 AL |
1115 | |
1116 | /* go to the next entry */ | |
4d611c9a | 1117 | } |
54f254f9 | 1118 | |
971a5a40 | 1119 | out: |
8e65b7c0 | 1120 | s->pending_int_mask |= int_mask; |
4d611c9a PB |
1121 | } |
1122 | ||
9a16c595 GH |
1123 | static void uhci_bh(void *opaque) |
1124 | { | |
1125 | UHCIState *s = opaque; | |
1126 | uhci_process_frame(s); | |
1127 | } | |
1128 | ||
bb36d470 FB |
1129 | static void uhci_frame_timer(void *opaque) |
1130 | { | |
1131 | UHCIState *s = opaque; | |
f8f48b69 HG |
1132 | uint64_t t_now, t_last_run; |
1133 | int i, frames; | |
1134 | const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; | |
8e65b7c0 | 1135 | |
88793816 | 1136 | s->completions_only = false; |
9a16c595 | 1137 | qemu_bh_cancel(s->bh); |
bb36d470 FB |
1138 | |
1139 | if (!(s->cmd & UHCI_CMD_RS)) { | |
54f254f9 | 1140 | /* Full stop */ |
50dcc0f8 | 1141 | trace_usb_uhci_schedule_stop(); |
bc72ad67 | 1142 | timer_del(s->frame_timer); |
d9a528db | 1143 | uhci_async_cancel_all(s); |
52328140 FB |
1144 | /* set hchalted bit in status - UHCI11D 2.1.2 */ |
1145 | s->status |= UHCI_STS_HCHALTED; | |
bb36d470 FB |
1146 | return; |
1147 | } | |
54f254f9 | 1148 | |
f8f48b69 HG |
1149 | /* We still store expire_time in our state, for migration */ |
1150 | t_last_run = s->expire_time - frame_t; | |
bc72ad67 | 1151 | t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
54f254f9 | 1152 | |
f8f48b69 HG |
1153 | /* Process up to MAX_FRAMES_PER_TICK frames */ |
1154 | frames = (t_now - t_last_run) / frame_t; | |
9fdf7027 HG |
1155 | if (frames > s->maxframes) { |
1156 | int skipped = frames - s->maxframes; | |
1157 | s->expire_time += skipped * frame_t; | |
1158 | s->frnum = (s->frnum + skipped) & 0x7ff; | |
1159 | frames -= skipped; | |
1160 | } | |
f8f48b69 HG |
1161 | if (frames > MAX_FRAMES_PER_TICK) { |
1162 | frames = MAX_FRAMES_PER_TICK; | |
1163 | } | |
b9dc033c | 1164 | |
f8f48b69 HG |
1165 | for (i = 0; i < frames; i++) { |
1166 | s->frame_bytes = 0; | |
1167 | trace_usb_uhci_frame_start(s->frnum); | |
1168 | uhci_async_validate_begin(s); | |
1169 | uhci_process_frame(s); | |
1170 | uhci_async_validate_end(s); | |
1171 | /* The spec says frnum is the frame currently being processed, and | |
1172 | * the guest must look at frnum - 1 on interrupt, so inc frnum now */ | |
1173 | s->frnum = (s->frnum + 1) & 0x7ff; | |
1174 | s->expire_time += frame_t; | |
1175 | } | |
719c130d | 1176 | |
f8f48b69 | 1177 | /* Complete the previous frame(s) */ |
719c130d HG |
1178 | if (s->pending_int_mask) { |
1179 | s->status2 |= s->pending_int_mask; | |
1180 | s->status |= UHCI_STS_USBINT; | |
1181 | uhci_update_irq(s); | |
1182 | } | |
1183 | s->pending_int_mask = 0; | |
1184 | ||
bc72ad67 | 1185 | timer_mod(s->frame_timer, t_now + frame_t); |
bb36d470 FB |
1186 | } |
1187 | ||
a03f66e4 | 1188 | static const MemoryRegionOps uhci_ioport_ops = { |
89eb147c GH |
1189 | .read = uhci_port_read, |
1190 | .write = uhci_port_write, | |
1191 | .valid.min_access_size = 1, | |
1192 | .valid.max_access_size = 4, | |
1193 | .impl.min_access_size = 2, | |
1194 | .impl.max_access_size = 2, | |
1195 | .endianness = DEVICE_LITTLE_ENDIAN, | |
a03f66e4 | 1196 | }; |
bb36d470 | 1197 | |
0d86d2be GH |
1198 | static USBPortOps uhci_port_ops = { |
1199 | .attach = uhci_attach, | |
618c169b | 1200 | .detach = uhci_detach, |
4706ab6c | 1201 | .child_detach = uhci_child_detach, |
9159f679 | 1202 | .wakeup = uhci_wakeup, |
13a9a0d3 | 1203 | .complete = uhci_async_complete, |
0d86d2be GH |
1204 | }; |
1205 | ||
07771f6f | 1206 | static USBBusOps uhci_bus_ops = { |
07771f6f GH |
1207 | }; |
1208 | ||
63216dc7 | 1209 | static void usb_uhci_common_realize(PCIDevice *dev, Error **errp) |
bb36d470 | 1210 | { |
f4bbaaf5 | 1211 | Error *err = NULL; |
973002c1 | 1212 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
8f3f90b0 | 1213 | UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); |
49184b62 | 1214 | UHCIState *s = UHCI(dev); |
6cf9b6f1 | 1215 | uint8_t *pci_conf = s->dev.config; |
bb36d470 FB |
1216 | int i; |
1217 | ||
db579e9e | 1218 | pci_conf[PCI_CLASS_PROG] = 0x00; |
db579e9e | 1219 | /* TODO: reset value should be 0. */ |
e59d33a7 | 1220 | pci_conf[USB_SBRN] = USB_RELEASE_1; // release number |
3b46e624 | 1221 | |
9e64f8a3 | 1222 | pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); |
973002c1 | 1223 | |
35e4977f HG |
1224 | if (s->masterbus) { |
1225 | USBPort *ports[NB_PORTS]; | |
1226 | for(i = 0; i < NB_PORTS; i++) { | |
1227 | ports[i] = &s->ports[i].port; | |
1228 | } | |
f4bbaaf5 MA |
1229 | usb_register_companion(s->masterbus, ports, NB_PORTS, |
1230 | s->firstport, s, &uhci_port_ops, | |
1231 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, | |
1232 | &err); | |
1233 | if (err) { | |
63216dc7 MA |
1234 | error_propagate(errp, err); |
1235 | return; | |
35e4977f HG |
1236 | } |
1237 | } else { | |
c889b3a5 | 1238 | usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); |
35e4977f HG |
1239 | for (i = 0; i < NB_PORTS; i++) { |
1240 | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, | |
1241 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1242 | } | |
bb36d470 | 1243 | } |
9a16c595 | 1244 | s->bh = qemu_bh_new(uhci_bh, s); |
bc72ad67 | 1245 | s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); |
64e58fe5 | 1246 | s->num_ports_vmstate = NB_PORTS; |
f8af1e88 | 1247 | QTAILQ_INIT(&s->queues); |
bb36d470 | 1248 | |
22fc860b PB |
1249 | memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, |
1250 | "uhci", 0x20); | |
1251 | ||
38ca0f6d PB |
1252 | /* Use region 4 for consistency with real hardware. BSD guests seem |
1253 | to rely on this. */ | |
e824b2cc | 1254 | pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); |
bb36d470 | 1255 | } |
afcc3cdf | 1256 | |
63216dc7 | 1257 | static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) |
30235a54 | 1258 | { |
49184b62 | 1259 | UHCIState *s = UHCI(dev); |
30235a54 HC |
1260 | uint8_t *pci_conf = s->dev.config; |
1261 | ||
30235a54 HC |
1262 | /* USB misc control 1/2 */ |
1263 | pci_set_long(pci_conf + 0x40,0x00001000); | |
1264 | /* PM capability */ | |
1265 | pci_set_long(pci_conf + 0x80,0x00020001); | |
1266 | /* USB legacy support */ | |
1267 | pci_set_long(pci_conf + 0xc0,0x00002000); | |
1268 | ||
63216dc7 | 1269 | usb_uhci_common_realize(dev, errp); |
30235a54 HC |
1270 | } |
1271 | ||
3a3464b0 GA |
1272 | static void usb_uhci_exit(PCIDevice *dev) |
1273 | { | |
49184b62 | 1274 | UHCIState *s = UHCI(dev); |
3a3464b0 | 1275 | |
d733f74c GA |
1276 | trace_usb_uhci_exit(); |
1277 | ||
3a3464b0 GA |
1278 | if (s->frame_timer) { |
1279 | timer_del(s->frame_timer); | |
1280 | timer_free(s->frame_timer); | |
1281 | s->frame_timer = NULL; | |
1282 | } | |
1283 | ||
1284 | if (s->bh) { | |
1285 | qemu_bh_delete(s->bh); | |
1286 | } | |
1287 | ||
1288 | uhci_async_cancel_all(s); | |
1289 | ||
1290 | if (!s->masterbus) { | |
1291 | usb_bus_release(&s->bus); | |
1292 | } | |
1293 | } | |
1294 | ||
638ca939 | 1295 | static Property uhci_properties_companion[] = { |
1b5a7570 GH |
1296 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), |
1297 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
40141d12 | 1298 | DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), |
9fdf7027 | 1299 | DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), |
1b5a7570 GH |
1300 | DEFINE_PROP_END_OF_LIST(), |
1301 | }; | |
638ca939 GH |
1302 | static Property uhci_properties_standalone[] = { |
1303 | DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), | |
1304 | DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), | |
1305 | DEFINE_PROP_END_OF_LIST(), | |
1306 | }; | |
1b5a7570 | 1307 | |
2c2e8525 | 1308 | static void uhci_class_init(ObjectClass *klass, void *data) |
40021f08 | 1309 | { |
39bffca2 | 1310 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 1311 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
49184b62 GA |
1312 | |
1313 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1314 | dc->vmsd = &vmstate_uhci; | |
1315 | dc->reset = uhci_reset; | |
1316 | set_bit(DEVICE_CATEGORY_USB, dc->categories); | |
1317 | } | |
1318 | ||
1319 | static const TypeInfo uhci_pci_type_info = { | |
1320 | .name = TYPE_UHCI, | |
1321 | .parent = TYPE_PCI_DEVICE, | |
1322 | .instance_size = sizeof(UHCIState), | |
1323 | .class_size = sizeof(UHCIPCIDeviceClass), | |
1324 | .abstract = true, | |
1325 | .class_init = uhci_class_init, | |
1326 | }; | |
1327 | ||
1328 | static void uhci_data_class_init(ObjectClass *klass, void *data) | |
1329 | { | |
1330 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1331 | DeviceClass *dc = DEVICE_CLASS(klass); | |
8f3f90b0 | 1332 | UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); |
2c2e8525 GH |
1333 | UHCIInfo *info = data; |
1334 | ||
63216dc7 | 1335 | k->realize = info->realize ? info->realize : usb_uhci_common_realize; |
3a3464b0 | 1336 | k->exit = info->unplug ? usb_uhci_exit : NULL; |
2c2e8525 GH |
1337 | k->vendor_id = info->vendor_id; |
1338 | k->device_id = info->device_id; | |
1339 | k->revision = info->revision; | |
638ca939 GH |
1340 | if (!info->unplug) { |
1341 | /* uhci controllers in companion setups can't be hotplugged */ | |
1342 | dc->hotpluggable = false; | |
1343 | dc->props = uhci_properties_companion; | |
1344 | } else { | |
1345 | dc->props = uhci_properties_standalone; | |
1346 | } | |
8f3f90b0 | 1347 | u->info = *info; |
40021f08 AL |
1348 | } |
1349 | ||
2c2e8525 GH |
1350 | static UHCIInfo uhci_info[] = { |
1351 | { | |
1352 | .name = "piix3-usb-uhci", | |
1353 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1354 | .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, | |
1355 | .revision = 0x01, | |
8f3f90b0 | 1356 | .irq_pin = 3, |
2c2e8525 GH |
1357 | .unplug = true, |
1358 | },{ | |
1359 | .name = "piix4-usb-uhci", | |
1360 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1361 | .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, | |
1362 | .revision = 0x01, | |
8f3f90b0 | 1363 | .irq_pin = 3, |
2c2e8525 GH |
1364 | .unplug = true, |
1365 | },{ | |
1366 | .name = "vt82c686b-usb-uhci", | |
1367 | .vendor_id = PCI_VENDOR_ID_VIA, | |
1368 | .device_id = PCI_DEVICE_ID_VIA_UHCI, | |
1369 | .revision = 0x01, | |
8f3f90b0 | 1370 | .irq_pin = 3, |
63216dc7 | 1371 | .realize = usb_uhci_vt82c686b_realize, |
2c2e8525 GH |
1372 | .unplug = true, |
1373 | },{ | |
74625ea2 | 1374 | .name = "ich9-usb-uhci1", /* 00:1d.0 */ |
2c2e8525 GH |
1375 | .vendor_id = PCI_VENDOR_ID_INTEL, |
1376 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, | |
1377 | .revision = 0x03, | |
8f3f90b0 | 1378 | .irq_pin = 0, |
2c2e8525 GH |
1379 | .unplug = false, |
1380 | },{ | |
74625ea2 | 1381 | .name = "ich9-usb-uhci2", /* 00:1d.1 */ |
2c2e8525 GH |
1382 | .vendor_id = PCI_VENDOR_ID_INTEL, |
1383 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, | |
1384 | .revision = 0x03, | |
8f3f90b0 | 1385 | .irq_pin = 1, |
2c2e8525 GH |
1386 | .unplug = false, |
1387 | },{ | |
74625ea2 | 1388 | .name = "ich9-usb-uhci3", /* 00:1d.2 */ |
2c2e8525 GH |
1389 | .vendor_id = PCI_VENDOR_ID_INTEL, |
1390 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, | |
1391 | .revision = 0x03, | |
8f3f90b0 | 1392 | .irq_pin = 2, |
2c2e8525 | 1393 | .unplug = false, |
74625ea2 GH |
1394 | },{ |
1395 | .name = "ich9-usb-uhci4", /* 00:1a.0 */ | |
1396 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1397 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, | |
1398 | .revision = 0x03, | |
1399 | .irq_pin = 0, | |
1400 | .unplug = false, | |
1401 | },{ | |
1402 | .name = "ich9-usb-uhci5", /* 00:1a.1 */ | |
1403 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1404 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, | |
1405 | .revision = 0x03, | |
1406 | .irq_pin = 1, | |
1407 | .unplug = false, | |
1408 | },{ | |
1409 | .name = "ich9-usb-uhci6", /* 00:1a.2 */ | |
1410 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1411 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, | |
1412 | .revision = 0x03, | |
1413 | .irq_pin = 2, | |
1414 | .unplug = false, | |
2c2e8525 | 1415 | } |
6cf9b6f1 | 1416 | }; |
afcc3cdf | 1417 | |
83f7d43a | 1418 | static void uhci_register_types(void) |
6cf9b6f1 | 1419 | { |
2c2e8525 | 1420 | TypeInfo uhci_type_info = { |
49184b62 GA |
1421 | .parent = TYPE_UHCI, |
1422 | .class_init = uhci_data_class_init, | |
2c2e8525 GH |
1423 | }; |
1424 | int i; | |
1425 | ||
49184b62 GA |
1426 | type_register_static(&uhci_pci_type_info); |
1427 | ||
2c2e8525 GH |
1428 | for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { |
1429 | uhci_type_info.name = uhci_info[i].name; | |
1430 | uhci_type_info.class_data = uhci_info + i; | |
1431 | type_register(&uhci_type_info); | |
1432 | } | |
6cf9b6f1 | 1433 | } |
83f7d43a AF |
1434 | |
1435 | type_init(uhci_register_types) |