[people/ms/u-boot.git] / include / asm-arm / arch-mx27 / imx-regs.h

/*
 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _IMX_REGS_H
#define _IMX_REGS_H

#ifndef __ASSEMBLY__

extern void imx_gpio_mode (int gpio_mode);

#ifdef CONFIG_MXC_UART
extern void mx27_uart_init_pins(void);
#endif /* CONFIG_MXC_UART */

#ifdef CONFIG_FEC_MXC
extern void mx27_fec_init_pins(void);
#endif /* CONFIG_FEC_MXC */

#ifdef CONFIG_MXC_MMC
extern void mx27_sd2_init_pins(void);
#endif /* CONFIG_MXC_MMC */

/* AIPI */
struct aipi_regs {
	u32 psr0;
	u32 psr1;
};

/* System Control */
struct system_control_regs {
	u32 res[5];
	u32 fmcr;
	u32 gpcr;
	u32 wbcr;
	u32 dscr1;
	u32 dscr2;
	u32 dscr3;
	u32 dscr4;
	u32 dscr5;
	u32 dscr6;
	u32 dscr7;
	u32 dscr8;
	u32 dscr9;
	u32 dscr10;
	u32 dscr11;
	u32 dscr12;
	u32 dscr13;
	u32 pscr;
	u32 pmcr;
	u32 res1;
	u32 dcvr0;
	u32 dcvr1;
	u32 dcvr2;
	u32 dcvr3;
};

/* Chip Select Registers */
struct weim_regs {
	u32 cs0u;	/* Chip Select 0 Upper Register */
	u32 cs0l;	/* Chip Select 0 Lower Register */
	u32 cs0a;	/* Chip Select 0 Addition Register */
	u32 pad0;
	u32 cs1u;	/* Chip Select 1 Upper Register */
	u32 cs1l;	/* Chip Select 1 Lower Register */
	u32 cs1a;	/* Chip Select 1 Addition Register */
	u32 pad1;
	u32 cs2u;	/* Chip Select 2 Upper Register */
	u32 cs2l;	/* Chip Select 2 Lower Register */
	u32 cs2a;	/* Chip Select 2 Addition Register */
	u32 pad2;
	u32 cs3u;	/* Chip Select 3 Upper Register */
	u32 cs3l;	/* Chip Select 3 Lower Register */
	u32 cs3a;	/* Chip Select 3 Addition Register */
	u32 pad3;
	u32 cs4u;	/* Chip Select 4 Upper Register */
	u32 cs4l;	/* Chip Select 4 Lower Register */
	u32 cs4a;	/* Chip Select 4 Addition Register */
	u32 pad4;
	u32 cs5u;	/* Chip Select 5 Upper Register */
	u32 cs5l;	/* Chip Select 5 Lower Register */
	u32 cs5a;	/* Chip Select 5 Addition Register */
	u32 pad5;
	u32 eim;	/* WEIM Configuration Register */
};

/* SDRAM Controller registers */
struct esdramc_regs {
/* Enhanced SDRAM Control Register 0 */
	u32 esdctl0;
/* Enhanced SDRAM Configuration Register 0 */
	u32 esdcfg0;
/* Enhanced SDRAM Control Register 1 */
	u32 esdctl1;
/* Enhanced SDRAM Configuration Register 1 */
	u32 esdcfg1;
/* Enhanced SDRAM Miscellanious Register */
	u32 esdmisc;
};

/* Watchdog Registers*/
struct wdog_regs {
	u32 wcr;
	u32 wsr;
	u32 wstr;
};

/* PLL registers */
struct pll_regs {
	u32 cscr;	/* Clock Source Control Register */
	u32 mpctl0;	/* MCU PLL Control Register 0 */
	u32 mpctl1;	/* MCU PLL Control Register 1 */
	u32 spctl0;	/* System PLL Control Register 0 */
	u32 spctl1;	/* System PLL Control Register 1 */
	u32 osc26mctl;	/* Oscillator 26M Register */
	u32 pcdr0;	/* Peripheral Clock Divider Register 0 */
	u32 pcdr1;	/* Peripheral Clock Divider Register 1 */
	u32 pccr0;	/* Peripheral Clock Control Register 0 */
	u32 pccr1;	/* Peripheral Clock Control Register 1 */
	u32 ccsr;	/* Clock Control Status Register */
};

/*
 * Definitions for the clocksource registers
 */
struct gpt_regs {
	u32 gpt_tctl;
	u32 gpt_tprer;
	u32 gpt_tcmp;
	u32 gpt_tcr;
	u32 gpt_tcn;
	u32 gpt_tstat;
};

/*
 *  GPIO Module and I/O Multiplexer
 */
#define PORTA 0
#define PORTB 1
#define PORTC 2
#define PORTD 3
#define PORTE 4
#define PORTF 5

struct gpio_regs {
	struct {
		u32 ddir;
		u32 ocr1;
		u32 ocr2;
		u32 iconfa1;
		u32 iconfa2;
		u32 iconfb1;
		u32 iconfb2;
		u32 dr;
		u32 gius;
		u32 ssr;
		u32 icr1;
		u32 icr2;
		u32 imr;
		u32 isr;
		u32 gpr;
		u32 swr;
		u32 puen;
		u32 res[0x2f];
	} port[6];
};

/* IIM Control Registers */
struct iim_regs {
	u32 iim_stat;
	u32 iim_statm;
	u32 iim_err;
	u32 iim_emask;
	u32 iim_fctl;
	u32 iim_ua;
	u32 iim_la;
	u32 iim_sdat;
	u32 iim_prev;
	u32 iim_srev;
	u32 iim_prog_p;
	u32 iim_scs0;
	u32 iim_scs1;
	u32 iim_scs2;
	u32 iim_scs3;
	u32 res[0x1F0];
	u32 iim_bank_area0[0x100];
};
#endif

#define IMX_IO_BASE		0x10000000

#define IMX_AIPI1_BASE		(0x00000 + IMX_IO_BASE)
#define IMX_WDT_BASE		(0x02000 + IMX_IO_BASE)
#define IMX_TIM1_BASE		(0x03000 + IMX_IO_BASE)
#define IMX_TIM2_BASE		(0x04000 + IMX_IO_BASE)
#define IMX_TIM3_BASE		(0x05000 + IMX_IO_BASE)
#define IMX_UART1_BASE		(0x0a000 + IMX_IO_BASE)
#define IMX_UART2_BASE		(0x0b000 + IMX_IO_BASE)
#define IMX_UART3_BASE		(0x0c000 + IMX_IO_BASE)
#define IMX_UART4_BASE		(0x0d000 + IMX_IO_BASE)
#define IMX_I2C1_BASE		(0x12000 + IMX_IO_BASE)
#define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
#define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
#define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
#define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
#define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
#define IMX_I2C2_BASE		(0x1D000 + IMX_IO_BASE)
#define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
#define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
#define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)
#define IMX_SYSTEM_CTL_BASE	(0x27800 + IMX_IO_BASE)
#define IMX_IIM_BASE		(0x28000 + IMX_IO_BASE)
#define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)

#define IMX_ESD_BASE		(0xD8001000)
#define IMX_WEIM_BASE		(0xD8002000)

/* FMCR System Control bit definition*/
#define UART4_RXD_CTL	(1 << 25)
#define UART4_RTS_CTL	(1 << 24)
#define KP_COL6_CTL	(1 << 18)
#define KP_ROW7_CTL	(1 << 17)
#define KP_ROW6_CTL	(1 << 16)
#define PC_WAIT_B_CTL	(1 << 14)
#define PC_READY_CTL	(1 << 13)
#define PC_VS1_CTL	(1 << 12)
#define PC_VS2_CTL	(1 << 11)
#define PC_BVD1_CTL	(1 << 10)
#define PC_BVD2_CTL	(1 << 9)
#define IOS16_CTL	(1 << 8)
#define NF_FMS		(1 << 5)
#define NF_16BIT_SEL	(1 << 4)
#define SLCDC_SEL	(1 << 2)
#define SDCS1_SEL	(1 << 1)
#define SDCS0_SEL	(1 << 0)


/* important definition of some bits of WCR */
#define WCR_WDE 0x04

#define CSCR_MPEN		(1 << 0)
#define CSCR_SPEN		(1 << 1)
#define CSCR_FPM_EN		(1 << 2)
#define CSCR_OSC26M_DIS		(1 << 3)
#define CSCR_OSC26M_DIV1P5	(1 << 4)
#define CSCR_AHB_DIV
#define CSCR_ARM_DIV
#define CSCR_ARM_SRC_MPLL	(1 << 15)
#define CSCR_MCU_SEL		(1 << 16)
#define CSCR_SP_SEL		(1 << 17)
#define CSCR_MPLL_RESTART	(1 << 18)
#define CSCR_SPLL_RESTART	(1 << 19)
#define CSCR_MSHC_SEL		(1 << 20)
#define CSCR_H264_SEL		(1 << 21)
#define CSCR_SSI1_SEL		(1 << 22)
#define CSCR_SSI2_SEL		(1 << 23)
#define CSCR_SD_CNT
#define CSCR_USB_DIV
#define CSCR_UPDATE_DIS		(1 << 31)

#define MPCTL1_BRMO		(1 << 6)
#define MPCTL1_LF		(1 << 15)

#define PCCR0_SSI2_EN	(1 << 0)
#define PCCR0_SSI1_EN	(1 << 1)
#define PCCR0_SLCDC_EN	(1 << 2)
#define PCCR0_SDHC3_EN	(1 << 3)
#define PCCR0_SDHC2_EN	(1 << 4)
#define PCCR0_SDHC1_EN	(1 << 5)
#define PCCR0_SDC_EN	(1 << 6)
#define PCCR0_SAHARA_EN	(1 << 7)
#define PCCR0_RTIC_EN	(1 << 8)
#define PCCR0_RTC_EN	(1 << 9)
#define PCCR0_PWM_EN	(1 << 11)
#define PCCR0_OWIRE_EN	(1 << 12)
#define PCCR0_MSHC_EN	(1 << 13)
#define PCCR0_LCDC_EN	(1 << 14)
#define PCCR0_KPP_EN	(1 << 15)
#define PCCR0_IIM_EN	(1 << 16)
#define PCCR0_I2C2_EN	(1 << 17)
#define PCCR0_I2C1_EN	(1 << 18)
#define PCCR0_GPT6_EN	(1 << 19)
#define PCCR0_GPT5_EN	(1 << 20)
#define PCCR0_GPT4_EN	(1 << 21)
#define PCCR0_GPT3_EN	(1 << 22)
#define PCCR0_GPT2_EN	(1 << 23)
#define PCCR0_GPT1_EN	(1 << 24)
#define PCCR0_GPIO_EN	(1 << 25)
#define PCCR0_FEC_EN	(1 << 26)
#define PCCR0_EMMA_EN	(1 << 27)
#define PCCR0_DMA_EN	(1 << 28)
#define PCCR0_CSPI3_EN	(1 << 29)
#define PCCR0_CSPI2_EN	(1 << 30)
#define PCCR0_CSPI1_EN	(1 << 31)

#define PCCR1_MSHC_BAUDEN	(1 << 2)
#define PCCR1_NFC_BAUDEN	(1 << 3)
#define PCCR1_SSI2_BAUDEN	(1 << 4)
#define PCCR1_SSI1_BAUDEN	(1 << 5)
#define PCCR1_H264_BAUDEN	(1 << 6)
#define PCCR1_PERCLK4_EN	(1 << 7)
#define PCCR1_PERCLK3_EN	(1 << 8)
#define PCCR1_PERCLK2_EN	(1 << 9)
#define PCCR1_PERCLK1_EN	(1 << 10)
#define PCCR1_HCLK_USB		(1 << 11)
#define PCCR1_HCLK_SLCDC	(1 << 12)
#define PCCR1_HCLK_SAHARA	(1 << 13)
#define PCCR1_HCLK_RTIC		(1 << 14)
#define PCCR1_HCLK_LCDC		(1 << 15)
#define PCCR1_HCLK_H264		(1 << 16)
#define PCCR1_HCLK_FEC		(1 << 17)
#define PCCR1_HCLK_EMMA		(1 << 18)
#define PCCR1_HCLK_EMI		(1 << 19)
#define PCCR1_HCLK_DMA		(1 << 20)
#define PCCR1_HCLK_CSI		(1 << 21)
#define PCCR1_HCLK_BROM		(1 << 22)
#define PCCR1_HCLK_ATA		(1 << 23)
#define PCCR1_WDT_EN		(1 << 24)
#define PCCR1_USB_EN		(1 << 25)
#define PCCR1_UART6_EN		(1 << 26)
#define PCCR1_UART5_EN		(1 << 27)
#define PCCR1_UART4_EN		(1 << 28)
#define PCCR1_UART3_EN		(1 << 29)
#define PCCR1_UART2_EN		(1 << 30)
#define PCCR1_UART1_EN		(1 << 31)

/* SDRAM Controller registers bitfields */
#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
#define ESDCTL_BL		(1 << 7)
#define ESDCTL_FP		(1 << 8)
#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
#define ESDCTL_DSIZ_32		(2 << 16)
#define ESDCTL_COL8		(0 << 20)
#define ESDCTL_COL9		(1 << 20)
#define ESDCTL_COL10		(2 << 20)
#define ESDCTL_ROW11		(0 << 24)
#define ESDCTL_ROW12		(1 << 24)
#define ESDCTL_ROW13		(2 << 24)
#define ESDCTL_ROW14		(3 << 24)
#define ESDCTL_ROW15		(4 << 24)
#define ESDCTL_SP		(1 << 27)
#define ESDCTL_SMODE_NORMAL	(0 << 28)
#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
#define ESDCTL_SMODE_MAN_REF	(4 << 28)
#define ESDCTL_SDE		(1 << 31)

#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
#define ESDCFG_TWR		(1 << 15)
#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
#define ESDCFG_TWTR		(1 << 20)
#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)

#define ESDMISC_RST		(1 << 1)
#define ESDMISC_MDDREN		(1 << 2)
#define ESDMISC_MDDR_DL_RST	(1 << 3)
#define ESDMISC_MDDR_MDIS	(1 << 4)
#define ESDMISC_LHD		(1 << 5)
#define ESDMISC_MA10_SHARE	(1 << 6)
#define ESDMISC_SDRAM_RDY	(1 << 31)

#define PC5_PF_I2C2_DATA	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
#define PC6_PF_I2C2_CLK		(GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
#define PC7_PF_USBOTG_DATA5	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
#define PC8_PF_USBOTG_DATA6	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
#define PC9_PF_USBOTG_DATA0	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
#define PC10_PF_USBOTG_DATA2	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
#define PC11_PF_USBOTG_DATA1	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
#define PC12_PF_USBOTG_DATA4	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
#define PC13_PF_USBOTG_DATA3	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)

#define PD0_AIN_FEC_TXD0	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
#define PD1_AIN_FEC_TXD1	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
#define PD2_AIN_FEC_TXD2	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
#define PD3_AIN_FEC_TXD3	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
#define PD4_AOUT_FEC_RX_ER	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
#define PD5_AOUT_FEC_RXD1	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
#define PD6_AOUT_FEC_RXD2	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
#define PD7_AOUT_FEC_RXD3	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
#define PD8_AF_FEC_MDIO		(GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
#define PD9_AIN_FEC_MDC		(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
#define PD10_AOUT_FEC_CRS	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
#define PD11_AOUT_FEC_TX_CLK	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
#define PD12_AOUT_FEC_RXD0	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
#define PD13_AOUT_FEC_RX_DV	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
#define PD14_AOUT_FEC_CLR	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
#define PD15_AOUT_FEC_COL	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
#define PD16_AIN_FEC_TX_ER	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
#define PF23_AIN_FEC_TX_EN	(GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)

#define PE0_PF_USBOTG_NXT	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
#define PE1_PF_USBOTG_STP	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
#define PE2_PF_USBOTG_DIR	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
#define PE3_PF_UART2_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
#define PE4_PF_UART2_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
#define PE6_PF_UART2_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
#define PE7_PF_UART2_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
#define PE8_PF_UART3_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
#define PE9_PF_UART3_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
#define PE10_PF_UART3_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
#define PE11_PF_UART3_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
#define PE12_PF_UART1_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
#define PE13_PF_UART1_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
#define PE14_PF_UART1_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
#define PE15_PF_UART1_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
#define PE18_PF_SD1_D0		(GPIO_PORTE | GPIO_PF | 18)
#define PE19_PF_SD1_D1		(GPIO_PORTE | GPIO_PF | 19)
#define PE20_PF_SD1_D2		(GPIO_PORTE | GPIO_PF | 20)
#define PE21_PF_SD1_D3		(GPIO_PORTE | GPIO_PF | 21)
#define PE22_PF_SD1_CMD		(GPIO_PORTE | GPIO_PF | 22)
#define PE23_PF_SD1_CLK		(GPIO_PORTE | GPIO_PF | 23)
#define PB4_PF_SD2_D0		(GPIO_PORTB | GPIO_PF | 4)
#define PB5_PF_SD2_D1		(GPIO_PORTB | GPIO_PF | 5)
#define PB6_PF_SD2_D2		(GPIO_PORTB | GPIO_PF | 6)
#define PB7_PF_SD2_D3		(GPIO_PORTB | GPIO_PF | 7)
#define PB8_PF_SD2_CMD		(GPIO_PORTB | GPIO_PF | 8)
#define PB9_PF_SD2_CLK		(GPIO_PORTB | GPIO_PF | 9)
#define PD17_PF_I2C_DATA	(GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
#define PD18_PF_I2C_CLK		(GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
#define PE24_PF_USBOTG_CLK	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
#define PE25_PF_USBOTG_DATA7	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)

/* Clocksource Bitfields */
#define TCTL_SWR	(1 << 15)	/* Software reset */
#define TCTL_FRR	(1 << 8)	/* Freerun / restart */
#define TCTL_CAP	(3 << 6)	/* Capture Edge */
#define TCTL_OM		(1 << 5)	/* output mode */
#define TCTL_IRQEN	(1 << 4)	/* interrupt enable */
#define TCTL_CLKSOURCE	1		/* Clock source bit position */
#define TCTL_TEN	1		/* Timer enable */
#define TPRER_PRES	0xff		/* Prescale */
#define TSTAT_CAPT	(1 << 1)	/* Capture event */
#define TSTAT_COMP	1		/* Compare event */

#define GPIO_PIN_MASK	0x1f

#define GPIO_PORT_SHIFT	5
#define GPIO_PORT_MASK	(0x7 << GPIO_PORT_SHIFT)

#define GPIO_PORTA	(PORTA << GPIO_PORT_SHIFT)
#define GPIO_PORTB	(PORTB << GPIO_PORT_SHIFT)
#define GPIO_PORTC	(PORTC << GPIO_PORT_SHIFT)
#define GPIO_PORTD	(PORTD << GPIO_PORT_SHIFT)
#define GPIO_PORTE	(PORTE << GPIO_PORT_SHIFT)
#define GPIO_PORTF	(PORTF << GPIO_PORT_SHIFT)

#define GPIO_OUT	(1 << 8)
#define GPIO_IN		(0 << 8)
#define GPIO_PUEN	(1 << 9)

#define GPIO_PF		(1 << 10)
#define GPIO_AF		(1 << 11)

#define GPIO_OCR_SHIFT	12
#define GPIO_OCR_MASK	(3 << GPIO_OCR_SHIFT)
#define GPIO_AIN	(0 << GPIO_OCR_SHIFT)
#define GPIO_BIN	(1 << GPIO_OCR_SHIFT)
#define GPIO_CIN	(2 << GPIO_OCR_SHIFT)
#define GPIO_GPIO	(3 << GPIO_OCR_SHIFT)

#define GPIO_AOUT_SHIFT	14
#define GPIO_AOUT_MASK	(3 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT	(0 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_ISR	(1 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_0	(2 << GPIO_AOUT_SHIFT)
#define GPIO_AOUT_1	(3 << GPIO_AOUT_SHIFT)

#define GPIO_BOUT_SHIFT	16
#define GPIO_BOUT_MASK	(3 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT	(0 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_ISR	(1 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_0	(2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1	(3 << GPIO_BOUT_SHIFT)

#define IIM_STAT_BUSY	(1 << 7)
#define IIM_STAT_PRGD	(1 << 1)
#define IIM_STAT_SNSD	(1 << 0)
#define IIM_ERR_PRGE	(1 << 7)
#define IIM_ERR_WPE	(1 << 6)
#define IIM_ERR_OPE	(1 << 5)
#define IIM_ERR_RPE	(1 << 4)
#define IIM_ERR_WLRE	(1 << 3)
#define IIM_ERR_SNSE	(1 << 2)
#define IIM_ERR_PARITYE	(1 << 1)

/* Definitions for i.MX27 TO2 */
#define IIM0_MAC		5
#define IIM0_SCC_KEY		11
#define IIM1_SUID		1

#endif				/* _IMX_REGS_H */
Commit	Line	Data
1dc4da74	1	/*
1dc4da74 IY	2	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
	3	* (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef _IMX_REGS_H
	25	#define _IMX_REGS_H
	26
	27	#ifndef __ASSEMBLY__
	28
	29	extern void imx_gpio_mode (int gpio_mode);
	30
10bc241d IY	31	#ifdef CONFIG_MXC_UART
	32	extern void mx27_uart_init_pins(void);
	33	#endif /* CONFIG_MXC_UART */
	34
	35	#ifdef CONFIG_FEC_MXC
	36	extern void mx27_fec_init_pins(void);
	37	#endif /* CONFIG_FEC_MXC */
	38
	39	#ifdef CONFIG_MXC_MMC
	40	extern void mx27_sd2_init_pins(void);
	41	#endif /* CONFIG_MXC_MMC */
	42
1dc4da74 IY	43	/* AIPI */
	44	struct aipi_regs {
	45	u32 psr0;
	46	u32 psr1;
	47	};
	48
	49	/* System Control */
	50	struct system_control_regs {
	51	u32 res[5];
	52	u32 fmcr;
	53	u32 gpcr;
	54	u32 wbcr;
	55	u32 dscr1;
	56	u32 dscr2;
	57	u32 dscr3;
	58	u32 dscr4;
	59	u32 dscr5;
	60	u32 dscr6;
	61	u32 dscr7;
	62	u32 dscr8;
	63	u32 dscr9;
	64	u32 dscr10;
	65	u32 dscr11;
	66	u32 dscr12;
	67	u32 dscr13;
	68	u32 pscr;
	69	u32 pmcr;
	70	u32 res1;
	71	u32 dcvr0;
	72	u32 dcvr1;
	73	u32 dcvr2;
	74	u32 dcvr3;
	75	};
	76
	77	/* Chip Select Registers */
	78	struct weim_regs {
	79	u32 cs0u; /* Chip Select 0 Upper Register */
	80	u32 cs0l; /* Chip Select 0 Lower Register */
	81	u32 cs0a; /* Chip Select 0 Addition Register */
	82	u32 pad0;
	83	u32 cs1u; /* Chip Select 1 Upper Register */
	84	u32 cs1l; /* Chip Select 1 Lower Register */
	85	u32 cs1a; /* Chip Select 1 Addition Register */
	86	u32 pad1;
	87	u32 cs2u; /* Chip Select 2 Upper Register */
	88	u32 cs2l; /* Chip Select 2 Lower Register */
	89	u32 cs2a; /* Chip Select 2 Addition Register */
	90	u32 pad2;
	91	u32 cs3u; /* Chip Select 3 Upper Register */
	92	u32 cs3l; /* Chip Select 3 Lower Register */
	93	u32 cs3a; /* Chip Select 3 Addition Register */
	94	u32 pad3;
	95	u32 cs4u; /* Chip Select 4 Upper Register */
	96	u32 cs4l; /* Chip Select 4 Lower Register */
	97	u32 cs4a; /* Chip Select 4 Addition Register */
	98	u32 pad4;
	99	u32 cs5u; /* Chip Select 5 Upper Register */
	100	u32 cs5l; /* Chip Select 5 Lower Register */
	101	u32 cs5a; /* Chip Select 5 Addition Register */
	102	u32 pad5;
	103	u32 eim; /* WEIM Configuration Register */
	104	};
	105
	106	/* SDRAM Controller registers */
107	struct esdramc_regs {
108	/* Enhanced SDRAM Control Register 0 */
109	u32 esdctl0;
110	/* Enhanced SDRAM Configuration Register 0 */
111	u32 esdcfg0;
112	/* Enhanced SDRAM Control Register 1 */
113	u32 esdctl1;
114	/* Enhanced SDRAM Configuration Register 1 */
115	u32 esdcfg1;
116	/* Enhanced SDRAM Miscellanious Register */
117	u32 esdmisc;
118	};
119
120	/* Watchdog Registers*/
121	struct wdog_regs {
122	u32 wcr;
123	u32 wsr;
124	u32 wstr;
125	};
126
127	/* PLL registers */
128	struct pll_regs {
129	u32 cscr; /* Clock Source Control Register */
130	u32 mpctl0; /* MCU PLL Control Register 0 */
131	u32 mpctl1; /* MCU PLL Control Register 1 */
132	u32 spctl0; /* System PLL Control Register 0 */
133	u32 spctl1; /* System PLL Control Register 1 */
134	u32 osc26mctl; /* Oscillator 26M Register */
135	u32 pcdr0; /* Peripheral Clock Divider Register 0 */
136	u32 pcdr1; /* Peripheral Clock Divider Register 1 */
137	u32 pccr0; /* Peripheral Clock Control Register 0 */
138	u32 pccr1; /* Peripheral Clock Control Register 1 */
139	u32 ccsr; /* Clock Control Status Register */
140	};
141
142	/*
143	* Definitions for the clocksource registers
144	*/
145	struct gpt_regs {
146	u32 gpt_tctl;
147	u32 gpt_tprer;
148	u32 gpt_tcmp;
149	u32 gpt_tcr;
150	u32 gpt_tcn;
151	u32 gpt_tstat;
152	};
153
154	/*
155	* GPIO Module and I/O Multiplexer
156	*/
157	#define PORTA 0
158	#define PORTB 1
159	#define PORTC 2
160	#define PORTD 3
161	#define PORTE 4
162	#define PORTF 5
163
164	struct gpio_regs {
165	struct {
166	u32 ddir;
167	u32 ocr1;
168	u32 ocr2;
169	u32 iconfa1;
170	u32 iconfa2;
171	u32 iconfb1;
172	u32 iconfb2;
173	u32 dr;
174	u32 gius;
175	u32 ssr;
176	u32 icr1;
177	u32 icr2;
178	u32 imr;
179	u32 isr;
180	u32 gpr;
181	u32 swr;
182	u32 puen;
183	u32 res[0x2f];
184	} port[6];
185	};
186
187	/* IIM Control Registers */
188	struct iim_regs {
189	u32 iim_stat;
190	u32 iim_statm;
191	u32 iim_err;
192	u32 iim_emask;
193	u32 iim_fctl;
194	u32 iim_ua;
195	u32 iim_la;
196	u32 iim_sdat;
197	u32 iim_prev;
198	u32 iim_srev;
199	u32 iim_prog_p;
200	u32 iim_scs0;
201	u32 iim_scs1;
202	u32 iim_scs2;
203	u32 iim_scs3;
204	u32 res[0x1F0];
205	u32 iim_bank_area0[0x100];
206	};
207	#endif
208
209	#define IMX_IO_BASE 0x10000000
210
211	#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
212	#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
213	#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
214	#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
215	#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
216	#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
217	#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
218	#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
219	#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
220	#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
221	#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
222	#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
223	#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
224	#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
225	#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
226	#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
227	#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
228	#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
229	#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
230	#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
231	#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
232	#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
233
234	#define IMX_ESD_BASE (0xD8001000)
235	#define IMX_WEIM_BASE (0xD8002000)
236
237	/* FMCR System Control bit definition*/
238	#define UART4_RXD_CTL (1 << 25)
239	#define UART4_RTS_CTL (1 << 24)
240	#define KP_COL6_CTL (1 << 18)
241	#define KP_ROW7_CTL (1 << 17)
242	#define KP_ROW6_CTL (1 << 16)
243	#define PC_WAIT_B_CTL (1 << 14)
244	#define PC_READY_CTL (1 << 13)
245	#define PC_VS1_CTL (1 << 12)
246	#define PC_VS2_CTL (1 << 11)
247	#define PC_BVD1_CTL (1 << 10)
248	#define PC_BVD2_CTL (1 << 9)
249	#define IOS16_CTL (1 << 8)
250	#define NF_FMS (1 << 5)
251	#define NF_16BIT_SEL (1 << 4)
252	#define SLCDC_SEL (1 << 2)
253	#define SDCS1_SEL (1 << 1)
254	#define SDCS0_SEL (1 << 0)
255
256
257	/* important definition of some bits of WCR */
258	#define WCR_WDE 0x04
259
260	#define CSCR_MPEN (1 << 0)
261	#define CSCR_SPEN (1 << 1)
262	#define CSCR_FPM_EN (1 << 2)
263	#define CSCR_OSC26M_DIS (1 << 3)
264	#define CSCR_OSC26M_DIV1P5 (1 << 4)
265	#define CSCR_AHB_DIV
266	#define CSCR_ARM_DIV
267	#define CSCR_ARM_SRC_MPLL (1 << 15)
268	#define CSCR_MCU_SEL (1 << 16)
269	#define CSCR_SP_SEL (1 << 17)
270	#define CSCR_MPLL_RESTART (1 << 18)
271	#define CSCR_SPLL_RESTART (1 << 19)
272	#define CSCR_MSHC_SEL (1 << 20)
273	#define CSCR_H264_SEL (1 << 21)
274	#define CSCR_SSI1_SEL (1 << 22)
275	#define CSCR_SSI2_SEL (1 << 23)
276	#define CSCR_SD_CNT
277	#define CSCR_USB_DIV
278	#define CSCR_UPDATE_DIS (1 << 31)
279
280	#define MPCTL1_BRMO (1 << 6)
281	#define MPCTL1_LF (1 << 15)
282
283	#define PCCR0_SSI2_EN (1 << 0)
284	#define PCCR0_SSI1_EN (1 << 1)
285	#define PCCR0_SLCDC_EN (1 << 2)
286	#define PCCR0_SDHC3_EN (1 << 3)
287	#define PCCR0_SDHC2_EN (1 << 4)
288	#define PCCR0_SDHC1_EN (1 << 5)
289	#define PCCR0_SDC_EN (1 << 6)
290	#define PCCR0_SAHARA_EN (1 << 7)
291	#define PCCR0_RTIC_EN (1 << 8)
292	#define PCCR0_RTC_EN (1 << 9)
293	#define PCCR0_PWM_EN (1 << 11)
294	#define PCCR0_OWIRE_EN (1 << 12)
295	#define PCCR0_MSHC_EN (1 << 13)
296	#define PCCR0_LCDC_EN (1 << 14)
297	#define PCCR0_KPP_EN (1 << 15)
298	#define PCCR0_IIM_EN (1 << 16)
299	#define PCCR0_I2C2_EN (1 << 17)
300	#define PCCR0_I2C1_EN (1 << 18)
301	#define PCCR0_GPT6_EN (1 << 19)
302	#define PCCR0_GPT5_EN (1 << 20)
303	#define PCCR0_GPT4_EN (1 << 21)
304	#define PCCR0_GPT3_EN (1 << 22)
305	#define PCCR0_GPT2_EN (1 << 23)
306	#define PCCR0_GPT1_EN (1 << 24)
307	#define PCCR0_GPIO_EN (1 << 25)
308	#define PCCR0_FEC_EN (1 << 26)
309	#define PCCR0_EMMA_EN (1 << 27)
310	#define PCCR0_DMA_EN (1 << 28)
311	#define PCCR0_CSPI3_EN (1 << 29)
312	#define PCCR0_CSPI2_EN (1 << 30)
313	#define PCCR0_CSPI1_EN (1 << 31)
314
315	#define PCCR1_MSHC_BAUDEN (1 << 2)
316	#define PCCR1_NFC_BAUDEN (1 << 3)
317	#define PCCR1_SSI2_BAUDEN (1 << 4)
318	#define PCCR1_SSI1_BAUDEN (1 << 5)
319	#define PCCR1_H264_BAUDEN (1 << 6)
320	#define PCCR1_PERCLK4_EN (1 << 7)
321	#define PCCR1_PERCLK3_EN (1 << 8)
322	#define PCCR1_PERCLK2_EN (1 << 9)
323	#define PCCR1_PERCLK1_EN (1 << 10)
324	#define PCCR1_HCLK_USB (1 << 11)
325	#define PCCR1_HCLK_SLCDC (1 << 12)
326	#define PCCR1_HCLK_SAHARA (1 << 13)
327	#define PCCR1_HCLK_RTIC (1 << 14)
328	#define PCCR1_HCLK_LCDC (1 << 15)
329	#define PCCR1_HCLK_H264 (1 << 16)
330	#define PCCR1_HCLK_FEC (1 << 17)
331	#define PCCR1_HCLK_EMMA (1 << 18)
332	#define PCCR1_HCLK_EMI (1 << 19)
333	#define PCCR1_HCLK_DMA (1 << 20)
334	#define PCCR1_HCLK_CSI (1 << 21)
335	#define PCCR1_HCLK_BROM (1 << 22)
336	#define PCCR1_HCLK_ATA (1 << 23)
337	#define PCCR1_WDT_EN (1 << 24)
338	#define PCCR1_USB_EN (1 << 25)
339	#define PCCR1_UART6_EN (1 << 26)
340	#define PCCR1_UART5_EN (1 << 27)
341	#define PCCR1_UART4_EN (1 << 28)
342	#define PCCR1_UART3_EN (1 << 29)
343	#define PCCR1_UART2_EN (1 << 30)
344	#define PCCR1_UART1_EN (1 << 31)
345
346	/* SDRAM Controller registers bitfields */
347	#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
348	#define ESDCTL_BL (1 << 7)
349	#define ESDCTL_FP (1 << 8)
350	#define ESDCTL_PWDT(x) (((x) & 3) << 10)
351	#define ESDCTL_SREFR(x) (((x) & 7) << 13)
352	#define ESDCTL_DSIZ_16_UPPER (0 << 16)
353	#define ESDCTL_DSIZ_16_LOWER (1 << 16)
354	#define ESDCTL_DSIZ_32 (2 << 16)
355	#define ESDCTL_COL8 (0 << 20)
356	#define ESDCTL_COL9 (1 << 20)
357	#define ESDCTL_COL10 (2 << 20)
358	#define ESDCTL_ROW11 (0 << 24)
359	#define ESDCTL_ROW12 (1 << 24)
360	#define ESDCTL_ROW13 (2 << 24)
361	#define ESDCTL_ROW14 (3 << 24)
362	#define ESDCTL_ROW15 (4 << 24)
363	#define ESDCTL_SP (1 << 27)
364	#define ESDCTL_SMODE_NORMAL (0 << 28)
365	#define ESDCTL_SMODE_PRECHARGE (1 << 28)
366	#define ESDCTL_SMODE_AUTO_REF (2 << 28)
367	#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
368	#define ESDCTL_SMODE_MAN_REF (4 << 28)
369	#define ESDCTL_SDE (1 << 31)
370
371	#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
372	#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
373	#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
374	#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
375	#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
376	#define ESDCFG_TWR (1 << 15)
377	#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
378	#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
379	#define ESDCFG_TWTR (1 << 20)
380	#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
381
382	#define ESDMISC_RST (1 << 1)
383	#define ESDMISC_MDDREN (1 << 2)
384	#define ESDMISC_MDDR_DL_RST (1 << 3)
385	#define ESDMISC_MDDR_MDIS (1 << 4)
386	#define ESDMISC_LHD (1 << 5)
387	#define ESDMISC_MA10_SHARE (1 << 6)
388	#define ESDMISC_SDRAM_RDY (1 << 31)
389
390	#define PC5_PF_I2C2_DATA (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 5)
391	#define PC6_PF_I2C2_CLK (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 6)
392	#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 7)
393	#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 8)
394	#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 9)
395	#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 10)
396	#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 11)
397	#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 12)
398	#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC \| GPIO_OUT \| GPIO_PF \| 13)
399
400	#define PD0_AIN_FEC_TXD0 (GPIO_PORTD \| GPIO_OUT \| GPIO_AIN \| 0)
401	#define PD1_AIN_FEC_TXD1 (GPIO_PORTD \| GPIO_OUT \| GPIO_AIN \| 1)
402	#define PD2_AIN_FEC_TXD2 (GPIO_PORTD \| GPIO_OUT \| GPIO_AIN \| 2)
403	#define PD3_AIN_FEC_TXD3 (GPIO_PORTD \| GPIO_OUT \| GPIO_AIN \| 3)
404	#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 4)
405	#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 5)
406	#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 6)
407	#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 7)
408	#define PD8_AF_FEC_MDIO (GPIO_PORTD \| GPIO_IN \| GPIO_AF \| 8)
409	#define PD9_AIN_FEC_MDC (GPIO_PORTD \| GPIO_OUT \| GPIO_AIN \| 9)
410	#define PD10_AOUT_FEC_CRS (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 10)
411	#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 11)
412	#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 12)
413	#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 13)
414	#define PD14_AOUT_FEC_CLR (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 14)
415	#define PD15_AOUT_FEC_COL (GPIO_PORTD \| GPIO_IN \| GPIO_AOUT \| 15)
416	#define PD16_AIN_FEC_TX_ER (GPIO_PORTD \| GPIO_OUT \| GPIO_AIN \| 16)
417	#define PF23_AIN_FEC_TX_EN (GPIO_PORTF \| GPIO_OUT \| GPIO_AIN \| 23)
418
419	#define PE0_PF_USBOTG_NXT (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 0)
420	#define PE1_PF_USBOTG_STP (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 1)
421	#define PE2_PF_USBOTG_DIR (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 2)
422	#define PE3_PF_UART2_CTS (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 3)
423	#define PE4_PF_UART2_RTS (GPIO_PORTE \| GPIO_IN \| GPIO_PF \| 4)
424	#define PE6_PF_UART2_TXD (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 6)
425	#define PE7_PF_UART2_RXD (GPIO_PORTE \| GPIO_IN \| GPIO_PF \| 7)
426	#define PE8_PF_UART3_TXD (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 8)
427	#define PE9_PF_UART3_RXD (GPIO_PORTE \| GPIO_IN \| GPIO_PF \| 9)
428	#define PE10_PF_UART3_CTS (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 10)
429	#define PE11_PF_UART3_RTS (GPIO_PORTE \| GPIO_IN \| GPIO_PF \| 11)
430	#define PE12_PF_UART1_TXD (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 12)
431	#define PE13_PF_UART1_RXD (GPIO_PORTE \| GPIO_IN \| GPIO_PF \| 13)
432	#define PE14_PF_UART1_CTS (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 14)
433	#define PE15_PF_UART1_RTS (GPIO_PORTE \| GPIO_IN \| GPIO_PF \| 15)
434	#define PE18_PF_SD1_D0 (GPIO_PORTE \| GPIO_PF \| 18)
435	#define PE19_PF_SD1_D1 (GPIO_PORTE \| GPIO_PF \| 19)
436	#define PE20_PF_SD1_D2 (GPIO_PORTE \| GPIO_PF \| 20)
437	#define PE21_PF_SD1_D3 (GPIO_PORTE \| GPIO_PF \| 21)
438	#define PE22_PF_SD1_CMD (GPIO_PORTE \| GPIO_PF \| 22)
439	#define PE23_PF_SD1_CLK (GPIO_PORTE \| GPIO_PF \| 23)
440	#define PB4_PF_SD2_D0 (GPIO_PORTB \| GPIO_PF \| 4)
441	#define PB5_PF_SD2_D1 (GPIO_PORTB \| GPIO_PF \| 5)
442	#define PB6_PF_SD2_D2 (GPIO_PORTB \| GPIO_PF \| 6)
443	#define PB7_PF_SD2_D3 (GPIO_PORTB \| GPIO_PF \| 7)
444	#define PB8_PF_SD2_CMD (GPIO_PORTB \| GPIO_PF \| 8)
445	#define PB9_PF_SD2_CLK (GPIO_PORTB \| GPIO_PF \| 9)
446	#define PD17_PF_I2C_DATA (GPIO_PORTD \| GPIO_OUT \| GPIO_PF \| 17)
447	#define PD18_PF_I2C_CLK (GPIO_PORTD \| GPIO_OUT \| GPIO_PF \| 18)
448	#define PE24_PF_USBOTG_CLK (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 24)
449	#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE \| GPIO_OUT \| GPIO_PF \| 25)
450
451	/* Clocksource Bitfields */
452	#define TCTL_SWR (1 << 15) /* Software reset */
453	#define TCTL_FRR (1 << 8) /* Freerun / restart */
454	#define TCTL_CAP (3 << 6) /* Capture Edge */
455	#define TCTL_OM (1 << 5) /* output mode */
456	#define TCTL_IRQEN (1 << 4) /* interrupt enable */
457	#define TCTL_CLKSOURCE 1 /* Clock source bit position */
458	#define TCTL_TEN 1 /* Timer enable */
459	#define TPRER_PRES 0xff /* Prescale */
460	#define TSTAT_CAPT (1 << 1) /* Capture event */
461	#define TSTAT_COMP 1 /* Compare event */
462
463	#define GPIO_PIN_MASK 0x1f
464
465	#define GPIO_PORT_SHIFT 5
466	#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
467
468	#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
469	#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
470	#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
471	#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
472	#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
473	#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
474
475	#define GPIO_OUT (1 << 8)
476	#define GPIO_IN (0 << 8)
477	#define GPIO_PUEN (1 << 9)
478
479	#define GPIO_PF (1 << 10)
480	#define GPIO_AF (1 << 11)
481
482	#define GPIO_OCR_SHIFT 12
483	#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
484	#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
485	#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
486	#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
487	#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
488
489	#define GPIO_AOUT_SHIFT 14
490	#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
491	#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
492	#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
493	#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
494	#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
495
496	#define GPIO_BOUT_SHIFT 16
497	#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
498	#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
499	#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
500	#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
501	#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
502
503	#define IIM_STAT_BUSY (1 << 7)
504	#define IIM_STAT_PRGD (1 << 1)
505	#define IIM_STAT_SNSD (1 << 0)
506	#define IIM_ERR_PRGE (1 << 7)
507	#define IIM_ERR_WPE (1 << 6)
508	#define IIM_ERR_OPE (1 << 5)
509	#define IIM_ERR_RPE (1 << 4)
510	#define IIM_ERR_WLRE (1 << 3)
511	#define IIM_ERR_SNSE (1 << 2)
512	#define IIM_ERR_PARITYE (1 << 1)
513
514	/* Definitions for i.MX27 TO2 */
515	#define IIM0_MAC 5
516	#define IIM0_SCC_KEY 11
517	#define IIM1_SUID 1
518
519	#endif /* _IMX_REGS_H */