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8ed96046 WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef _OMAP2420_SYS_H_ | |
26 | #define _OMAP2420_SYS_H_ | |
27 | ||
28 | #include <asm/arch/sizes.h> | |
29 | ||
30 | /* | |
31 | * 2420 specific Section | |
32 | */ | |
33 | ||
c97a2aaf WD |
34 | /* L3 Firewall */ |
35 | #define A_REQINFOPERM0 0x68005048 | |
36 | #define A_READPERM0 0x68005050 | |
37 | #define A_WRITEPERM0 0x68005058 | |
b8e16a34 | 38 | /* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ |
c97a2aaf | 39 | |
49a7581c WD |
40 | /* L3 Firewall */ |
41 | #define A_REQINFOPERM0 0x68005048 | |
42 | #define A_READPERM0 0x68005050 | |
43 | #define A_WRITEPERM0 0x68005058 | |
44 | ||
8ed96046 WD |
45 | /* CONTROL */ |
46 | #define OMAP2420_CTRL_BASE (0x48000000) | |
47 | #define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) | |
48 | ||
49a7581c WD |
49 | /* device type */ |
50 | #define TST_DEVICE 0x0 | |
51 | #define EMU_DEVICE 0x1 | |
52 | #define HS_DEVICE 0x2 | |
53 | #define GP_DEVICE 0x3 | |
54 | ||
8ed96046 WD |
55 | /* TAP information */ |
56 | #define OMAP2420_TAP_BASE (0x48014000) | |
57 | #define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) | |
49a7581c | 58 | #define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) |
8ed96046 WD |
59 | |
60 | /* GPMC */ | |
61 | #define OMAP2420_GPMC_BASE (0x6800A000) | |
62 | #define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) | |
63 | #define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) | |
64 | #define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) | |
65 | #define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) | |
66 | #define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) | |
67 | #define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) | |
68 | #define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) | |
69 | #define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) | |
70 | #define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) | |
289f932c | 71 | #define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) |
8ed96046 WD |
72 | #define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) |
73 | #define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) | |
74 | #define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) | |
75 | #define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) | |
76 | #define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) | |
77 | #define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) | |
78 | #define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) | |
79 | #define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) | |
5ca9881a PP |
80 | #define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) |
81 | #define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) | |
82 | #define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) | |
83 | #define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) | |
84 | #define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) | |
85 | #define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) | |
86 | #define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) | |
87 | #define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) | |
88 | #define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) | |
89 | #define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) | |
90 | #define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) | |
91 | #define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) | |
92 | #define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) | |
93 | #define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) | |
8ed96046 WD |
94 | |
95 | /* SMS */ | |
96 | #define OMAP2420_SMS_BASE 0x68008000 | |
97 | #define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) | |
289f932c WD |
98 | #define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) |
99 | # define BURSTCOMPLETE_GROUP7 BIT31 | |
8ed96046 WD |
100 | |
101 | /* SDRC */ | |
102 | #define OMAP2420_SDRC_BASE 0x68009000 | |
103 | #define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) | |
104 | #define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) | |
49a7581c | 105 | #define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) |
8ed96046 WD |
106 | #define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) |
107 | #define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) | |
108 | #define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) | |
109 | #define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) | |
110 | #define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) | |
111 | #define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) | |
112 | #define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) | |
113 | #define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) | |
114 | #define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) | |
115 | #define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) | |
116 | #define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) | |
117 | #define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) | |
118 | #define OMAP2420_SDRC_CS0 0x80000000 | |
119 | #define OMAP2420_SDRC_CS1 0xA0000000 | |
120 | #define CMD_NOP 0x0 | |
121 | #define CMD_PRECHARGE 0x1 | |
122 | #define CMD_AUTOREFRESH 0x2 | |
123 | #define CMD_ENTR_PWRDOWN 0x3 | |
124 | #define CMD_EXIT_PWRDOWN 0x4 | |
125 | #define CMD_ENTR_SRFRSH 0x5 | |
126 | #define CMD_CKE_HIGH 0x6 | |
127 | #define CMD_CKE_LOW 0x7 | |
128 | #define SOFTRESET BIT1 | |
129 | #define SMART_IDLE (0x2 << 3) | |
130 | #define REF_ON_IDLE (0x1 << 6) | |
131 | ||
132 | ||
133 | /* UART */ | |
134 | #define OMAP2420_UART1 0x4806A000 | |
135 | #define OMAP2420_UART2 0x4806C000 | |
136 | #define OMAP2420_UART3 0x4806E000 | |
137 | ||
138 | /* General Purpose Timers */ | |
139 | #define OMAP2420_GPT1 0x48028000 | |
140 | #define OMAP2420_GPT2 0x4802A000 | |
141 | #define OMAP2420_GPT3 0x48078000 | |
142 | #define OMAP2420_GPT4 0x4807A000 | |
143 | #define OMAP2420_GPT5 0x4807C000 | |
144 | #define OMAP2420_GPT6 0x4807E000 | |
145 | #define OMAP2420_GPT7 0x48080000 | |
146 | #define OMAP2420_GPT8 0x48082000 | |
147 | #define OMAP2420_GPT9 0x48084000 | |
148 | #define OMAP2420_GPT10 0x48086000 | |
149 | #define OMAP2420_GPT11 0x48088000 | |
150 | #define OMAP2420_GPT12 0x4808A000 | |
151 | ||
152 | /* timer regs offsets (32 bit regs) */ | |
153 | #define TIDR 0x0 /* r */ | |
154 | #define TIOCP_CFG 0x10 /* rw */ | |
155 | #define TISTAT 0x14 /* r */ | |
156 | #define TISR 0x18 /* rw */ | |
157 | #define TIER 0x1C /* rw */ | |
158 | #define TWER 0x20 /* rw */ | |
159 | #define TCLR 0x24 /* rw */ | |
160 | #define TCRR 0x28 /* rw */ | |
161 | #define TLDR 0x2C /* rw */ | |
162 | #define TTGR 0x30 /* rw */ | |
163 | #define TWPS 0x34 /* r */ | |
164 | #define TMAR 0x38 /* rw */ | |
165 | #define TCAR1 0x3c /* r */ | |
166 | #define TSICR 0x40 /* rw */ | |
167 | #define TCAR2 0x44 /* r */ | |
168 | ||
169 | /* WatchDog Timers (1 secure, 3 GP) */ | |
170 | #define WD1_BASE 0x48020000 | |
171 | #define WD2_BASE 0x48022000 | |
172 | #define WD3_BASE 0x48024000 | |
173 | #define WD4_BASE 0x48026000 | |
174 | #define WWPS 0x34 /* r */ | |
175 | #define WSPR 0x48 /* rw */ | |
176 | #define WD_UNLOCK1 0xAAAA | |
177 | #define WD_UNLOCK2 0x5555 | |
178 | ||
179 | /* PRCM */ | |
180 | #define OMAP2420_CM_BASE 0x48008000 | |
181 | #define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) | |
182 | #define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) | |
183 | #define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) | |
184 | #define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) | |
185 | #define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) | |
186 | #define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) | |
187 | #define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) | |
188 | #define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) | |
189 | #define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) | |
190 | #define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) | |
191 | #define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) | |
192 | #define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) | |
193 | #define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) | |
194 | #define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) | |
195 | #define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) | |
196 | #define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) | |
197 | ||
198 | /* | |
199 | * H4 specific Section | |
200 | */ | |
201 | ||
202 | /* | |
203 | * The 2420's chip selects are programmable. The mask ROM | |
204 | * does configure CS0 to 0x08000000 before dispatch. So, if | |
205 | * you want your code to live below that address, you have to | |
206 | * be prepared to jump though hoops, to reset the base address. | |
207 | */ | |
208 | #if defined(CONFIG_OMAP2420H4) | |
209 | /* GPMC */ | |
210 | #ifdef CONFIG_VIRTIO_A /* Pre version B */ | |
211 | # define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ | |
212 | # define H4_CS1_BASE 0x04000000 /* debug board */ | |
213 | # define H4_CS2_BASE 0x0A000000 /* wifi board */ | |
214 | #else | |
215 | # define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ | |
216 | # define H4_CS1_BASE 0x08000000 /* debug board */ | |
217 | # define H4_CS2_BASE 0x0A000000 /* wifi board */ | |
218 | #endif | |
219 | ||
220 | /* base address for indirect vectors (internal boot mode) */ | |
221 | #define SRAM_OFFSET0 0x40000000 | |
222 | #define SRAM_OFFSET1 0x00200000 | |
223 | #define SRAM_OFFSET2 0x0000F800 | |
224 | #define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) | |
225 | ||
8ed96046 WD |
226 | /* FPGA on Debug board.*/ |
227 | #define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) | |
228 | #define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) | |
229 | #endif /* endif CONFIG_2420H4 */ | |
230 | ||
5ca9881a PP |
231 | #if defined(CONFIG_APOLLON) |
232 | #define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ | |
233 | #define APOLLON_CS1_BASE 0x08000000 /* ethernet */ | |
234 | #define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ | |
235 | #define APOLLON_CS3_BASE 0x18000000 /* NOR */ | |
236 | ||
237 | #define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) | |
238 | #define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) | |
239 | #endif /* endif CONFIG_APOLLON */ | |
240 | ||
241 | /* Common */ | |
242 | #define LOW_LEVEL_SRAM_STACK 0x4020FFFC | |
243 | ||
244 | #define PERIFERAL_PORT_BASE 0x480FE003 | |
245 | ||
8ed96046 | 246 | #endif |