[people/ms/u-boot.git] / include / asm-arm / arch-omap3 / cpu.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments, <www.ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#ifndef _CPU_H
#define _CPU_H

/* Register offsets of common modules */
/* Control */
#ifndef __ASSEMBLY__
typedef struct ctrl {
	unsigned char res1[0xC0];
	unsigned short gpmc_nadv_ale;	/* 0xC0 */
	unsigned short gpmc_noe;	/* 0xC2 */
	unsigned short gpmc_nwe;	/* 0xC4 */
	unsigned char res2[0x22A];
	unsigned int status;		/* 0x2F0 */
	unsigned int gpstatus;		/* 0x2F4 */
	unsigned char res3[0x08];
	unsigned int rpubkey_0;		/* 0x300 */
	unsigned int rpubkey_1;		/* 0x304 */
	unsigned int rpubkey_2;		/* 0x308 */
	unsigned int rpubkey_3;		/* 0x30C */
	unsigned int rpubkey_4;		/* 0x310 */
	unsigned char res4[0x04];
	unsigned int randkey_0;		/* 0x318 */
	unsigned int randkey_1;		/* 0x31C */
	unsigned int randkey_2;		/* 0x320 */
	unsigned int randkey_3;		/* 0x324 */
	unsigned char res5[0x124];
	unsigned int ctrl_omap_stat;	/* 0x44C */
} ctrl_t;
#else /* __ASSEMBLY__ */
#define CONTROL_STATUS		0x2F0
#endif /* __ASSEMBLY__ */

/* cpu type */
#define OMAP3503		0x5c00
#define OMAP3515		0x1c00
#define OMAP3525		0x4c00
#define OMAP3530		0x0c00

/* device type */
#define DEVICE_MASK		(0x7 << 8)
#define SYSBOOT_MASK		0x1F
#define TST_DEVICE		0x0
#define EMU_DEVICE		0x1
#define HS_DEVICE		0x2
#define GP_DEVICE		0x3

/* GPMC CS3/cs4/cs6 not avaliable */
#define GPMC_BASE		(OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0		0x60
#define GPMC_CONFIG_CS6		0x150
#define GPMC_CONFIG_CS0_BASE	(GPMC_BASE + GPMC_CONFIG_CS0)
#define GPMC_CONFIG_CS6_BASE	(GPMC_BASE + GPMC_CONFIG_CS6)
#define GPMC_CONFIG_WP		0x10

#define GPMC_CONFIG_WIDTH	0x30

#ifndef __ASSEMBLY__
typedef struct gpmc {
	unsigned char res1[0x10];
	unsigned int sysconfig;		/* 0x10 */
	unsigned char res2[0x4];
	unsigned int irqstatus;		/* 0x18 */
	unsigned int irqenable; 	/* 0x1C */
	unsigned char res3[0x20];
	unsigned int timeout_control; 	/* 0x40 */
	unsigned char res4[0xC];
	unsigned int config;		/* 0x50 */
	unsigned int status;		/* 0x54 */
	unsigned char res5[0x19C];
	unsigned int ecc_config;	/* 0x1F4 */
	unsigned int ecc_control;	/* 0x1F8 */
	unsigned int ecc_size_config;	/* 0x1FC */
	unsigned int ecc1_result;	/* 0x200 */
	unsigned int ecc2_result;	/* 0x204 */
	unsigned int ecc3_result;	/* 0x208 */
	unsigned int ecc4_result;	/* 0x20C */
	unsigned int ecc5_result;	/* 0x210 */
	unsigned int ecc6_result;	/* 0x214 */
	unsigned int ecc7_result;	/* 0x218 */
	unsigned int ecc8_result;	/* 0x21C */
	unsigned int ecc9_result;	/* 0x220 */
} gpmc_t;

typedef struct gpmc_csx {
	unsigned int config1;		/* 0x00 */
	unsigned int config2;		/* 0x04 */
	unsigned int config3;		/* 0x08 */
	unsigned int config4;		/* 0x0C */
	unsigned int config5;		/* 0x10 */
	unsigned int config6;		/* 0x14 */
	unsigned int config7;		/* 0x18 */
	unsigned int nand_cmd;		/* 0x1C */
	unsigned int nand_adr;		/* 0x20 */
	unsigned int nand_dat;		/* 0x24 */
} gpmc_csx_t;
#else /* __ASSEMBLY__ */
#define GPMC_CONFIG1		0x00
#define GPMC_CONFIG2		0x04
#define GPMC_CONFIG3		0x08
#define GPMC_CONFIG4		0x0C
#define GPMC_CONFIG5		0x10
#define GPMC_CONFIG6		0x14
#define GPMC_CONFIG7		0x18
#endif /* __ASSEMBLY__ */

/* GPMC Mapping */
#define FLASH_BASE		0x10000000	/* NOR flash, */
						/* aligned to 256 Meg */
#define FLASH_BASE_SDPV1	0x04000000	/* NOR flash, */
						/* aligned to 64 Meg */
#define FLASH_BASE_SDPV2	0x10000000	/* NOR flash, */
						/* aligned to 256 Meg */
#define DEBUG_BASE		0x08000000	/* debug board */
#define NAND_BASE		0x30000000	/* NAND addr */
						/* (actual size small port) */
#define PISMO2_BASE		0x18000000	/* PISMO2 CS1/2 */
#define ONENAND_MAP		0x20000000	/* OneNand addr */
						/* (actual size small port) */
/* SMS */
#ifndef __ASSEMBLY__
typedef struct sms {
	unsigned char res1[0x10];
	unsigned int sysconfig;		/* 0x10 */
	unsigned char res2[0x34];
	unsigned int rg_att0;		/* 0x48 */
	unsigned char res3[0x84];
	unsigned int class_arb0;	/* 0xD0 */
} sms_t;
#endif /* __ASSEMBLY__ */

#define BURSTCOMPLETE_GROUP7	(0x1 << 31)

/* SDRC */
#ifndef __ASSEMBLY__
typedef struct sdrc_cs {
	unsigned int mcfg;		/* 0x80 || 0xB0 */
	unsigned int mr;		/* 0x84 || 0xB4 */
	unsigned char res1[0x4];
	unsigned int emr2;		/* 0x8C || 0xBC */
	unsigned char res2[0x14];
	unsigned int rfr_ctrl;		/* 0x84 || 0xD4 */
	unsigned int manual;		/* 0xA8 || 0xD8 */
	unsigned char res3[0x4];
} sdrc_cs_t;

typedef struct sdrc_actim {
	unsigned int ctrla;		/* 0x9C || 0xC4 */
	unsigned int ctrlb;		/* 0xA0 || 0xC8 */
} sdrc_actim_t;

typedef struct sdrc {
	unsigned char res1[0x10];
	unsigned int sysconfig;		/* 0x10 */
	unsigned int status;		/* 0x14 */
	unsigned char res2[0x28];
	unsigned int cs_cfg;		/* 0x40 */
	unsigned int sharing;		/* 0x44 */
	unsigned char res3[0x18];
	unsigned int dlla_ctrl;		/* 0x60 */
	unsigned int dlla_status;	/* 0x64 */
	unsigned int dllb_ctrl;		/* 0x68 */
	unsigned int dllb_status;	/* 0x6C */
	unsigned int power;		/* 0x70 */
	unsigned char res4[0xC];
	sdrc_cs_t cs[2];		/* 0x80 || 0xB0 */
} sdrc_t;
#endif /* __ASSEMBLY__ */

#define DLLPHASE_90		(0x1 << 1)
#define LOADDLL			(0x1 << 2)
#define ENADLL			(0x1 << 3)
#define DLL_DELAY_MASK		0xFF00
#define DLL_NO_FILTER_MASK	((0x1 << 9) | (0x1 << 8))

#define PAGEPOLICY_HIGH		(0x1 << 0)
#define SRFRONRESET		(0x1 << 7)
#define WAKEUPPROC		(0x1 << 26)

#define DDR_SDRAM		(0x1 << 0)
#define DEEPPD			(0x1 << 3)
#define B32NOT16		(0x1 << 4)
#define BANKALLOCATION		(0x2 << 6)
#define RAMSIZE_128		(0x40 << 8) /* RAM size in 2MB chunks */
#define ADDRMUXLEGACY		(0x1 << 19)
#define CASWIDTH_10BITS		(0x5 << 20)
#define RASWIDTH_13BITS		(0x2 << 24)
#define BURSTLENGTH4		(0x2 << 0)
#define CASL3			(0x3 << 4)
#define SDRC_ACTIM_CTRL0_BASE	(OMAP34XX_SDRC_BASE + 0x9C)
#define SDRC_ACTIM_CTRL1_BASE	(OMAP34XX_SDRC_BASE + 0xC4)
#define ARE_ARCV_1		(0x1 << 0)
#define ARCV			(0x4e2 << 8) /* Autorefresh count */
#define OMAP34XX_SDRC_CS0	0x80000000
#define OMAP34XX_SDRC_CS1	0xA0000000
#define CMD_NOP			0x0
#define CMD_PRECHARGE		0x1
#define CMD_AUTOREFRESH		0x2
#define CMD_ENTR_PWRDOWN	0x3
#define CMD_EXIT_PWRDOWN	0x4
#define CMD_ENTR_SRFRSH		0x5
#define CMD_CKE_HIGH		0x6
#define CMD_CKE_LOW		0x7
#define SOFTRESET		(0x1 << 1)
#define SMART_IDLE		(0x2 << 3)
#define REF_ON_IDLE		(0x1 << 6)

/* timer regs offsets (32 bit regs) */

#ifndef __ASSEMBLY__
typedef struct gptimer {
	unsigned int tidr;	/* 0x00 r */
	unsigned char res[0xc];
	unsigned int tiocp_cfg;	/* 0x10 rw */
	unsigned int tistat;	/* 0x14 r */
	unsigned int tisr;	/* 0x18 rw */
	unsigned int tier;	/* 0x1c rw */
	unsigned int twer;	/* 0x20 rw */
	unsigned int tclr;	/* 0x24 rw */
	unsigned int tcrr;	/* 0x28 rw */
	unsigned int tldr;	/* 0x2c rw */
	unsigned int ttgr;	/* 0x30 rw */
	unsigned int twpc;	/* 0x34 r*/
	unsigned int tmar;	/* 0x38 rw*/
	unsigned int tcar1;	/* 0x3c r */
	unsigned int tcicr;	/* 0x40 rw */
	unsigned int tcar2;	/* 0x44 r */
} gptimer_t;
#endif /* __ASSEMBLY__ */

/* enable sys_clk NO-prescale /1 */
#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))

/* Watchdog */
#ifndef __ASSEMBLY__
typedef struct watchdog {
	unsigned char res1[0x34];
	unsigned int wwps;	/* 0x34 r */
	unsigned char res2[0x10];
	unsigned int wspr;	/* 0x48 rw */
} watchdog_t;
#endif /* __ASSEMBLY__ */

#define WD_UNLOCK1		0xAAAA
#define WD_UNLOCK2		0x5555

/* PRCM */
#define PRCM_BASE		0x48004000

#ifndef __ASSEMBLY__
typedef struct prcm {
	unsigned int fclken_iva2;	/* 0x00 */
	unsigned int clken_pll_iva2;	/* 0x04 */
	unsigned char res1[0x1c];
	unsigned int idlest_pll_iva2;	/* 0x24 */
	unsigned char res2[0x18];
	unsigned int clksel1_pll_iva2 ;	/* 0x40 */
	unsigned int clksel2_pll_iva2;	/* 0x44 */
	unsigned char res3[0x8bc];
	unsigned int clken_pll_mpu;	/* 0x904 */
	unsigned char res4[0x1c];
	unsigned int idlest_pll_mpu;	/* 0x924 */
	unsigned char res5[0x18];
	unsigned int clksel1_pll_mpu;	/* 0x940 */
	unsigned int clksel2_pll_mpu;	/* 0x944 */
	unsigned char res6[0xb8];
	unsigned int fclken1_core;	/* 0xa00 */
	unsigned char res7[0xc];
	unsigned int iclken1_core;	/* 0xa10 */
	unsigned int iclken2_core;	/* 0xa14 */
	unsigned char res8[0x28];
	unsigned int clksel_core;	/* 0xa40 */
	unsigned char res9[0xbc];
	unsigned int fclken_gfx;	/* 0xb00 */
	unsigned char res10[0xc];
	unsigned int iclken_gfx;	/* 0xb10 */
	unsigned char res11[0x2c];
	unsigned int clksel_gfx;	/* 0xb40 */
	unsigned char res12[0xbc];
	unsigned int fclken_wkup;	/* 0xc00 */
	unsigned char res13[0xc];
	unsigned int iclken_wkup;	/* 0xc10 */
	unsigned char res14[0xc];
	unsigned int idlest_wkup;	/* 0xc20 */
	unsigned char res15[0x1c];
	unsigned int clksel_wkup;	/* 0xc40 */
	unsigned char res16[0xbc];
	unsigned int clken_pll;		/* 0xd00 */
	unsigned char res17[0x1c];
	unsigned int idlest_ckgen;	/* 0xd20 */
	unsigned char res18[0x1c];
	unsigned int clksel1_pll;	/* 0xd40 */
	unsigned int clksel2_pll;	/* 0xd44 */
	unsigned int clksel3_pll;	/* 0xd48 */
	unsigned char res19[0xb4];
	unsigned int fclken_dss;	/* 0xe00 */
	unsigned char res20[0xc];
	unsigned int iclken_dss;	/* 0xe10 */
	unsigned char res21[0x2c];
	unsigned int clksel_dss;	/* 0xe40 */
	unsigned char res22[0xbc];
	unsigned int fclken_cam;	/* 0xf00 */
	unsigned char res23[0xc];
	unsigned int iclken_cam;	/* 0xf10 */
	unsigned char res24[0x2c];
	unsigned int clksel_cam;	/* 0xf40 */
	unsigned char res25[0xbc];
	unsigned int fclken_per;	/* 0x1000 */
	unsigned char res26[0xc];
	unsigned int iclken_per;	/* 0x1010 */
	unsigned char res27[0x2c];
	unsigned int clksel_per;	/* 0x1040 */
	unsigned char res28[0xfc];
	unsigned int clksel1_emu;	/* 0x1140 */
} prcm_t;
#else /* __ASSEMBLY__ */
#define CM_CLKSEL_CORE		0x48004a40
#define CM_CLKSEL_GFX		0x48004b40
#define CM_CLKSEL_WKUP		0x48004c40
#define CM_CLKEN_PLL		0x48004d00
#define CM_CLKSEL1_PLL		0x48004d40
#define CM_CLKSEL1_EMU		0x48005140
#endif /* __ASSEMBLY__ */

#define PRM_BASE		0x48306000

#ifndef __ASSEMBLY__
typedef struct prm {
	unsigned char res1[0xd40];
	unsigned int clksel;		/* 0xd40 */
	unsigned char res2[0x50c];
	unsigned int rstctrl;		/* 0x1250 */
	unsigned char res3[0x1c];
	unsigned int clksrc_ctrl;	/* 0x1270 */
} prm_t;
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL		0x48307250
#endif /* __ASSEMBLY__ */

#define SYSCLKDIV_1		(0x1 << 6)
#define SYSCLKDIV_2		(0x1 << 7)

#define CLKSEL_GPT1		(0x1 << 0)

#define EN_GPT1			(0x1 << 0)
#define EN_32KSYNC		(0x1 << 2)

#define ST_WDT2			(0x1 << 5)

#define ST_MPU_CLK		(0x1 << 0)

#define ST_CORE_CLK		(0x1 << 0)

#define ST_PERIPH_CLK		(0x1 << 1)

#define ST_IVA2_CLK		(0x1 << 0)

#define RESETDONE		(0x1 << 0)

#define TCLR_ST			(0x1 << 0)
#define TCLR_AR			(0x1 << 1)
#define TCLR_PRE		(0x1 << 5)

/* SMX-APE */
#define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)
#define PM_GPMC_BASE_ADDR_ARM		(SMX_APE_BASE + 0x12400)
#define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
#define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)

#ifndef __ASSEMBLY__
typedef struct pm {
	unsigned char res1[0x48];
	unsigned int req_info_permission_0;	/* 0x48 */
	unsigned char res2[0x4];
	unsigned int read_permission_0;		/* 0x50 */
	unsigned char res3[0x4];
	unsigned int wirte_permission_0;	/* 0x58 */
	unsigned char res4[0x4];
	unsigned int addr_match_1;		/* 0x58 */
	unsigned char res5[0x4];
	unsigned int req_info_permission_1;	/* 0x68 */
	unsigned char res6[0x14];
	unsigned int addr_match_2;		/* 0x80 */
} pm_t;
#endif /*__ASSEMBLY__ */

/* Permission values for registers -Full fledged permissions to all */
#define UNLOCK_1			0xFFFFFFFF
#define UNLOCK_2			0x00000000
#define UNLOCK_3			0x0000FFFF

#define NOT_EARLY			0

/* I2C base */
#define I2C_BASE1		(OMAP34XX_CORE_L4_IO_BASE + 0x70000)
#define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
#define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)

#endif /* _CPU_H */
Commit	Line	Data
2c803210 DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#ifndef _CPU_H
	26	#define _CPU_H
	27
	28	/* Register offsets of common modules */
	29	/* Control */
	30	#ifndef __ASSEMBLY__
	31	typedef struct ctrl {
	32	unsigned char res1[0xC0];
	33	unsigned short gpmc_nadv_ale; /* 0xC0 */
	34	unsigned short gpmc_noe; /* 0xC2 */
	35	unsigned short gpmc_nwe; /* 0xC4 */
	36	unsigned char res2[0x22A];
	37	unsigned int status; /* 0x2F0 */
6530a8bf DB	38	unsigned int gpstatus; /* 0x2F4 */
	39	unsigned char res3[0x08];
	40	unsigned int rpubkey_0; /* 0x300 */
	41	unsigned int rpubkey_1; /* 0x304 */
	42	unsigned int rpubkey_2; /* 0x308 */
	43	unsigned int rpubkey_3; /* 0x30C */
	44	unsigned int rpubkey_4; /* 0x310 */
	45	unsigned char res4[0x04];
	46	unsigned int randkey_0; /* 0x318 */
	47	unsigned int randkey_1; /* 0x31C */
	48	unsigned int randkey_2; /* 0x320 */
	49	unsigned int randkey_3; /* 0x324 */
	50	unsigned char res5[0x124];
	51	unsigned int ctrl_omap_stat; /* 0x44C */
2c803210 DB	52	} ctrl_t;
	53	#else /* __ASSEMBLY__ */
	54	#define CONTROL_STATUS 0x2F0
	55	#endif /* __ASSEMBLY__ */
	56
6530a8bf DB	57	/* cpu type */
	58	#define OMAP3503 0x5c00
	59	#define OMAP3515 0x1c00
	60	#define OMAP3525 0x4c00
	61	#define OMAP3530 0x0c00
	62
2c803210 DB	63	/* device type */
	64	#define DEVICE_MASK (0x7 << 8)
	65	#define SYSBOOT_MASK 0x1F
	66	#define TST_DEVICE 0x0
	67	#define EMU_DEVICE 0x1
	68	#define HS_DEVICE 0x2
	69	#define GP_DEVICE 0x3
	70
	71	/* GPMC CS3/cs4/cs6 not avaliable */
	72	#define GPMC_BASE (OMAP34XX_GPMC_BASE)
	73	#define GPMC_CONFIG_CS0 0x60
	74	#define GPMC_CONFIG_CS6 0x150
	75	#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
	76	#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
	77	#define GPMC_CONFIG_WP 0x10
	78
	79	#define GPMC_CONFIG_WIDTH 0x30
	80
	81	#ifndef __ASSEMBLY__
	82	typedef struct gpmc {
	83	unsigned char res1[0x10];
	84	unsigned int sysconfig; /* 0x10 */
	85	unsigned char res2[0x4];
	86	unsigned int irqstatus; /* 0x18 */
	87	unsigned int irqenable; /* 0x1C */
	88	unsigned char res3[0x20];
	89	unsigned int timeout_control; /* 0x40 */
	90	unsigned char res4[0xC];
	91	unsigned int config; /* 0x50 */
	92	unsigned int status; /* 0x54 */
	93	unsigned char res5[0x19C];
	94	unsigned int ecc_config; /* 0x1F4 */
	95	unsigned int ecc_control; /* 0x1F8 */
	96	unsigned int ecc_size_config; /* 0x1FC */
	97	unsigned int ecc1_result; /* 0x200 */
	98	unsigned int ecc2_result; /* 0x204 */
	99	unsigned int ecc3_result; /* 0x208 */
	100	unsigned int ecc4_result; /* 0x20C */
	101	unsigned int ecc5_result; /* 0x210 */
	102	unsigned int ecc6_result; /* 0x214 */
	103	unsigned int ecc7_result; /* 0x218 */
	104	unsigned int ecc8_result; /* 0x21C */
	105	unsigned int ecc9_result; /* 0x220 */
	106	} gpmc_t;
	107
	108	typedef struct gpmc_csx {
	109	unsigned int config1; /* 0x00 */
	110	unsigned int config2; /* 0x04 */
	111	unsigned int config3; /* 0x08 */
	112	unsigned int config4; /* 0x0C */
	113	unsigned int config5; /* 0x10 */
	114	unsigned int config6; /* 0x14 */
	115	unsigned int config7; /* 0x18 */
	116	unsigned int nand_cmd; /* 0x1C */
	117	unsigned int nand_adr; /* 0x20 */
	118	unsigned int nand_dat; /* 0x24 */
	119	} gpmc_csx_t;
	120	#else /* __ASSEMBLY__ */
	121	#define GPMC_CONFIG1 0x00
	122	#define GPMC_CONFIG2 0x04
	123	#define GPMC_CONFIG3 0x08
	124	#define GPMC_CONFIG4 0x0C
	125	#define GPMC_CONFIG5 0x10
	126	#define GPMC_CONFIG6 0x14
127	#define GPMC_CONFIG7 0x18
128	#endif /* __ASSEMBLY__ */
129
130	/* GPMC Mapping */
131	#define FLASH_BASE 0x10000000 /* NOR flash, */
132	/* aligned to 256 Meg */
133	#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
134	/* aligned to 64 Meg */
135	#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
136	/* aligned to 256 Meg */
137	#define DEBUG_BASE 0x08000000 /* debug board */
138	#define NAND_BASE 0x30000000 /* NAND addr */
139	/* (actual size small port) */
140	#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
141	#define ONENAND_MAP 0x20000000 /* OneNand addr */
142	/* (actual size small port) */
143	/* SMS */
144	#ifndef __ASSEMBLY__
145	typedef struct sms {
146	unsigned char res1[0x10];
147	unsigned int sysconfig; /* 0x10 */
148	unsigned char res2[0x34];
149	unsigned int rg_att0; /* 0x48 */
150	unsigned char res3[0x84];
151	unsigned int class_arb0; /* 0xD0 */
152	} sms_t;
153	#endif /* __ASSEMBLY__ */
154
155	#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
156
157	/* SDRC */
158	#ifndef __ASSEMBLY__
159	typedef struct sdrc_cs {
160	unsigned int mcfg; /* 0x80 \|\| 0xB0 */
161	unsigned int mr; /* 0x84 \|\| 0xB4 */
162	unsigned char res1[0x4];
163	unsigned int emr2; /* 0x8C \|\| 0xBC */
164	unsigned char res2[0x14];
165	unsigned int rfr_ctrl; /* 0x84 \|\| 0xD4 */
166	unsigned int manual; /* 0xA8 \|\| 0xD8 */
167	unsigned char res3[0x4];
168	} sdrc_cs_t;
169
170	typedef struct sdrc_actim {
171	unsigned int ctrla; /* 0x9C \|\| 0xC4 */
172	unsigned int ctrlb; /* 0xA0 \|\| 0xC8 */
173	} sdrc_actim_t;
174
175	typedef struct sdrc {
176	unsigned char res1[0x10];
177	unsigned int sysconfig; /* 0x10 */
178	unsigned int status; /* 0x14 */
179	unsigned char res2[0x28];
180	unsigned int cs_cfg; /* 0x40 */
181	unsigned int sharing; /* 0x44 */
182	unsigned char res3[0x18];
183	unsigned int dlla_ctrl; /* 0x60 */
184	unsigned int dlla_status; /* 0x64 */
185	unsigned int dllb_ctrl; /* 0x68 */
186	unsigned int dllb_status; /* 0x6C */
187	unsigned int power; /* 0x70 */
188	unsigned char res4[0xC];
189	sdrc_cs_t cs[2]; /* 0x80 \|\| 0xB0 */
190	} sdrc_t;
191	#endif /* __ASSEMBLY__ */
192
193	#define DLLPHASE_90 (0x1 << 1)
194	#define LOADDLL (0x1 << 2)
195	#define ENADLL (0x1 << 3)
196	#define DLL_DELAY_MASK 0xFF00
197	#define DLL_NO_FILTER_MASK ((0x1 << 9) \| (0x1 << 8))
198
199	#define PAGEPOLICY_HIGH (0x1 << 0)
200	#define SRFRONRESET (0x1 << 7)
201	#define WAKEUPPROC (0x1 << 26)
202
203	#define DDR_SDRAM (0x1 << 0)
204	#define DEEPPD (0x1 << 3)
205	#define B32NOT16 (0x1 << 4)
206	#define BANKALLOCATION (0x2 << 6)
207	#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
208	#define ADDRMUXLEGACY (0x1 << 19)
209	#define CASWIDTH_10BITS (0x5 << 20)
210	#define RASWIDTH_13BITS (0x2 << 24)
211	#define BURSTLENGTH4 (0x2 << 0)
212	#define CASL3 (0x3 << 4)
213	#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
214	#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
215	#define ARE_ARCV_1 (0x1 << 0)
216	#define ARCV (0x4e2 << 8) /* Autorefresh count */
217	#define OMAP34XX_SDRC_CS0 0x80000000
218	#define OMAP34XX_SDRC_CS1 0xA0000000
219	#define CMD_NOP 0x0
220	#define CMD_PRECHARGE 0x1
221	#define CMD_AUTOREFRESH 0x2
222	#define CMD_ENTR_PWRDOWN 0x3
223	#define CMD_EXIT_PWRDOWN 0x4
224	#define CMD_ENTR_SRFRSH 0x5
225	#define CMD_CKE_HIGH 0x6
226	#define CMD_CKE_LOW 0x7
227	#define SOFTRESET (0x1 << 1)
228	#define SMART_IDLE (0x2 << 3)
229	#define REF_ON_IDLE (0x1 << 6)
230
231	/* timer regs offsets (32 bit regs) */
232
233	#ifndef __ASSEMBLY__
234	typedef struct gptimer {
235	unsigned int tidr; /* 0x00 r */
236	unsigned char res[0xc];
237	unsigned int tiocp_cfg; /* 0x10 rw */
238	unsigned int tistat; /* 0x14 r */
239	unsigned int tisr; /* 0x18 rw */
240	unsigned int tier; /* 0x1c rw */
241	unsigned int twer; /* 0x20 rw */
242	unsigned int tclr; /* 0x24 rw */
243	unsigned int tcrr; /* 0x28 rw */
244	unsigned int tldr; /* 0x2c rw */
245	unsigned int ttgr; /* 0x30 rw */
246	unsigned int twpc; /* 0x34 r*/
247	unsigned int tmar; /* 0x38 rw*/
248	unsigned int tcar1; /* 0x3c r */
249	unsigned int tcicr; /* 0x40 rw */
250	unsigned int tcar2; /* 0x44 r */
251	} gptimer_t;
252	#endif /* __ASSEMBLY__ */
253
254	/* enable sys_clk NO-prescale /1 */
255	#define GPT_EN ((0x0 << 2) \| (0x1 << 1) \| (0x1 << 0))
256
257	/* Watchdog */
258	#ifndef __ASSEMBLY__
259	typedef struct watchdog {
260	unsigned char res1[0x34];
261	unsigned int wwps; /* 0x34 r */
262	unsigned char res2[0x10];
263	unsigned int wspr; /* 0x48 rw */
264	} watchdog_t;
265	#endif /* __ASSEMBLY__ */
266
267	#define WD_UNLOCK1 0xAAAA
268	#define WD_UNLOCK2 0x5555
269
270	/* PRCM */
271	#define PRCM_BASE 0x48004000
272
273	#ifndef __ASSEMBLY__
274	typedef struct prcm {
275	unsigned int fclken_iva2; /* 0x00 */
276	unsigned int clken_pll_iva2; /* 0x04 */
277	unsigned char res1[0x1c];
278	unsigned int idlest_pll_iva2; /* 0x24 */
279	unsigned char res2[0x18];
280	unsigned int clksel1_pll_iva2 ; /* 0x40 */
281	unsigned int clksel2_pll_iva2; /* 0x44 */
282	unsigned char res3[0x8bc];
283	unsigned int clken_pll_mpu; /* 0x904 */
284	unsigned char res4[0x1c];
285	unsigned int idlest_pll_mpu; /* 0x924 */
286	unsigned char res5[0x18];
287	unsigned int clksel1_pll_mpu; /* 0x940 */
288	unsigned int clksel2_pll_mpu; /* 0x944 */
289	unsigned char res6[0xb8];
290	unsigned int fclken1_core; /* 0xa00 */
291	unsigned char res7[0xc];
292	unsigned int iclken1_core; /* 0xa10 */
293	unsigned int iclken2_core; /* 0xa14 */
294	unsigned char res8[0x28];
295	unsigned int clksel_core; /* 0xa40 */
296	unsigned char res9[0xbc];
297	unsigned int fclken_gfx; /* 0xb00 */
298	unsigned char res10[0xc];
299	unsigned int iclken_gfx; /* 0xb10 */
300	unsigned char res11[0x2c];
301	unsigned int clksel_gfx; /* 0xb40 */
302	unsigned char res12[0xbc];
303	unsigned int fclken_wkup; /* 0xc00 */
304	unsigned char res13[0xc];
305	unsigned int iclken_wkup; /* 0xc10 */
306	unsigned char res14[0xc];
307	unsigned int idlest_wkup; /* 0xc20 */
308	unsigned char res15[0x1c];
309	unsigned int clksel_wkup; /* 0xc40 */
310	unsigned char res16[0xbc];
311	unsigned int clken_pll; /* 0xd00 */
312	unsigned char res17[0x1c];
313	unsigned int idlest_ckgen; /* 0xd20 */
314	unsigned char res18[0x1c];
315	unsigned int clksel1_pll; /* 0xd40 */
316	unsigned int clksel2_pll; /* 0xd44 */
317	unsigned int clksel3_pll; /* 0xd48 */
318	unsigned char res19[0xb4];
319	unsigned int fclken_dss; /* 0xe00 */
320	unsigned char res20[0xc];
321	unsigned int iclken_dss; /* 0xe10 */
322	unsigned char res21[0x2c];
323	unsigned int clksel_dss; /* 0xe40 */
324	unsigned char res22[0xbc];
325	unsigned int fclken_cam; /* 0xf00 */
326	unsigned char res23[0xc];
327	unsigned int iclken_cam; /* 0xf10 */
328	unsigned char res24[0x2c];
329	unsigned int clksel_cam; /* 0xf40 */
330	unsigned char res25[0xbc];
331	unsigned int fclken_per; /* 0x1000 */
332	unsigned char res26[0xc];
333	unsigned int iclken_per; /* 0x1010 */
334	unsigned char res27[0x2c];
335	unsigned int clksel_per; /* 0x1040 */
336	unsigned char res28[0xfc];
337	unsigned int clksel1_emu; /* 0x1140 */
338	} prcm_t;
339	#else /* __ASSEMBLY__ */
340	#define CM_CLKSEL_CORE 0x48004a40
341	#define CM_CLKSEL_GFX 0x48004b40
342	#define CM_CLKSEL_WKUP 0x48004c40
343	#define CM_CLKEN_PLL 0x48004d00
344	#define CM_CLKSEL1_PLL 0x48004d40
345	#define CM_CLKSEL1_EMU 0x48005140
346	#endif /* __ASSEMBLY__ */
347
348	#define PRM_BASE 0x48306000
349
350	#ifndef __ASSEMBLY__
351	typedef struct prm {
352	unsigned char res1[0xd40];
353	unsigned int clksel; /* 0xd40 */
354	unsigned char res2[0x50c];
355	unsigned int rstctrl; /* 0x1250 */
356	unsigned char res3[0x1c];
357	unsigned int clksrc_ctrl; /* 0x1270 */
358	} prm_t;
359	#else /* __ASSEMBLY__ */
360	#define PRM_RSTCTRL 0x48307250
361	#endif /* __ASSEMBLY__ */
362
363	#define SYSCLKDIV_1 (0x1 << 6)
364	#define SYSCLKDIV_2 (0x1 << 7)
365
366	#define CLKSEL_GPT1 (0x1 << 0)
367
368	#define EN_GPT1 (0x1 << 0)
369	#define EN_32KSYNC (0x1 << 2)
370
371	#define ST_WDT2 (0x1 << 5)
372
373	#define ST_MPU_CLK (0x1 << 0)
374
375	#define ST_CORE_CLK (0x1 << 0)
376
377	#define ST_PERIPH_CLK (0x1 << 1)
378
379	#define ST_IVA2_CLK (0x1 << 0)
380
381	#define RESETDONE (0x1 << 0)
382
383	#define TCLR_ST (0x1 << 0)
384	#define TCLR_AR (0x1 << 1)
385	#define TCLR_PRE (0x1 << 5)
386
387	/* SMX-APE */
388	#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
389	#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
390	#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
391	#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
392
393	#ifndef __ASSEMBLY__
394	typedef struct pm {
395	unsigned char res1[0x48];
396	unsigned int req_info_permission_0; /* 0x48 */
397	unsigned char res2[0x4];
398	unsigned int read_permission_0; /* 0x50 */
399	unsigned char res3[0x4];
400	unsigned int wirte_permission_0; /* 0x58 */
401	unsigned char res4[0x4];
402	unsigned int addr_match_1; /* 0x58 */
403	unsigned char res5[0x4];
404	unsigned int req_info_permission_1; /* 0x68 */
405	unsigned char res6[0x14];
406	unsigned int addr_match_2; /* 0x80 */
407	} pm_t;
408	#endif /__ASSEMBLY__ /
409
410	/* Permission values for registers -Full fledged permissions to all */
411	#define UNLOCK_1 0xFFFFFFFF
412	#define UNLOCK_2 0x00000000
413	#define UNLOCK_3 0x0000FFFF
414
415	#define NOT_EARLY 0
416
417	/* I2C base */
418	#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
419	#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
420	#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
421
422	#endif /* _CPU_H */