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041b1dea WD |
1 | /* |
2 | * linux/include/asm-arm/io.h | |
3 | * | |
4 | * Copyright (C) 1996-2000 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Modifications: | |
11 | * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both | |
12 | * constant addresses and variable addresses. | |
13 | * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture | |
14 | * specific IO header files. | |
15 | * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. | |
16 | * 04-Apr-1999 PJB Added check_signature. | |
17 | * 12-Dec-1999 RMK More cleanups | |
18 | * 18-Jun-2000 RMK Removed virt_to_* and friends definitions | |
19 | */ | |
20 | #ifndef __ASM_ARM_IO_H | |
21 | #define __ASM_ARM_IO_H | |
22 | ||
b783edae WD |
23 | #ifdef __KERNEL__ |
24 | ||
041b1dea WD |
25 | #include <linux/types.h> |
26 | #include <asm/byteorder.h> | |
27 | #include <asm/memory.h> | |
b783edae | 28 | #if 0 /* XXX###XXX */ |
041b1dea | 29 | #include <asm/arch/hardware.h> |
b783edae | 30 | #endif /* XXX###XXX */ |
041b1dea | 31 | |
3a197b2f HW |
32 | static inline void sync(void) |
33 | { | |
34 | } | |
35 | ||
4d7d6936 HS |
36 | /* |
37 | * Given a physical address and a length, return a virtual address | |
38 | * that can be used to access the memory range with the caching | |
39 | * properties specified by "flags". | |
40 | */ | |
4d7d6936 HS |
41 | #define MAP_NOCACHE (0) |
42 | #define MAP_WRCOMBINE (0) | |
43 | #define MAP_WRBACK (0) | |
44 | #define MAP_WRTHROUGH (0) | |
45 | ||
46 | static inline void * | |
47 | map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) | |
48 | { | |
49 | return (void *)paddr; | |
50 | } | |
51 | ||
52 | /* | |
53 | * Take down a mapping set up by map_physmem(). | |
54 | */ | |
55 | static inline void unmap_physmem(void *vaddr, unsigned long flags) | |
56 | { | |
57 | ||
58 | } | |
59 | ||
041b1dea WD |
60 | /* |
61 | * Generic virtual read/write. Note that we don't support half-word | |
62 | * read/writes. We define __arch_*[bl] here, and leave __arch_*w | |
63 | * to the architecture specific code. | |
64 | */ | |
65 | #define __arch_getb(a) (*(volatile unsigned char *)(a)) | |
8ed96046 WD |
66 | #define __arch_getw(a) (*(volatile unsigned short *)(a)) |
67 | #define __arch_getl(a) (*(volatile unsigned int *)(a)) | |
041b1dea WD |
68 | |
69 | #define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) | |
8ed96046 WD |
70 | #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) |
71 | #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) | |
041b1dea WD |
72 | |
73 | extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); | |
74 | extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); | |
75 | extern void __raw_writesl(unsigned int addr, const void *data, int longlen); | |
76 | ||
77 | extern void __raw_readsb(unsigned int addr, void *data, int bytelen); | |
78 | extern void __raw_readsw(unsigned int addr, void *data, int wordlen); | |
79 | extern void __raw_readsl(unsigned int addr, void *data, int longlen); | |
80 | ||
81 | #define __raw_writeb(v,a) __arch_putb(v,a) | |
82 | #define __raw_writew(v,a) __arch_putw(v,a) | |
83 | #define __raw_writel(v,a) __arch_putl(v,a) | |
84 | ||
85 | #define __raw_readb(a) __arch_getb(a) | |
86 | #define __raw_readw(a) __arch_getw(a) | |
87 | #define __raw_readl(a) __arch_getl(a) | |
88 | ||
ac7eb8a3 WD |
89 | #define writeb(v,a) __arch_putb(v,a) |
90 | #define writew(v,a) __arch_putw(v,a) | |
91 | #define writel(v,a) __arch_putl(v,a) | |
92 | ||
93 | #define readb(a) __arch_getb(a) | |
94 | #define readw(a) __arch_getw(a) | |
95 | #define readl(a) __arch_getl(a) | |
96 | ||
041b1dea WD |
97 | /* |
98 | * The compiler seems to be incapable of optimising constants | |
99 | * properly. Spell it out to the compiler in some cases. | |
100 | * These are only valid for small values of "off" (< 1<<12) | |
101 | */ | |
102 | #define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) | |
103 | #define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) | |
104 | #define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) | |
105 | ||
106 | #define __raw_base_readb(base,off) __arch_base_getb(base,off) | |
107 | #define __raw_base_readw(base,off) __arch_base_getw(base,off) | |
108 | #define __raw_base_readl(base,off) __arch_base_getl(base,off) | |
109 | ||
110 | /* | |
111 | * Now, pick up the machine-defined IO definitions | |
112 | */ | |
b783edae | 113 | #if 0 /* XXX###XXX */ |
041b1dea | 114 | #include <asm/arch/io.h> |
b783edae | 115 | #endif /* XXX###XXX */ |
041b1dea WD |
116 | |
117 | /* | |
06d01dbe WD |
118 | * IO port access primitives |
119 | * ------------------------- | |
120 | * | |
121 | * The ARM doesn't have special IO access instructions; all IO is memory | |
122 | * mapped. Note that these are defined to perform little endian accesses | |
123 | * only. Their primary purpose is to access PCI and ISA peripherals. | |
124 | * | |
125 | * Note that for a big endian machine, this implies that the following | |
126 | * big endian mode connectivity is in place, as described by numerious | |
127 | * ARM documents: | |
128 | * | |
129 | * PCI: D0-D7 D8-D15 D16-D23 D24-D31 | |
130 | * ARM: D24-D31 D16-D23 D8-D15 D0-D7 | |
131 | * | |
132 | * The machine specific io.h include defines __io to translate an "IO" | |
133 | * address to a memory address. | |
041b1dea WD |
134 | * |
135 | * Note that we prevent GCC re-ordering or caching values in expressions | |
136 | * by introducing sequence points into the in*() definitions. Note that | |
137 | * __raw_* do not guarantee this behaviour. | |
06d01dbe WD |
138 | * |
139 | * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. | |
041b1dea WD |
140 | */ |
141 | #ifdef __io | |
142 | #define outb(v,p) __raw_writeb(v,__io(p)) | |
06d01dbe WD |
143 | #define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) |
144 | #define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) | |
041b1dea | 145 | |
06d01dbe WD |
146 | #define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) |
147 | #define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) | |
148 | #define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) | |
041b1dea WD |
149 | |
150 | #define outsb(p,d,l) __raw_writesb(__io(p),d,l) | |
151 | #define outsw(p,d,l) __raw_writesw(__io(p),d,l) | |
152 | #define outsl(p,d,l) __raw_writesl(__io(p),d,l) | |
153 | ||
154 | #define insb(p,d,l) __raw_readsb(__io(p),d,l) | |
155 | #define insw(p,d,l) __raw_readsw(__io(p),d,l) | |
156 | #define insl(p,d,l) __raw_readsl(__io(p),d,l) | |
157 | #endif | |
158 | ||
159 | #define outb_p(val,port) outb((val),(port)) | |
160 | #define outw_p(val,port) outw((val),(port)) | |
161 | #define outl_p(val,port) outl((val),(port)) | |
162 | #define inb_p(port) inb((port)) | |
163 | #define inw_p(port) inw((port)) | |
164 | #define inl_p(port) inl((port)) | |
165 | ||
166 | #define outsb_p(port,from,len) outsb(port,from,len) | |
167 | #define outsw_p(port,from,len) outsw(port,from,len) | |
168 | #define outsl_p(port,from,len) outsl(port,from,len) | |
169 | #define insb_p(port,to,len) insb(port,to,len) | |
170 | #define insw_p(port,to,len) insw(port,to,len) | |
171 | #define insl_p(port,to,len) insl(port,to,len) | |
172 | ||
173 | /* | |
174 | * ioremap and friends. | |
175 | * | |
176 | * ioremap takes a PCI memory address, as specified in | |
177 | * linux/Documentation/IO-mapping.txt. If you want a | |
178 | * physical address, use __ioremap instead. | |
179 | */ | |
180 | extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); | |
181 | extern void __iounmap(void *addr); | |
182 | ||
183 | /* | |
184 | * Generic ioremap support. | |
185 | * | |
186 | * Define: | |
187 | * iomem_valid_addr(off,size) | |
188 | * iomem_to_phys(off) | |
189 | */ | |
190 | #ifdef iomem_valid_addr | |
191 | #define __arch_ioremap(off,sz,nocache) \ | |
192 | ({ \ | |
193 | unsigned long _off = (off), _size = (sz); \ | |
194 | void *_ret = (void *)0; \ | |
195 | if (iomem_valid_addr(_off, _size)) \ | |
196 | _ret = __ioremap(iomem_to_phys(_off),_size,0); \ | |
197 | _ret; \ | |
198 | }) | |
199 | ||
200 | #define __arch_iounmap __iounmap | |
201 | #endif | |
202 | ||
203 | #define ioremap(off,sz) __arch_ioremap((off),(sz),0) | |
204 | #define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) | |
205 | #define iounmap(_addr) __arch_iounmap(_addr) | |
206 | ||
207 | /* | |
208 | * DMA-consistent mapping functions. These allocate/free a region of | |
209 | * uncached, unwrite-buffered mapped memory space for use with DMA | |
210 | * devices. This is the "generic" version. The PCI specific version | |
211 | * is in pci.h | |
212 | */ | |
213 | extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); | |
214 | extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); | |
215 | extern void consistent_sync(void *vaddr, size_t size, int rw); | |
216 | ||
217 | /* | |
218 | * String version of IO memory access ops: | |
219 | */ | |
220 | extern void _memcpy_fromio(void *, unsigned long, size_t); | |
221 | extern void _memcpy_toio(unsigned long, const void *, size_t); | |
222 | extern void _memset_io(unsigned long, int, size_t); | |
223 | ||
224 | extern void __readwrite_bug(const char *fn); | |
225 | ||
226 | /* | |
227 | * If this architecture has PCI memory IO, then define the read/write | |
228 | * macros. These should only be used with the cookie passed from | |
229 | * ioremap. | |
230 | */ | |
231 | #ifdef __mem_pci | |
232 | ||
06d01dbe WD |
233 | #define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) |
234 | #define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) | |
235 | #define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) | |
041b1dea | 236 | |
06d01dbe WD |
237 | #define writeb(v,c) __raw_writeb(v,__mem_pci(c)) |
238 | #define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) | |
239 | #define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) | |
041b1dea | 240 | |
06d01dbe WD |
241 | #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) |
242 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) | |
243 | #define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) | |
041b1dea | 244 | |
06d01dbe WD |
245 | #define eth_io_copy_and_sum(s,c,l,b) \ |
246 | eth_copy_and_sum((s),__mem_pci(c),(l),(b)) | |
041b1dea WD |
247 | |
248 | static inline int | |
249 | check_signature(unsigned long io_addr, const unsigned char *signature, | |
250 | int length) | |
251 | { | |
252 | int retval = 0; | |
253 | do { | |
254 | if (readb(io_addr) != *signature) | |
255 | goto out; | |
256 | io_addr++; | |
257 | signature++; | |
258 | length--; | |
259 | } while (length); | |
260 | retval = 1; | |
261 | out: | |
262 | return retval; | |
263 | } | |
264 | ||
265 | #elif !defined(readb) | |
266 | ||
267 | #define readb(addr) (__readwrite_bug("readb"),0) | |
268 | #define readw(addr) (__readwrite_bug("readw"),0) | |
269 | #define readl(addr) (__readwrite_bug("readl"),0) | |
270 | #define writeb(v,addr) __readwrite_bug("writeb") | |
271 | #define writew(v,addr) __readwrite_bug("writew") | |
272 | #define writel(v,addr) __readwrite_bug("writel") | |
273 | ||
274 | #define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") | |
275 | ||
276 | #define check_signature(io,sig,len) (0) | |
277 | ||
278 | #endif /* __mem_pci */ | |
279 | ||
041b1dea WD |
280 | /* |
281 | * If this architecture has ISA IO, then define the isa_read/isa_write | |
282 | * macros. | |
283 | */ | |
284 | #ifdef __mem_isa | |
285 | ||
286 | #define isa_readb(addr) __raw_readb(__mem_isa(addr)) | |
287 | #define isa_readw(addr) __raw_readw(__mem_isa(addr)) | |
288 | #define isa_readl(addr) __raw_readl(__mem_isa(addr)) | |
289 | #define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) | |
290 | #define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) | |
291 | #define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) | |
292 | #define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) | |
293 | #define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) | |
294 | #define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) | |
295 | ||
296 | #define isa_eth_io_copy_and_sum(a,b,c,d) \ | |
297 | eth_copy_and_sum((a),__mem_isa(b),(c),(d)) | |
298 | ||
299 | static inline int | |
300 | isa_check_signature(unsigned long io_addr, const unsigned char *signature, | |
301 | int length) | |
302 | { | |
303 | int retval = 0; | |
304 | do { | |
305 | if (isa_readb(io_addr) != *signature) | |
306 | goto out; | |
307 | io_addr++; | |
308 | signature++; | |
309 | length--; | |
310 | } while (length); | |
311 | retval = 1; | |
312 | out: | |
313 | return retval; | |
314 | } | |
315 | ||
316 | #else /* __mem_isa */ | |
317 | ||
318 | #define isa_readb(addr) (__readwrite_bug("isa_readb"),0) | |
319 | #define isa_readw(addr) (__readwrite_bug("isa_readw"),0) | |
320 | #define isa_readl(addr) (__readwrite_bug("isa_readl"),0) | |
321 | #define isa_writeb(val,addr) __readwrite_bug("isa_writeb") | |
322 | #define isa_writew(val,addr) __readwrite_bug("isa_writew") | |
323 | #define isa_writel(val,addr) __readwrite_bug("isa_writel") | |
324 | #define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") | |
325 | #define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") | |
326 | #define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") | |
327 | ||
328 | #define isa_eth_io_copy_and_sum(a,b,c,d) \ | |
329 | __readwrite_bug("isa_eth_io_copy_and_sum") | |
330 | ||
331 | #define isa_check_signature(io,sig,len) (0) | |
332 | ||
333 | #endif /* __mem_isa */ | |
b783edae | 334 | #endif /* __KERNEL__ */ |
041b1dea | 335 | #endif /* __ASM_ARM_IO_H */ |