projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| df548d3c HS |
1 | /* |
| 2 | * Copyright (C) 2006 Atmel Corporation | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | #ifndef __ASM_AVR32_ARCH_CLK_H__ | |
| 23 | #define __ASM_AVR32_ARCH_CLK_H__ | |
| 24 | ||
| 5fee84a7 HS |
25 | #include <asm/arch/chip-features.h> |
| 26 | ||
| df548d3c | 27 | #ifdef CONFIG_PLL |
| 6d0f6bcf | 28 | #define MAIN_CLK_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) * CONFIG_SYS_PLL0_MUL) |
| df548d3c | 29 | #else |
| 6d0f6bcf | 30 | #define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ) |
| df548d3c HS |
31 | #endif |
| 32 | ||
| 33 | static inline unsigned long get_cpu_clk_rate(void) | |
| 34 | { | |
| 6d0f6bcf | 35 | return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU; |
| df548d3c HS |
36 | } |
| 37 | static inline unsigned long get_hsb_clk_rate(void) | |
| 38 | { | |
| 6d0f6bcf | 39 | return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB; |
| df548d3c HS |
40 | } |
| 41 | static inline unsigned long get_pba_clk_rate(void) | |
| 42 | { | |
| 6d0f6bcf | 43 | return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA; |
| df548d3c HS |
44 | } |
| 45 | static inline unsigned long get_pbb_clk_rate(void) | |
| 46 | { | |
| 6d0f6bcf | 47 | return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB; |
| df548d3c HS |
48 | } |
| 49 | ||
| 50 | /* Accessors for specific devices. More will be added as needed. */ | |
| 51 | static inline unsigned long get_sdram_clk_rate(void) | |
| 52 | { | |
| 53 | return get_hsb_clk_rate(); | |
| 54 | } | |
| 5fee84a7 | 55 | #ifdef AT32AP700x_CHIP_HAS_USART |
| df548d3c HS |
56 | static inline unsigned long get_usart_clk_rate(unsigned int dev_id) |
| 57 | { | |
| 58 | return get_pba_clk_rate(); | |
| 59 | } | |
| 5fee84a7 | 60 | #endif |
| cdd42c0c | 61 | #ifdef AT32AP700x_CHIP_HAS_MACB |
| b4ec9c2d HS |
62 | static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) |
| 63 | { | |
| 64 | return get_pbb_clk_rate(); | |
| 65 | } | |
| 66 | static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) | |
| 67 | { | |
| 68 | return get_hsb_clk_rate(); | |
| 69 | } | |
| 5fee84a7 HS |
70 | #endif |
| 71 | #ifdef AT32AP700x_CHIP_HAS_MMCI | |
| 05fdab1e HS |
72 | static inline unsigned long get_mci_clk_rate(void) |
| 73 | { | |
| 74 | return get_pbb_clk_rate(); | |
| 75 | } | |
| 5fee84a7 | 76 | #endif |
| 60445cb5 HCE |
77 | #ifdef AT32AP700x_CHIP_HAS_SPI |
| 78 | static inline unsigned long get_spi_clk_rate(unsigned int dev_id) | |
| 79 | { | |
| 80 | return get_pba_clk_rate(); | |
| 81 | } | |
| 82 | #endif | |
| df548d3c | 83 | |
| 3ace2527 | 84 | extern void clk_init(void); |
| 5c374c9e | 85 | extern void gclk_init(void) __attribute__((weak)); |
| 3ace2527 | 86 | |
| d38da537 | 87 | /* Board code may need the SDRAM base clock as a compile-time constant */ |
| 6d0f6bcf | 88 | #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB) |
| d38da537 | 89 | |
| df548d3c | 90 | #endif /* __ASM_AVR32_ARCH_CLK_H__ */ |