projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3a108ed8 ZL |
1 | /* |
| 2 | * MCF5272 Internal Memory Map | |
| 3 | * | |
| 4 | * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
| 5 | * 2006 Zachary P. Landau <zachary.landau@labxtechnologies.com> | |
| 6 | * | |
| 7 | * See file CREDITS for list of people who contributed to this | |
| 8 | * project. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of | |
| 13 | * the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public License | |
| 21 | * along with this program; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 23 | * MA 02111-1307 USA | |
| 24 | */ | |
| 25 | ||
| 26 | #ifndef __IMMAP_5271__ | |
| 27 | #define __IMMAP_5271__ | |
| 28 | ||
| 6d0f6bcf JCPV |
29 | #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) |
| 30 | #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) | |
| 31 | #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) | |
| 32 | #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) | |
| 33 | #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) | |
| 34 | #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) | |
| 35 | #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) | |
| 36 | #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) | |
| 37 | #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) | |
| 38 | #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) | |
| 39 | #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) | |
| 40 | #define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) | |
| 41 | #define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) | |
| 42 | #define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) | |
| 43 | #define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) | |
| 44 | #define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) | |
| 45 | #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) | |
| 46 | #define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) | |
| 47 | #define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) | |
| 48 | #define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) | |
| 49 | #define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) | |
| 50 | #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) | |
| 51 | #define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) | |
| 52 | #define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) | |
| 53 | #define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) | |
| 54 | #define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) | |
| 55 | #define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) | |
| 56 | #define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) | |
| 57 | #define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) | |
| 58 | #define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) | |
| 59 | #define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) | |
| 60 | #define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) | |
| 61 | #define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) | |
| 62 | #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) | |
| 63 | #define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) | |
| 64 | #define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) | |
| 3a108ed8 | 65 | |
| 56115665 TL |
66 | /* Interrupt module registers */ |
| 67 | typedef struct int0_ctrl { | |
| 68 | /* Interrupt Controller 0 */ | |
| 69 | u32 iprh0; /* 0x00 Pending Register High */ | |
| 70 | u32 iprl0; /* 0x04 Pending Register Low */ | |
| 71 | u32 imrh0; /* 0x08 Mask Register High */ | |
| 72 | u32 imrl0; /* 0x0C Mask Register Low */ | |
| 73 | u32 frch0; /* 0x10 Force Register High */ | |
| 74 | u32 frcl0; /* 0x14 Force Register Low */ | |
| 75 | u8 irlr; /* 0x18 */ | |
| 76 | u8 iacklpr; /* 0x19 */ | |
| 77 | u16 res1[19]; /* 0x1a - 0x3c */ | |
| 78 | u8 icr0[64]; /* 0x40 - 0x7F Control registers */ | |
| 79 | u32 res3[24]; /* 0x80 - 0xDF */ | |
| 80 | u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ | |
| 81 | u8 res4[3]; /* 0xE1 - 0xE3 */ | |
| 82 | u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ | |
| 83 | u8 res5[3]; /* 0xE5 - 0xE7 */ | |
| 84 | u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ | |
| 85 | u8 res6[3]; /* 0xE9 - 0xEB */ | |
| 86 | u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ | |
| 87 | u8 res7[3]; /* 0xED - 0xEF */ | |
| 88 | u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ | |
| 89 | u8 res8[3]; /* 0xF1 - 0xF3 */ | |
| 90 | u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ | |
| 91 | u8 res9[3]; /* 0xF5 - 0xF7 */ | |
| 92 | u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ | |
| 93 | u8 resa[3]; /* 0xF9 - 0xFB */ | |
| 94 | u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ | |
| 95 | u8 resb[3]; /* 0xFD - 0xFF */ | |
| 96 | } int0_t; | |
| 3a108ed8 | 97 | |
| 56115665 | 98 | #endif /* __IMMAP_5271__ */ |