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bf9e3b38 WD |
1 | /* |
2 | * MCF5282 Internal Memory Map | |
3 | * | |
4 | * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __IMMAP_5282__ | |
26 | #define __IMMAP_5282__ | |
27 | ||
9acb626f HS |
28 | struct sys_ctrl { |
29 | uint ipsbar; | |
30 | char res1[4]; | |
31 | uint rambar; | |
32 | char res2[4]; | |
33 | uchar crsr; | |
34 | uchar cwcr; | |
35 | uchar lpicr; | |
36 | uchar cwsr; | |
37 | uint dmareqc; | |
38 | char res3[4]; | |
39 | uint mpark; | |
40 | ||
41 | /* TODO: finish these */ | |
42 | }; | |
43 | ||
44 | ||
bf9e3b38 WD |
45 | |
46 | /* Fast ethernet controller registers | |
47 | */ | |
48 | typedef struct fec { | |
9acb626f HS |
49 | uint res1; /* reserved 1000*/ |
50 | uint fec_ievent; /* interrupt event register 1004*/ /* EIR */ | |
51 | uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */ | |
52 | uint res2; /* reserved 100c*/ | |
53 | uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */ | |
54 | uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */ | |
55 | uint res3[3]; /* reserved 1018*/ | |
56 | uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */ | |
57 | uint res4[6]; /* reserved 1028*/ | |
58 | uint fec_mii_data; /* MII data register 1040*/ /* MDATA */ | |
59 | uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */ | |
60 | /*1044*/ | |
61 | uint res5[7]; /* reserved 1048*/ | |
62 | uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */ | |
63 | uint res6[7]; /* reserved 1068*/ | |
64 | uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */ | |
65 | uint res7[15]; /* reserved 1088*/ | |
66 | uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */ | |
67 | uint res8[7]; /* reserved 10C8*/ | |
68 | uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */ | |
69 | uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */ | |
70 | uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */ | |
71 | uint res9[10]; /* reserved 10F0*/ | |
72 | uint fec_ihash_table_high; /* upper 32-bits of individual hash *//* IAUR */ | |
73 | uint fec_ihash_table_low; /* lower 32-bits of individual hash *//* IALR */ | |
74 | uint fec_ghash_table_high; /* upper 32-bits of group hash *//* GAUR */ | |
75 | uint fec_ghash_table_low; /* lower 32-bits of group hash *//* GALR */ | |
76 | uint res10[7]; /* reserved 1128*/ | |
77 | uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */ | |
78 | uint res11; /* reserved 1148*/ | |
79 | uint fec_r_bound; /* FIFO Receive Bound Register = end of *//* FRBR */ | |
80 | uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = *//* FRSR */ | |
81 | uint res12[11]; /* reserved 1154*/ | |
82 | uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*//* ERDSR */ | |
83 | uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*//* ETDSR */ | |
84 | uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */ | |
bf9e3b38 WD |
85 | } fec_t; |
86 | ||
87 | #endif /* __IMMAP_5282__ */ |