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5da627a4 WD |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * Include file for Alchemy Semiconductor's Au1k CPU. | |
5 | * | |
6 | * Copyright 2000,2001 MontaVista Software Inc. | |
7 | * Author: MontaVista Software, Inc. | |
8 | * ppopov@mvista.com or source@mvista.com | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License along | |
27 | * with this program; if not, write to the Free Software Foundation, Inc., | |
28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | /* | |
32 | * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp | |
33 | */ | |
34 | ||
35 | #ifndef _AU1X00_H_ | |
36 | #define _AU1X00_H_ | |
37 | ||
38 | #ifndef __ASSEMBLY__ | |
39 | /* cpu pipeline flush */ | |
40 | void static inline au_sync(void) | |
41 | { | |
42 | __asm__ volatile ("sync"); | |
43 | } | |
44 | ||
45 | void static inline au_sync_udelay(int us) | |
46 | { | |
47 | __asm__ volatile ("sync"); | |
48 | udelay(us); | |
49 | } | |
50 | ||
51 | void static inline au_writeb(u8 val, int reg) | |
52 | { | |
53 | *(volatile u8 *)(reg) = val; | |
54 | } | |
55 | ||
56 | void static inline au_writew(u16 val, int reg) | |
57 | { | |
58 | *(volatile u16 *)(reg) = val; | |
59 | } | |
60 | ||
61 | void static inline au_writel(u32 val, int reg) | |
62 | { | |
63 | *(volatile u32 *)(reg) = val; | |
64 | } | |
65 | ||
66 | static inline u8 au_readb(unsigned long port) | |
67 | { | |
68 | return (*(volatile u8 *)port); | |
69 | } | |
70 | ||
71 | static inline u16 au_readw(unsigned long port) | |
72 | { | |
73 | return (*(volatile u16 *)port); | |
74 | } | |
75 | ||
76 | static inline u32 au_readl(unsigned long port) | |
77 | { | |
78 | return (*(volatile u32 *)port); | |
79 | } | |
80 | ||
81 | /* These next three functions should be a generic part of the MIPS | |
82 | * kernel (with the 'au_' removed from the name) and selected for | |
83 | * processors that support the instructions. | |
84 | * Taken from PPC tree. -- Dan | |
85 | */ | |
86 | /* Return the bit position of the most significant 1 bit in a word */ | |
87 | static __inline__ int __ilog2(unsigned int x) | |
88 | { | |
89 | int lz; | |
90 | ||
91 | asm volatile ( | |
92 | ".set\tnoreorder\n\t" | |
93 | ".set\tnoat\n\t" | |
94 | ".set\tmips32\n\t" | |
95 | "clz\t%0,%1\n\t" | |
96 | ".set\tmips0\n\t" | |
97 | ".set\tat\n\t" | |
98 | ".set\treorder" | |
99 | : "=r" (lz) | |
100 | : "r" (x)); | |
101 | ||
102 | return 31 - lz; | |
103 | } | |
104 | ||
105 | static __inline__ int au_ffz(unsigned int x) | |
106 | { | |
107 | if ((x = ~x) == 0) | |
108 | return 32; | |
109 | return __ilog2(x & -x); | |
110 | } | |
111 | ||
112 | /* | |
113 | * ffs: find first bit set. This is defined the same way as | |
114 | * the libc and compiler builtin ffs routines, therefore | |
115 | * differs in spirit from the above ffz (man ffs). | |
116 | */ | |
117 | static __inline__ int au_ffs(int x) | |
118 | { | |
119 | return __ilog2(x & -x) + 1; | |
120 | } | |
121 | ||
0c32d96d WD |
122 | #define gpio_set(Value) outl(Value, SYS_OUTPUTSET) |
123 | #define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR) | |
124 | #define gpio_read() inl(SYS_PINSTATERD) | |
125 | #define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR) | |
126 | ||
5da627a4 WD |
127 | #endif /* !ASSEMBLY */ |
128 | ||
129 | #ifdef CONFIG_PM | |
130 | /* no CP0 timer irq */ | |
131 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) | |
132 | #else | |
133 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) | |
134 | #endif | |
135 | ||
a522fa0e WD |
136 | #define CP0_IWATCHLO $18,1 |
137 | #define CP0_DEBUG $23 | |
138 | ||
5da627a4 | 139 | /* SDRAM Controller */ |
ff36fd85 WD |
140 | #ifdef CONFIG_AU1550 |
141 | ||
142 | #define MEM_SDMODE0 0xB4000800 | |
143 | #define MEM_SDMODE1 0xB4000808 | |
144 | #define MEM_SDMODE2 0xB4000810 | |
145 | ||
146 | #define MEM_SDADDR0 0xB4000820 | |
147 | #define MEM_SDADDR1 0xB4000828 | |
148 | #define MEM_SDADDR2 0xB4000830 | |
149 | ||
150 | #define MEM_SDCONFIGA 0xB4000840 | |
151 | #define MEM_SDCONFIGB 0xB4000848 | |
152 | #define MEM_SDPRECMD 0xB40008c0 | |
153 | #define MEM_SDAUTOREF 0xB40008c8 | |
154 | ||
155 | #define MEM_SDWRMD0 0xB4000880 | |
156 | #define MEM_SDWRMD1 0xB4000888 | |
157 | #define MEM_SDWRMD2 0xB4000890 | |
158 | ||
159 | #else /* CONFIG_AU1550 */ | |
160 | ||
5da627a4 WD |
161 | #define MEM_SDMODE0 0xB4000000 |
162 | #define MEM_SDMODE1 0xB4000004 | |
163 | #define MEM_SDMODE2 0xB4000008 | |
164 | ||
165 | #define MEM_SDADDR0 0xB400000C | |
166 | #define MEM_SDADDR1 0xB4000010 | |
167 | #define MEM_SDADDR2 0xB4000014 | |
168 | ||
169 | #define MEM_SDREFCFG 0xB4000018 | |
170 | #define MEM_SDPRECMD 0xB400001C | |
171 | #define MEM_SDAUTOREF 0xB4000020 | |
172 | ||
173 | #define MEM_SDWRMD0 0xB4000024 | |
174 | #define MEM_SDWRMD1 0xB4000028 | |
175 | #define MEM_SDWRMD2 0xB400002C | |
176 | ||
ff36fd85 WD |
177 | #endif /* CONFIG_AU1550 */ |
178 | ||
5da627a4 WD |
179 | #define MEM_SDSLEEP 0xB4000030 |
180 | #define MEM_SDSMCKE 0xB4000034 | |
181 | ||
182 | /* Static Bus Controller */ | |
183 | #define MEM_STCFG0 0xB4001000 | |
184 | #define MEM_STTIME0 0xB4001004 | |
185 | #define MEM_STADDR0 0xB4001008 | |
186 | ||
187 | #define MEM_STCFG1 0xB4001010 | |
188 | #define MEM_STTIME1 0xB4001014 | |
189 | #define MEM_STADDR1 0xB4001018 | |
190 | ||
191 | #define MEM_STCFG2 0xB4001020 | |
192 | #define MEM_STTIME2 0xB4001024 | |
193 | #define MEM_STADDR2 0xB4001028 | |
194 | ||
195 | #define MEM_STCFG3 0xB4001030 | |
196 | #define MEM_STTIME3 0xB4001034 | |
197 | #define MEM_STADDR3 0xB4001038 | |
198 | ||
199 | /* Interrupt Controller 0 */ | |
200 | #define IC0_CFG0RD 0xB0400040 | |
201 | #define IC0_CFG0SET 0xB0400040 | |
202 | #define IC0_CFG0CLR 0xB0400044 | |
203 | ||
204 | #define IC0_CFG1RD 0xB0400048 | |
205 | #define IC0_CFG1SET 0xB0400048 | |
206 | #define IC0_CFG1CLR 0xB040004C | |
207 | ||
208 | #define IC0_CFG2RD 0xB0400050 | |
209 | #define IC0_CFG2SET 0xB0400050 | |
210 | #define IC0_CFG2CLR 0xB0400054 | |
211 | ||
212 | #define IC0_REQ0INT 0xB0400054 | |
213 | #define IC0_SRCRD 0xB0400058 | |
214 | #define IC0_SRCSET 0xB0400058 | |
215 | #define IC0_SRCCLR 0xB040005C | |
216 | #define IC0_REQ1INT 0xB040005C | |
217 | ||
218 | #define IC0_ASSIGNRD 0xB0400060 | |
219 | #define IC0_ASSIGNSET 0xB0400060 | |
220 | #define IC0_ASSIGNCLR 0xB0400064 | |
221 | ||
222 | #define IC0_WAKERD 0xB0400068 | |
223 | #define IC0_WAKESET 0xB0400068 | |
224 | #define IC0_WAKECLR 0xB040006C | |
225 | ||
226 | #define IC0_MASKRD 0xB0400070 | |
227 | #define IC0_MASKSET 0xB0400070 | |
228 | #define IC0_MASKCLR 0xB0400074 | |
229 | ||
230 | #define IC0_RISINGRD 0xB0400078 | |
231 | #define IC0_RISINGCLR 0xB0400078 | |
232 | #define IC0_FALLINGRD 0xB040007C | |
233 | #define IC0_FALLINGCLR 0xB040007C | |
234 | ||
235 | #define IC0_TESTBIT 0xB0400080 | |
236 | ||
237 | /* Interrupt Controller 1 */ | |
238 | #define IC1_CFG0RD 0xB1800040 | |
239 | #define IC1_CFG0SET 0xB1800040 | |
240 | #define IC1_CFG0CLR 0xB1800044 | |
241 | ||
242 | #define IC1_CFG1RD 0xB1800048 | |
243 | #define IC1_CFG1SET 0xB1800048 | |
244 | #define IC1_CFG1CLR 0xB180004C | |
245 | ||
246 | #define IC1_CFG2RD 0xB1800050 | |
247 | #define IC1_CFG2SET 0xB1800050 | |
248 | #define IC1_CFG2CLR 0xB1800054 | |
249 | ||
250 | #define IC1_REQ0INT 0xB1800054 | |
251 | #define IC1_SRCRD 0xB1800058 | |
252 | #define IC1_SRCSET 0xB1800058 | |
253 | #define IC1_SRCCLR 0xB180005C | |
254 | #define IC1_REQ1INT 0xB180005C | |
255 | ||
256 | #define IC1_ASSIGNRD 0xB1800060 | |
257 | #define IC1_ASSIGNSET 0xB1800060 | |
258 | #define IC1_ASSIGNCLR 0xB1800064 | |
259 | ||
260 | #define IC1_WAKERD 0xB1800068 | |
261 | #define IC1_WAKESET 0xB1800068 | |
262 | #define IC1_WAKECLR 0xB180006C | |
263 | ||
264 | #define IC1_MASKRD 0xB1800070 | |
265 | #define IC1_MASKSET 0xB1800070 | |
266 | #define IC1_MASKCLR 0xB1800074 | |
267 | ||
268 | #define IC1_RISINGRD 0xB1800078 | |
269 | #define IC1_RISINGCLR 0xB1800078 | |
270 | #define IC1_FALLINGRD 0xB180007C | |
271 | #define IC1_FALLINGCLR 0xB180007C | |
272 | ||
273 | #define IC1_TESTBIT 0xB1800080 | |
274 | ||
275 | /* Interrupt Configuration Modes */ | |
276 | #define INTC_INT_DISABLED 0 | |
277 | #define INTC_INT_RISE_EDGE 0x1 | |
278 | #define INTC_INT_FALL_EDGE 0x2 | |
279 | #define INTC_INT_RISE_AND_FALL_EDGE 0x3 | |
280 | #define INTC_INT_HIGH_LEVEL 0x5 | |
281 | #define INTC_INT_LOW_LEVEL 0x6 | |
282 | #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 | |
283 | ||
284 | /* Interrupt Numbers */ | |
285 | #define AU1X00_UART0_INT 0 | |
286 | #define AU1000_UART1_INT 1 /* au1000 */ | |
287 | #define AU1000_UART2_INT 2 /* au1000 */ | |
288 | ||
289 | #define AU1500_PCI_INTA 1 /* au1500 */ | |
290 | #define AU1500_PCI_INTB 2 /* au1500 */ | |
291 | ||
292 | #define AU1X00_UART3_INT 3 | |
293 | ||
294 | #define AU1000_SSI0_INT 4 /* au1000 */ | |
295 | #define AU1000_SSI1_INT 5 /* au1000 */ | |
296 | ||
297 | #define AU1500_PCI_INTC 4 /* au1500 */ | |
298 | #define AU1500_PCI_INTD 5 /* au1500 */ | |
299 | ||
300 | #define AU1X00_DMA_INT_BASE 6 | |
301 | #define AU1X00_TOY_INT 14 | |
302 | #define AU1X00_TOY_MATCH0_INT 15 | |
303 | #define AU1X00_TOY_MATCH1_INT 16 | |
304 | #define AU1X00_TOY_MATCH2_INT 17 | |
305 | #define AU1X00_RTC_INT 18 | |
306 | #define AU1X00_RTC_MATCH0_INT 19 | |
307 | #define AU1X00_RTC_MATCH1_INT 20 | |
308 | #define AU1X00_RTC_MATCH2_INT 21 | |
309 | #define AU1000_IRDA_TX_INT 22 /* au1000 */ | |
310 | #define AU1000_IRDA_RX_INT 23 /* au1000 */ | |
311 | #define AU1X00_USB_DEV_REQ_INT 24 | |
312 | #define AU1X00_USB_DEV_SUS_INT 25 | |
313 | #define AU1X00_USB_HOST_INT 26 | |
314 | #define AU1X00_ACSYNC_INT 27 | |
315 | #define AU1X00_MAC0_DMA_INT 28 | |
316 | #define AU1X00_MAC1_DMA_INT 29 | |
317 | #define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT | |
318 | #define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT | |
319 | #define AU1000_I2S_UO_INT 30 /* au1000 */ | |
320 | #define AU1X00_AC97C_INT 31 | |
321 | #define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT | |
322 | #define AU1X00_GPIO_0 32 | |
323 | #define AU1X00_GPIO_1 33 | |
324 | #define AU1X00_GPIO_2 34 | |
325 | #define AU1X00_GPIO_3 35 | |
326 | #define AU1X00_GPIO_4 36 | |
327 | #define AU1X00_GPIO_5 37 | |
328 | #define AU1X00_GPIO_6 38 | |
329 | #define AU1X00_GPIO_7 39 | |
330 | #define AU1X00_GPIO_8 40 | |
331 | #define AU1X00_GPIO_9 41 | |
332 | #define AU1X00_GPIO_10 42 | |
333 | #define AU1X00_GPIO_11 43 | |
334 | #define AU1X00_GPIO_12 44 | |
335 | #define AU1X00_GPIO_13 45 | |
336 | #define AU1X00_GPIO_14 46 | |
337 | #define AU1X00_GPIO_15 47 | |
338 | ||
339 | /* Au1000 only */ | |
340 | #define AU1000_GPIO_16 48 | |
341 | #define AU1000_GPIO_17 49 | |
342 | #define AU1000_GPIO_18 50 | |
343 | #define AU1000_GPIO_19 51 | |
344 | #define AU1000_GPIO_20 52 | |
345 | #define AU1000_GPIO_21 53 | |
346 | #define AU1000_GPIO_22 54 | |
347 | #define AU1000_GPIO_23 55 | |
348 | #define AU1000_GPIO_24 56 | |
349 | #define AU1000_GPIO_25 57 | |
350 | #define AU1000_GPIO_26 58 | |
351 | #define AU1000_GPIO_27 59 | |
352 | #define AU1000_GPIO_28 60 | |
353 | #define AU1000_GPIO_29 61 | |
354 | #define AU1000_GPIO_30 62 | |
355 | #define AU1000_GPIO_31 63 | |
356 | ||
357 | /* Au1500 only */ | |
358 | #define AU1500_GPIO_200 48 | |
359 | #define AU1500_GPIO_201 49 | |
360 | #define AU1500_GPIO_202 50 | |
361 | #define AU1500_GPIO_203 51 | |
362 | #define AU1500_GPIO_20 52 | |
363 | #define AU1500_GPIO_204 53 | |
364 | #define AU1500_GPIO_205 54 | |
365 | #define AU1500_GPIO_23 55 | |
366 | #define AU1500_GPIO_24 56 | |
367 | #define AU1500_GPIO_25 57 | |
368 | #define AU1500_GPIO_26 58 | |
369 | #define AU1500_GPIO_27 59 | |
370 | #define AU1500_GPIO_28 60 | |
371 | #define AU1500_GPIO_206 61 | |
372 | #define AU1500_GPIO_207 62 | |
373 | #define AU1500_GPIO_208_215 63 | |
374 | ||
375 | #define AU1X00_MAX_INTR 63 | |
376 | ||
377 | #define AU1100_SD 2 | |
378 | #define AU1100_GPIO_208_215 29 | |
379 | /* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */ | |
380 | ||
381 | /* Programmable Counters 0 and 1 */ | |
382 | #define SYS_BASE 0xB1900000 | |
383 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) | |
384 | #define SYS_CNTRL_E1S (1<<23) | |
385 | #define SYS_CNTRL_T1S (1<<20) | |
386 | #define SYS_CNTRL_M21 (1<<19) | |
387 | #define SYS_CNTRL_M11 (1<<18) | |
388 | #define SYS_CNTRL_M01 (1<<17) | |
389 | #define SYS_CNTRL_C1S (1<<16) | |
390 | #define SYS_CNTRL_BP (1<<14) | |
391 | #define SYS_CNTRL_EN1 (1<<13) | |
392 | #define SYS_CNTRL_BT1 (1<<12) | |
393 | #define SYS_CNTRL_EN0 (1<<11) | |
394 | #define SYS_CNTRL_BT0 (1<<10) | |
395 | #define SYS_CNTRL_E0 (1<<8) | |
396 | #define SYS_CNTRL_E0S (1<<7) | |
397 | #define SYS_CNTRL_32S (1<<5) | |
398 | #define SYS_CNTRL_T0S (1<<4) | |
399 | #define SYS_CNTRL_M20 (1<<3) | |
400 | #define SYS_CNTRL_M10 (1<<2) | |
401 | #define SYS_CNTRL_M00 (1<<1) | |
402 | #define SYS_CNTRL_C0S (1<<0) | |
403 | ||
404 | /* Programmable Counter 0 Registers */ | |
405 | #define SYS_TOYTRIM (SYS_BASE + 0) | |
406 | #define SYS_TOYWRITE (SYS_BASE + 4) | |
407 | #define SYS_TOYMATCH0 (SYS_BASE + 8) | |
408 | #define SYS_TOYMATCH1 (SYS_BASE + 0xC) | |
409 | #define SYS_TOYMATCH2 (SYS_BASE + 0x10) | |
410 | #define SYS_TOYREAD (SYS_BASE + 0x40) | |
411 | ||
412 | /* Programmable Counter 1 Registers */ | |
413 | #define SYS_RTCTRIM (SYS_BASE + 0x44) | |
414 | #define SYS_RTCWRITE (SYS_BASE + 0x48) | |
415 | #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) | |
416 | #define SYS_RTCMATCH1 (SYS_BASE + 0x50) | |
417 | #define SYS_RTCMATCH2 (SYS_BASE + 0x54) | |
418 | #define SYS_RTCREAD (SYS_BASE + 0x58) | |
419 | ||
420 | /* I2S Controller */ | |
421 | #define I2S_DATA 0xB1000000 | |
422 | #define I2S_DATA_MASK (0xffffff) | |
423 | #define I2S_CONFIG 0xB1000004 | |
424 | #define I2S_CONFIG_XU (1<<25) | |
425 | #define I2S_CONFIG_XO (1<<24) | |
426 | #define I2S_CONFIG_RU (1<<23) | |
427 | #define I2S_CONFIG_RO (1<<22) | |
428 | #define I2S_CONFIG_TR (1<<21) | |
429 | #define I2S_CONFIG_TE (1<<20) | |
430 | #define I2S_CONFIG_TF (1<<19) | |
431 | #define I2S_CONFIG_RR (1<<18) | |
432 | #define I2S_CONFIG_RE (1<<17) | |
433 | #define I2S_CONFIG_RF (1<<16) | |
434 | #define I2S_CONFIG_PD (1<<11) | |
435 | #define I2S_CONFIG_LB (1<<10) | |
436 | #define I2S_CONFIG_IC (1<<9) | |
437 | #define I2S_CONFIG_FM_BIT 7 | |
438 | #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) | |
439 | #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) | |
440 | #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) | |
441 | #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) | |
442 | #define I2S_CONFIG_TN (1<<6) | |
443 | #define I2S_CONFIG_RN (1<<5) | |
444 | #define I2S_CONFIG_SZ_BIT 0 | |
445 | #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) | |
446 | ||
447 | #define I2S_CONTROL 0xB1000008 | |
448 | #define I2S_CONTROL_D (1<<1) | |
449 | #define I2S_CONTROL_CE (1<<0) | |
450 | ||
451 | /* USB Host Controller */ | |
452 | /* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */ | |
453 | #define USB_OHCI_BASE 0x10100000 | |
454 | #define USB_OHCI_LEN 0x00100000 | |
455 | #define USB_HOST_CONFIG 0xB017fffc | |
456 | ||
457 | /* USB Device Controller */ | |
458 | #define USBD_EP0RD 0xB0200000 | |
459 | #define USBD_EP0WR 0xB0200004 | |
460 | #define USBD_EP2WR 0xB0200008 | |
461 | #define USBD_EP3WR 0xB020000C | |
462 | #define USBD_EP4RD 0xB0200010 | |
463 | #define USBD_EP5RD 0xB0200014 | |
464 | #define USBD_INTEN 0xB0200018 | |
465 | #define USBD_INTSTAT 0xB020001C | |
466 | #define USBDEV_INT_SOF (1<<12) | |
467 | #define USBDEV_INT_HF_BIT 6 | |
468 | #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) | |
469 | #define USBDEV_INT_CMPLT_BIT 0 | |
470 | #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) | |
471 | #define USBD_CONFIG 0xB0200020 | |
472 | #define USBD_EP0CS 0xB0200024 | |
473 | #define USBD_EP2CS 0xB0200028 | |
474 | #define USBD_EP3CS 0xB020002C | |
475 | #define USBD_EP4CS 0xB0200030 | |
476 | #define USBD_EP5CS 0xB0200034 | |
477 | #define USBDEV_CS_SU (1<<14) | |
478 | #define USBDEV_CS_NAK (1<<13) | |
479 | #define USBDEV_CS_ACK (1<<12) | |
480 | #define USBDEV_CS_BUSY (1<<11) | |
481 | #define USBDEV_CS_TSIZE_BIT 1 | |
482 | #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) | |
483 | #define USBDEV_CS_STALL (1<<0) | |
484 | #define USBD_EP0RDSTAT 0xB0200040 | |
485 | #define USBD_EP0WRSTAT 0xB0200044 | |
486 | #define USBD_EP2WRSTAT 0xB0200048 | |
487 | #define USBD_EP3WRSTAT 0xB020004C | |
488 | #define USBD_EP4RDSTAT 0xB0200050 | |
489 | #define USBD_EP5RDSTAT 0xB0200054 | |
490 | #define USBDEV_FSTAT_FLUSH (1<<6) | |
491 | #define USBDEV_FSTAT_UF (1<<5) | |
492 | #define USBDEV_FSTAT_OF (1<<4) | |
493 | #define USBDEV_FSTAT_FCNT_BIT 0 | |
494 | #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) | |
495 | #define USBD_ENABLE 0xB0200058 | |
496 | #define USBDEV_ENABLE (1<<1) | |
497 | #define USBDEV_CE (1<<0) | |
498 | ||
499 | /* Ethernet Controllers */ | |
500 | #define AU1000_ETH0_BASE 0xB0500000 | |
501 | #define AU1000_ETH1_BASE 0xB0510000 | |
502 | #define AU1500_ETH0_BASE 0xB1500000 | |
503 | #define AU1500_ETH1_BASE 0xB1510000 | |
504 | #define AU1100_ETH0_BASE 0xB0500000 | |
ff36fd85 WD |
505 | #define AU1550_ETH0_BASE 0xB0500000 |
506 | #define AU1550_ETH1_BASE 0xB0510000 | |
5da627a4 WD |
507 | |
508 | /* 4 byte offsets from AU1000_ETH_BASE */ | |
509 | #define MAC_CONTROL 0x0 | |
510 | #define MAC_RX_ENABLE (1<<2) | |
511 | #define MAC_TX_ENABLE (1<<3) | |
512 | #define MAC_DEF_CHECK (1<<5) | |
513 | #define MAC_SET_BL(X) (((X)&0x3)<<6) | |
514 | #define MAC_AUTO_PAD (1<<8) | |
515 | #define MAC_DISABLE_RETRY (1<<10) | |
516 | #define MAC_DISABLE_BCAST (1<<11) | |
517 | #define MAC_LATE_COL (1<<12) | |
518 | #define MAC_HASH_MODE (1<<13) | |
519 | #define MAC_HASH_ONLY (1<<15) | |
520 | #define MAC_PASS_ALL (1<<16) | |
521 | #define MAC_INVERSE_FILTER (1<<17) | |
522 | #define MAC_PROMISCUOUS (1<<18) | |
523 | #define MAC_PASS_ALL_MULTI (1<<19) | |
524 | #define MAC_FULL_DUPLEX (1<<20) | |
525 | #define MAC_NORMAL_MODE 0 | |
526 | #define MAC_INT_LOOPBACK (1<<21) | |
527 | #define MAC_EXT_LOOPBACK (1<<22) | |
528 | #define MAC_DISABLE_RX_OWN (1<<23) | |
529 | #define MAC_BIG_ENDIAN (1<<30) | |
530 | #define MAC_RX_ALL (1<<31) | |
531 | #define MAC_ADDRESS_HIGH 0x4 | |
532 | #define MAC_ADDRESS_LOW 0x8 | |
533 | #define MAC_MCAST_HIGH 0xC | |
534 | #define MAC_MCAST_LOW 0x10 | |
535 | #define MAC_MII_CNTRL 0x14 | |
536 | #define MAC_MII_BUSY (1<<0) | |
537 | #define MAC_MII_READ 0 | |
538 | #define MAC_MII_WRITE (1<<1) | |
539 | #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) | |
540 | #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) | |
541 | #define MAC_MII_DATA 0x18 | |
542 | #define MAC_FLOW_CNTRL 0x1C | |
543 | #define MAC_FLOW_CNTRL_BUSY (1<<0) | |
544 | #define MAC_FLOW_CNTRL_ENABLE (1<<1) | |
545 | #define MAC_PASS_CONTROL (1<<2) | |
546 | #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) | |
547 | #define MAC_VLAN1_TAG 0x20 | |
548 | #define MAC_VLAN2_TAG 0x24 | |
549 | ||
550 | /* Ethernet Controller Enable */ | |
551 | #define AU1000_MAC0_ENABLE 0xB0520000 | |
552 | #define AU1000_MAC1_ENABLE 0xB0520004 | |
553 | #define AU1500_MAC0_ENABLE 0xB1520000 | |
554 | #define AU1500_MAC1_ENABLE 0xB1520004 | |
555 | #define AU1100_MAC0_ENABLE 0xB0520000 | |
ff36fd85 WD |
556 | #define AU1550_MAC0_ENABLE 0xB0520000 |
557 | #define AU1550_MAC1_ENABLE 0xB0520004 | |
5da627a4 WD |
558 | |
559 | #define MAC_EN_CLOCK_ENABLE (1<<0) | |
560 | #define MAC_EN_RESET0 (1<<1) | |
561 | #define MAC_EN_TOSS (0<<2) | |
562 | #define MAC_EN_CACHEABLE (1<<3) | |
563 | #define MAC_EN_RESET1 (1<<4) | |
564 | #define MAC_EN_RESET2 (1<<5) | |
565 | #define MAC_DMA_RESET (1<<6) | |
566 | ||
567 | /* Ethernet Controller DMA Channels */ | |
568 | ||
569 | #define MAC0_TX_DMA_ADDR 0xB4004000 | |
570 | #define MAC1_TX_DMA_ADDR 0xB4004200 | |
571 | /* offsets from MAC_TX_RING_ADDR address */ | |
572 | #define MAC_TX_BUFF0_STATUS 0x0 | |
573 | #define TX_FRAME_ABORTED (1<<0) | |
574 | #define TX_JAB_TIMEOUT (1<<1) | |
575 | #define TX_NO_CARRIER (1<<2) | |
576 | #define TX_LOSS_CARRIER (1<<3) | |
577 | #define TX_EXC_DEF (1<<4) | |
578 | #define TX_LATE_COLL_ABORT (1<<5) | |
579 | #define TX_EXC_COLL (1<<6) | |
580 | #define TX_UNDERRUN (1<<7) | |
581 | #define TX_DEFERRED (1<<8) | |
582 | #define TX_LATE_COLL (1<<9) | |
583 | #define TX_COLL_CNT_MASK (0xF<<10) | |
584 | #define TX_PKT_RETRY (1<<31) | |
585 | #define MAC_TX_BUFF0_ADDR 0x4 | |
586 | #define TX_DMA_ENABLE (1<<0) | |
587 | #define TX_T_DONE (1<<1) | |
588 | #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) | |
589 | #define MAC_TX_BUFF0_LEN 0x8 | |
590 | #define MAC_TX_BUFF1_STATUS 0x10 | |
591 | #define MAC_TX_BUFF1_ADDR 0x14 | |
592 | #define MAC_TX_BUFF1_LEN 0x18 | |
593 | #define MAC_TX_BUFF2_STATUS 0x20 | |
594 | #define MAC_TX_BUFF2_ADDR 0x24 | |
595 | #define MAC_TX_BUFF2_LEN 0x28 | |
596 | #define MAC_TX_BUFF3_STATUS 0x30 | |
597 | #define MAC_TX_BUFF3_ADDR 0x34 | |
598 | #define MAC_TX_BUFF3_LEN 0x38 | |
599 | ||
600 | #define MAC0_RX_DMA_ADDR 0xB4004100 | |
601 | #define MAC1_RX_DMA_ADDR 0xB4004300 | |
602 | /* offsets from MAC_RX_RING_ADDR */ | |
603 | #define MAC_RX_BUFF0_STATUS 0x0 | |
604 | #define RX_FRAME_LEN_MASK 0x3fff | |
605 | #define RX_WDOG_TIMER (1<<14) | |
606 | #define RX_RUNT (1<<15) | |
607 | #define RX_OVERLEN (1<<16) | |
608 | #define RX_COLL (1<<17) | |
609 | #define RX_ETHER (1<<18) | |
610 | #define RX_MII_ERROR (1<<19) | |
611 | #define RX_DRIBBLING (1<<20) | |
612 | #define RX_CRC_ERROR (1<<21) | |
613 | #define RX_VLAN1 (1<<22) | |
614 | #define RX_VLAN2 (1<<23) | |
615 | #define RX_LEN_ERROR (1<<24) | |
616 | #define RX_CNTRL_FRAME (1<<25) | |
617 | #define RX_U_CNTRL_FRAME (1<<26) | |
618 | #define RX_MCAST_FRAME (1<<27) | |
619 | #define RX_BCAST_FRAME (1<<28) | |
620 | #define RX_FILTER_FAIL (1<<29) | |
621 | #define RX_PACKET_FILTER (1<<30) | |
622 | #define RX_MISSED_FRAME (1<<31) | |
623 | ||
624 | #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | |
42d1f039 WD |
625 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ |
626 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | |
5da627a4 WD |
627 | #define MAC_RX_BUFF0_ADDR 0x4 |
628 | #define RX_DMA_ENABLE (1<<0) | |
629 | #define RX_T_DONE (1<<1) | |
630 | #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) | |
631 | #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) | |
632 | #define MAC_RX_BUFF1_STATUS 0x10 | |
633 | #define MAC_RX_BUFF1_ADDR 0x14 | |
634 | #define MAC_RX_BUFF2_STATUS 0x20 | |
635 | #define MAC_RX_BUFF2_ADDR 0x24 | |
636 | #define MAC_RX_BUFF3_STATUS 0x30 | |
637 | #define MAC_RX_BUFF3_ADDR 0x34 | |
638 | ||
639 | ||
640 | /* UARTS 0-3 */ | |
641 | #define UART0_ADDR 0xB1100000 | |
642 | #define UART1_ADDR 0xB1200000 | |
643 | #define UART2_ADDR 0xB1300000 | |
644 | #define UART3_ADDR 0xB1400000 | |
645 | #define UART_BASE UART0_ADDR | |
646 | #define UART_DEBUG_BASE UART2_ADDR | |
647 | ||
648 | #define UART_RX 0 /* Receive buffer */ | |
649 | #define UART_TX 4 /* Transmit buffer */ | |
650 | #define UART_IER 8 /* Interrupt Enable Register */ | |
651 | #define UART_IIR 0xC /* Interrupt ID Register */ | |
652 | #define UART_FCR 0x10 /* FIFO Control Register */ | |
653 | #define UART_LCR 0x14 /* Line Control Register */ | |
654 | #define UART_MCR 0x18 /* Modem Control Register */ | |
655 | #define UART_LSR 0x1C /* Line Status Register */ | |
656 | #define UART_MSR 0x20 /* Modem Status Register */ | |
657 | #define UART_CLK 0x28 /* Baud Rate Clock Divider */ | |
658 | #define UART_ENABLE 0x100 /* Uart enable */ | |
659 | ||
660 | #define UART_EN_CE 1 /* Clock enable */ | |
661 | #define UART_EN_E 2 /* Enable */ | |
662 | ||
663 | #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ | |
664 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ | |
665 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ | |
666 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ | |
667 | #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ | |
668 | #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ | |
669 | #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ | |
670 | #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ | |
671 | #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ | |
672 | #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ | |
673 | #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ | |
674 | #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ | |
675 | #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ | |
676 | ||
677 | /* | |
678 | * These are the definitions for the Line Control Register | |
679 | */ | |
680 | #define UART_LCR_SBC 0x40 /* Set break control */ | |
681 | #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ | |
682 | #define UART_LCR_EPAR 0x10 /* Even parity select */ | |
683 | #define UART_LCR_PARITY 0x08 /* Parity Enable */ | |
684 | #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ | |
685 | #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ | |
686 | #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ | |
687 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ | |
688 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ | |
689 | ||
690 | /* | |
691 | * These are the definitions for the Line Status Register | |
692 | */ | |
693 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
694 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
695 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
696 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
697 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
698 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
699 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
700 | ||
701 | /* | |
702 | * These are the definitions for the Interrupt Identification Register | |
703 | */ | |
704 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
705 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
706 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
707 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
708 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
709 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
710 | ||
711 | /* | |
712 | * These are the definitions for the Interrupt Enable Register | |
713 | */ | |
714 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
715 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
716 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
717 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
718 | ||
719 | /* | |
720 | * These are the definitions for the Modem Control Register | |
721 | */ | |
722 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
723 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
724 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
725 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
726 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
727 | ||
728 | /* | |
729 | * These are the definitions for the Modem Status Register | |
730 | */ | |
731 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
732 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
733 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
734 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
735 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
736 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
737 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
738 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
739 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
740 | ||
741 | ||
5da627a4 WD |
742 | /* SSIO */ |
743 | #define SSI0_STATUS 0xB1600000 | |
744 | #define SSI_STATUS_BF (1<<4) | |
745 | #define SSI_STATUS_OF (1<<3) | |
746 | #define SSI_STATUS_UF (1<<2) | |
747 | #define SSI_STATUS_D (1<<1) | |
748 | #define SSI_STATUS_B (1<<0) | |
749 | #define SSI0_INT 0xB1600004 | |
750 | #define SSI_INT_OI (1<<3) | |
751 | #define SSI_INT_UI (1<<2) | |
752 | #define SSI_INT_DI (1<<1) | |
753 | #define SSI0_INT_ENABLE 0xB1600008 | |
754 | #define SSI_INTE_OIE (1<<3) | |
755 | #define SSI_INTE_UIE (1<<2) | |
756 | #define SSI_INTE_DIE (1<<1) | |
757 | #define SSI0_CONFIG 0xB1600020 | |
758 | #define SSI_CONFIG_AO (1<<24) | |
759 | #define SSI_CONFIG_DO (1<<23) | |
760 | #define SSI_CONFIG_ALEN_BIT 20 | |
761 | #define SSI_CONFIG_ALEN_MASK (0x7<<20) | |
762 | #define SSI_CONFIG_DLEN_BIT 16 | |
763 | #define SSI_CONFIG_DLEN_MASK (0x7<<16) | |
764 | #define SSI_CONFIG_DD (1<<11) | |
765 | #define SSI_CONFIG_AD (1<<10) | |
766 | #define SSI_CONFIG_BM_BIT 8 | |
767 | #define SSI_CONFIG_BM_MASK (0x3<<8) | |
768 | #define SSI_CONFIG_CE (1<<7) | |
769 | #define SSI_CONFIG_DP (1<<6) | |
770 | #define SSI_CONFIG_DL (1<<5) | |
771 | #define SSI_CONFIG_EP (1<<4) | |
772 | #define SSI0_ADATA 0xB1600024 | |
773 | #define SSI_AD_D (1<<24) | |
774 | #define SSI_AD_ADDR_BIT 16 | |
775 | #define SSI_AD_ADDR_MASK (0xff<<16) | |
776 | #define SSI_AD_DATA_BIT 0 | |
777 | #define SSI_AD_DATA_MASK (0xfff<<0) | |
778 | #define SSI0_CLKDIV 0xB1600028 | |
779 | #define SSI0_CONTROL 0xB1600100 | |
780 | #define SSI_CONTROL_CD (1<<1) | |
781 | #define SSI_CONTROL_E (1<<0) | |
782 | ||
783 | /* SSI1 */ | |
784 | #define SSI1_STATUS 0xB1680000 | |
785 | #define SSI1_INT 0xB1680004 | |
786 | #define SSI1_INT_ENABLE 0xB1680008 | |
787 | #define SSI1_CONFIG 0xB1680020 | |
788 | #define SSI1_ADATA 0xB1680024 | |
789 | #define SSI1_CLKDIV 0xB1680028 | |
790 | #define SSI1_ENABLE 0xB1680100 | |
791 | ||
792 | /* | |
793 | * Register content definitions | |
794 | */ | |
795 | #define SSI_STATUS_BF (1<<4) | |
796 | #define SSI_STATUS_OF (1<<3) | |
797 | #define SSI_STATUS_UF (1<<2) | |
798 | #define SSI_STATUS_D (1<<1) | |
799 | #define SSI_STATUS_B (1<<0) | |
800 | ||
801 | /* SSI_INT */ | |
802 | #define SSI_INT_OI (1<<3) | |
803 | #define SSI_INT_UI (1<<2) | |
804 | #define SSI_INT_DI (1<<1) | |
805 | ||
806 | /* SSI_INTEN */ | |
807 | #define SSI_INTEN_OIE (1<<3) | |
808 | #define SSI_INTEN_UIE (1<<2) | |
809 | #define SSI_INTEN_DIE (1<<1) | |
810 | ||
811 | #define SSI_CONFIG_AO (1<<24) | |
812 | #define SSI_CONFIG_DO (1<<23) | |
813 | #define SSI_CONFIG_ALEN (7<<20) | |
814 | #define SSI_CONFIG_DLEN (15<<16) | |
815 | #define SSI_CONFIG_DD (1<<11) | |
816 | #define SSI_CONFIG_AD (1<<10) | |
817 | #define SSI_CONFIG_BM (3<<8) | |
818 | #define SSI_CONFIG_CE (1<<7) | |
819 | #define SSI_CONFIG_DP (1<<6) | |
820 | #define SSI_CONFIG_DL (1<<5) | |
821 | #define SSI_CONFIG_EP (1<<4) | |
822 | #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) | |
823 | #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) | |
824 | #define SSI_CONFIG_BM_HI (0<<8) | |
825 | #define SSI_CONFIG_BM_LO (1<<8) | |
826 | #define SSI_CONFIG_BM_CY (2<<8) | |
827 | ||
828 | #define SSI_ADATA_D (1<<24) | |
829 | #define SSI_ADATA_ADDR (0xFF<<16) | |
830 | #define SSI_ADATA_DATA (0x0FFF) | |
831 | #define SSI_ADATA_ADDR_N(N) (N<<16) | |
832 | ||
833 | #define SSI_ENABLE_CD (1<<1) | |
834 | #define SSI_ENABLE_E (1<<0) | |
835 | ||
836 | ||
837 | /* IrDA Controller */ | |
838 | #define IRDA_BASE 0xB0300000 | |
839 | #define IR_RING_PTR_STATUS (IRDA_BASE+0x00) | |
840 | #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) | |
841 | #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) | |
842 | #define IR_RING_SIZE (IRDA_BASE+0x0C) | |
843 | #define IR_RING_PROMPT (IRDA_BASE+0x10) | |
844 | #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) | |
845 | #define IR_INT_CLEAR (IRDA_BASE+0x18) | |
846 | #define IR_CONFIG_1 (IRDA_BASE+0x20) | |
847 | #define IR_RX_INVERT_LED (1<<0) | |
848 | #define IR_TX_INVERT_LED (1<<1) | |
849 | #define IR_ST (1<<2) | |
850 | #define IR_SF (1<<3) | |
851 | #define IR_SIR (1<<4) | |
852 | #define IR_MIR (1<<5) | |
853 | #define IR_FIR (1<<6) | |
854 | #define IR_16CRC (1<<7) | |
855 | #define IR_TD (1<<8) | |
856 | #define IR_RX_ALL (1<<9) | |
857 | #define IR_DMA_ENABLE (1<<10) | |
858 | #define IR_RX_ENABLE (1<<11) | |
859 | #define IR_TX_ENABLE (1<<12) | |
860 | #define IR_LOOPBACK (1<<14) | |
861 | #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ | |
42d1f039 | 862 | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) |
5da627a4 WD |
863 | #define IR_SIR_FLAGS (IRDA_BASE+0x24) |
864 | #define IR_ENABLE (IRDA_BASE+0x28) | |
865 | #define IR_RX_STATUS (1<<9) | |
866 | #define IR_TX_STATUS (1<<10) | |
867 | #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) | |
868 | #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) | |
869 | #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) | |
870 | #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) | |
871 | #define IR_CONFIG_2 (IRDA_BASE+0x3C) | |
872 | #define IR_MODE_INV (1<<0) | |
873 | #define IR_ONE_PIN (1<<1) | |
874 | #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) | |
875 | ||
876 | /* GPIO */ | |
877 | #define SYS_PINFUNC 0xB190002C | |
878 | #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ | |
879 | #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ | |
880 | #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ | |
881 | #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ | |
882 | #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ | |
883 | #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ | |
884 | #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ | |
885 | #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ | |
886 | #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ | |
887 | #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ | |
888 | #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ | |
889 | #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ | |
890 | #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ | |
891 | #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ | |
892 | #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ | |
893 | #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ | |
894 | #define SYS_TRIOUTRD 0xB1900100 | |
895 | #define SYS_TRIOUTCLR 0xB1900100 | |
896 | #define SYS_OUTPUTRD 0xB1900108 | |
897 | #define SYS_OUTPUTSET 0xB1900108 | |
898 | #define SYS_OUTPUTCLR 0xB190010C | |
899 | #define SYS_PINSTATERD 0xB1900110 | |
900 | #define SYS_PININPUTEN 0xB1900110 | |
901 | ||
902 | /* GPIO2, Au1500 only */ | |
903 | #define GPIO2_BASE 0xB1700000 | |
904 | #define GPIO2_DIR (GPIO2_BASE + 0) | |
905 | #define GPIO2_DATA_EN (GPIO2_BASE + 8) | |
906 | #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) | |
907 | #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10) | |
908 | #define GPIO2_ENABLE (GPIO2_BASE + 0x14) | |
909 | ||
910 | /* Power Management */ | |
911 | #define SYS_SCRATCH0 0xB1900018 | |
912 | #define SYS_SCRATCH1 0xB190001C | |
913 | #define SYS_WAKEMSK 0xB1900034 | |
914 | #define SYS_ENDIAN 0xB1900038 | |
915 | #define SYS_POWERCTRL 0xB190003C | |
916 | #define SYS_WAKESRC 0xB190005C | |
917 | #define SYS_SLPPWR 0xB1900078 | |
918 | #define SYS_SLEEP 0xB190007C | |
919 | ||
920 | /* Clock Controller */ | |
921 | #define SYS_FREQCTRL0 0xB1900020 | |
922 | #define SYS_FC_FRDIV2_BIT 22 | |
923 | #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) | |
924 | #define SYS_FC_FE2 (1<<21) | |
925 | #define SYS_FC_FS2 (1<<20) | |
926 | #define SYS_FC_FRDIV1_BIT 12 | |
927 | #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) | |
928 | #define SYS_FC_FE1 (1<<11) | |
929 | #define SYS_FC_FS1 (1<<10) | |
930 | #define SYS_FC_FRDIV0_BIT 2 | |
931 | #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) | |
932 | #define SYS_FC_FE0 (1<<1) | |
933 | #define SYS_FC_FS0 (1<<0) | |
934 | #define SYS_FREQCTRL1 0xB1900024 | |
935 | #define SYS_FC_FRDIV5_BIT 22 | |
936 | #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) | |
937 | #define SYS_FC_FE5 (1<<21) | |
938 | #define SYS_FC_FS5 (1<<20) | |
939 | #define SYS_FC_FRDIV4_BIT 12 | |
940 | #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) | |
941 | #define SYS_FC_FE4 (1<<11) | |
942 | #define SYS_FC_FS4 (1<<10) | |
943 | #define SYS_FC_FRDIV3_BIT 2 | |
944 | #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) | |
945 | #define SYS_FC_FE3 (1<<1) | |
946 | #define SYS_FC_FS3 (1<<0) | |
947 | #define SYS_CLKSRC 0xB1900028 | |
948 | #define SYS_CS_ME1_BIT 27 | |
949 | #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT) | |
950 | #define SYS_CS_DE1 (1<<26) | |
951 | #define SYS_CS_CE1 (1<<25) | |
952 | #define SYS_CS_ME0_BIT 22 | |
953 | #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT) | |
954 | #define SYS_CS_DE0 (1<<21) | |
955 | #define SYS_CS_CE0 (1<<20) | |
956 | #define SYS_CS_MI2_BIT 17 | |
957 | #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT) | |
958 | #define SYS_CS_DI2 (1<<16) | |
959 | #define SYS_CS_CI2 (1<<15) | |
960 | #define SYS_CS_MUH_BIT 12 | |
961 | #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT) | |
962 | #define SYS_CS_DUH (1<<11) | |
963 | #define SYS_CS_CUH (1<<10) | |
964 | #define SYS_CS_MUD_BIT 7 | |
965 | #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT) | |
966 | #define SYS_CS_DUD (1<<6) | |
967 | #define SYS_CS_CUD (1<<5) | |
968 | #define SYS_CS_MIR_BIT 2 | |
969 | #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT) | |
970 | #define SYS_CS_DIR (1<<1) | |
971 | #define SYS_CS_CIR (1<<0) | |
972 | ||
973 | #define SYS_CS_MUX_AUX 0x1 | |
974 | #define SYS_CS_MUX_FQ0 0x2 | |
975 | #define SYS_CS_MUX_FQ1 0x3 | |
976 | #define SYS_CS_MUX_FQ2 0x4 | |
977 | #define SYS_CS_MUX_FQ3 0x5 | |
978 | #define SYS_CS_MUX_FQ4 0x6 | |
979 | #define SYS_CS_MUX_FQ5 0x7 | |
980 | #define SYS_CPUPLL 0xB1900060 | |
981 | #define SYS_AUXPLL 0xB1900064 | |
982 | ||
983 | /* AC97 Controller */ | |
984 | #define AC97C_CONFIG 0xB0000000 | |
985 | #define AC97C_RECV_SLOTS_BIT 13 | |
986 | #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) | |
987 | #define AC97C_XMIT_SLOTS_BIT 3 | |
988 | #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) | |
989 | #define AC97C_SG (1<<2) | |
990 | #define AC97C_SYNC (1<<1) | |
991 | #define AC97C_RESET (1<<0) | |
992 | #define AC97C_STATUS 0xB0000004 | |
993 | #define AC97C_XU (1<<11) | |
994 | #define AC97C_XO (1<<10) | |
995 | #define AC97C_RU (1<<9) | |
996 | #define AC97C_RO (1<<8) | |
997 | #define AC97C_READY (1<<7) | |
998 | #define AC97C_CP (1<<6) | |
999 | #define AC97C_TR (1<<5) | |
1000 | #define AC97C_TE (1<<4) | |
1001 | #define AC97C_TF (1<<3) | |
1002 | #define AC97C_RR (1<<2) | |
1003 | #define AC97C_RE (1<<1) | |
1004 | #define AC97C_RF (1<<0) | |
1005 | #define AC97C_DATA 0xB0000008 | |
1006 | #define AC97C_CMD 0xB000000C | |
1007 | #define AC97C_WD_BIT 16 | |
1008 | #define AC97C_READ (1<<7) | |
1009 | #define AC97C_INDEX_MASK 0x7f | |
1010 | #define AC97C_CNTRL 0xB0000010 | |
1011 | #define AC97C_RS (1<<1) | |
1012 | #define AC97C_CE (1<<0) | |
1013 | ||
ff36fd85 WD |
1014 | #define DB1000_BCSR_ADDR 0xAE000000 |
1015 | #define DB1550_BCSR_ADDR 0xAF000000 | |
1016 | ||
1017 | #ifdef CONFIG_DBAU1550 | |
1018 | #define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR | |
1019 | #else | |
1020 | #define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR | |
1021 | #endif | |
1022 | ||
5da627a4 WD |
1023 | #ifdef CONFIG_SOC_AU1500 |
1024 | /* Au1500 PCI Controller */ | |
1025 | #define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */ | |
1026 | #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) | |
1027 | #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) | |
1028 | #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) | |
1029 | #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) | |
1030 | #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) | |
1031 | #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) | |
1032 | #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) | |
1033 | #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) | |
1034 | #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) | |
1035 | #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) | |
1036 | #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) | |
1037 | #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) | |
1038 | #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) | |
1039 | #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) | |
1040 | #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) | |
1041 | ||
1042 | #define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */ | |
1043 | ||
1044 | /* All of our structures, like pci resource, have 32 bit members. | |
1045 | * Drivers are expected to do an ioremap on the PCI MEM resource, but it's | |
1046 | * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch | |
1047 | * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and | |
1048 | * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM | |
1049 | * addresses. For PCI IO, it's simpler because we get to do the ioremap | |
1050 | * ourselves and then adjust the device's resources. | |
1051 | */ | |
1052 | #define Au1500_EXT_CFG 0x600000000 | |
1053 | #define Au1500_EXT_CFG_TYPE1 0x680000000 | |
1054 | #define Au1500_PCI_IO_START 0x500000000 | |
1055 | #define Au1500_PCI_IO_END 0x5000FFFFF | |
1056 | #define Au1500_PCI_MEM_START 0x440000000 | |
1057 | #define Au1500_PCI_MEM_END 0x443FFFFFF | |
1058 | ||
1059 | #define PCI_IO_START (Au1500_PCI_IO_START + 0x300) | |
1060 | #define PCI_IO_END (Au1500_PCI_IO_END) | |
1061 | #define PCI_MEM_START (Au1500_PCI_MEM_START) | |
1062 | #define PCI_MEM_END (Au1500_PCI_MEM_END) | |
1063 | #define PCI_FIRST_DEVFN (0<<3) | |
1064 | #define PCI_LAST_DEVFN (19<<3) | |
1065 | ||
1066 | #endif | |
1067 | ||
1068 | #if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000)) | |
1069 | /* no PCI bus controller */ | |
1070 | #define PCI_IO_START 0 | |
1071 | #define PCI_IO_END 0 | |
1072 | #define PCI_MEM_START 0 | |
1073 | #define PCI_MEM_END 0 | |
1074 | #define PCI_FIRST_DEVFN 0 | |
1075 | #define PCI_LAST_DEVFN 0 | |
1076 | #endif | |
1077 | #define AU1X_SOCK0_IO 0xF00000000 | |
1078 | #define AU1X_SOCK0_PHYS_ATTR 0xF40000000 | |
1079 | #define AU1X_SOCK0_PHYS_MEM 0xF80000000 | |
1080 | ||
1081 | /* pcmcia socket 1 needs external glue logic so the memory map | |
1082 | * differs from board to board. | |
1083 | */ | |
1084 | ||
1085 | /* Only for db board, not older pb */ | |
1086 | #define AU1X_SOCK1_IO 0xF04000000 | |
1087 | #define AU1X_SOCK1_PHYS_ATTR 0xF44000000 | |
1088 | #define AU1X_SOCK1_PHYS_MEM 0xF84000000 | |
1089 | ||
1090 | #endif |