projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c021880a WD |
1 | |
| 2 | /****************************************************************************** | |
| 3 | Copyright (c) 2002, Infineon Technologies. All rights reserved. | |
| 4 | ||
| 8bde7f77 WD |
5 | No Warranty |
| 6 | Because the program is licensed free of charge, there is no warranty for | |
| 7 | the program, to the extent permitted by applicable law. Except when | |
| 8 | otherwise stated in writing the copyright holders and/or other parties | |
| 9 | provide the program "as is" without warranty of any kind, either | |
| 10 | expressed or implied, including, but not limited to, the implied | |
| 11 | warranties of merchantability and fitness for a particular purpose. The | |
| 12 | entire risk as to the quality and performance of the program is with | |
| 13 | you. should the program prove defective, you assume the cost of all | |
| 14 | necessary servicing, repair or correction. | |
| 15 | ||
| 16 | In no event unless required by applicable law or agreed to in writing | |
| 17 | will any copyright holder, or any other party who may modify and/or | |
| 18 | redistribute the program as permitted above, be liable to you for | |
| 19 | damages, including any general, special, incidental or consequential | |
| 20 | damages arising out of the use or inability to use the program | |
| 21 | (including but not limited to loss of data or data being rendered | |
| 22 | inaccurate or losses sustained by you or third parties or a failure of | |
| 23 | the program to operate with any other programs), even if such holder or | |
| 24 | other party has been advised of the possibility of such damages. | |
| c021880a | 25 | ******************************************************************************/ |
| 8bde7f77 WD |
26 | |
| 27 | ||
| c021880a WD |
28 | /***********************************************************************/ |
| 29 | /* Module : WDT register address and bits */ | |
| 30 | /***********************************************************************/ | |
| 8bde7f77 | 31 | |
| c021880a | 32 | #define INCA_IP_WDT (0xB8000000) |
| 8bde7f77 WD |
33 | /***********************************************************************/ |
| 34 | ||
| c021880a | 35 | |
| 8bde7f77 | 36 | /***Reset Status Register Power On***/ |
| c021880a | 37 | #define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) |
| 8bde7f77 WD |
38 | |
| 39 | /***Reset Request Register***/ | |
| c021880a WD |
40 | #define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010)) |
| 41 | #define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24) | |
| 42 | #define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16) | |
| 43 | #define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5) | |
| 44 | #define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4) | |
| 45 | #define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3) | |
| 46 | #define INCA_IP_WDT_RST_REQ_RREXT (1 << 2) | |
| 47 | #define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1) | |
| 48 | #define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) | |
| 8bde7f77 WD |
49 | |
| 50 | /***NMI Status Register***/ | |
| c021880a WD |
51 | #define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C)) |
| 52 | #define INCA_IP_WDT_NMISR_NMIWDT (1 << 2) | |
| 53 | #define INCA_IP_WDT_NMISR_NMIPLL (1 << 1) | |
| 54 | #define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) | |
| 8bde7f77 WD |
55 | |
| 56 | /***Manufacturer Identification Register***/ | |
| c021880a WD |
57 | #define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070)) |
| 58 | #define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) | |
| 8bde7f77 WD |
59 | |
| 60 | /***Chip Identification Register***/ | |
| c021880a WD |
61 | #define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074)) |
| 62 | #define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28) | |
| 63 | #define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12) | |
| 64 | #define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) | |
| 8bde7f77 WD |
65 | |
| 66 | /***Redesign Tracing Identification Register***/ | |
| c021880a WD |
67 | #define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078)) |
| 68 | #define INCA_IP_WDT_RTID_LC (1 << 15) | |
| 69 | #define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
70 | |
| 71 | /***Watchdog Timer Control Register 0***/ | |
| c021880a | 72 | #define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) |
| 8bde7f77 WD |
73 | |
| 74 | /***Watchdog Timer Control Register 1***/ | |
| c021880a WD |
75 | #define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024)) |
| 76 | #define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3) | |
| 77 | #define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) | |
| 8bde7f77 WD |
78 | |
| 79 | /***Watchdog Timer Status Register***/ | |
| c021880a WD |
80 | #define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028)) |
| 81 | #define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16) | |
| 82 | #define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5) | |
| 83 | #define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4) | |
| 84 | #define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3) | |
| 85 | #define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2) | |
| 86 | #define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1) | |
| 8bde7f77 WD |
87 | #define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) |
| 88 | ||
| c021880a WD |
89 | /***********************************************************************/ |
| 90 | /* Module : CGU register address and bits */ | |
| 91 | /***********************************************************************/ | |
| 8bde7f77 | 92 | |
| c021880a | 93 | #define INCA_IP_CGU (0xBF107000) |
| 8bde7f77 WD |
94 | /***********************************************************************/ |
| 95 | ||
| c021880a | 96 | |
| 8bde7f77 | 97 | /***CGU PLL1 Control Register***/ |
| c021880a WD |
98 | #define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008)) |
| 99 | #define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31) | |
| 100 | #define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30) | |
| 101 | #define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) | |
| 102 | #define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
103 | |
| 104 | /***CGU PLL0 Control Register***/ | |
| c021880a WD |
105 | #define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000)) |
| 106 | #define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31) | |
| 107 | #define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30) | |
| 108 | #define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) | |
| 109 | #define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
110 | |
| 111 | /***CGU PLL0 Status Register***/ | |
| c021880a WD |
112 | #define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004)) |
| 113 | #define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31) | |
| 114 | #define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29) | |
| 115 | #define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) | |
| 8bde7f77 WD |
116 | |
| 117 | /***CGU PLL1 Status Register***/ | |
| c021880a WD |
118 | #define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C)) |
| 119 | #define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31) | |
| 120 | #define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29) | |
| 121 | #define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) | |
| 8bde7f77 WD |
122 | |
| 123 | /***CGU Divider Control Register***/ | |
| c021880a | 124 | #define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) |
| 8bde7f77 WD |
125 | |
| 126 | /***CGU Multiplexer Control Register***/ | |
| c021880a WD |
127 | #define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014)) |
| 128 | #define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31) | |
| 129 | #define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1) | |
| 130 | #define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) | |
| 8bde7f77 WD |
131 | |
| 132 | /***CGU Fractional Divider Control Register***/ | |
| c021880a WD |
133 | #define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018)) |
| 134 | #define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31) | |
| 135 | #define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16) | |
| 8bde7f77 WD |
136 | #define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) |
| 137 | ||
| c021880a WD |
138 | /***********************************************************************/ |
| 139 | /* Module : PMU register address and bits */ | |
| 140 | /***********************************************************************/ | |
| 8bde7f77 | 141 | |
| c021880a | 142 | #define INCA_IP_PMU (0xBF102000) |
| 8bde7f77 WD |
143 | /***********************************************************************/ |
| 144 | ||
| c021880a | 145 | |
| 8bde7f77 | 146 | /***PM Global Enable Register***/ |
| c021880a WD |
147 | #define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000)) |
| 148 | #define INCA_IP_PMU_PM_GEN_EN16 (1 << 16) | |
| 149 | #define INCA_IP_PMU_PM_GEN_EN15 (1 << 15) | |
| 150 | #define INCA_IP_PMU_PM_GEN_EN14 (1 << 14) | |
| 151 | #define INCA_IP_PMU_PM_GEN_EN13 (1 << 13) | |
| 152 | #define INCA_IP_PMU_PM_GEN_EN12 (1 << 12) | |
| 153 | #define INCA_IP_PMU_PM_GEN_EN11 (1 << 11) | |
| 154 | #define INCA_IP_PMU_PM_GEN_EN10 (1 << 10) | |
| 155 | #define INCA_IP_PMU_PM_GEN_EN9 (1 << 9) | |
| 156 | #define INCA_IP_PMU_PM_GEN_EN8 (1 << 8) | |
| 157 | #define INCA_IP_PMU_PM_GEN_EN7 (1 << 7) | |
| 158 | #define INCA_IP_PMU_PM_GEN_EN6 (1 << 6) | |
| 159 | #define INCA_IP_PMU_PM_GEN_EN5 (1 << 5) | |
| 160 | #define INCA_IP_PMU_PM_GEN_EN4 (1 << 4) | |
| 161 | #define INCA_IP_PMU_PM_GEN_EN3 (1 << 3) | |
| 162 | #define INCA_IP_PMU_PM_GEN_EN2 (1 << 2) | |
| 163 | #define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) | |
| 8bde7f77 WD |
164 | |
| 165 | /***PM Power Down Enable Register***/ | |
| c021880a WD |
166 | #define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008)) |
| 167 | #define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16) | |
| 168 | #define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15) | |
| 169 | #define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14) | |
| 170 | #define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13) | |
| 171 | #define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12) | |
| 172 | #define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11) | |
| 173 | #define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10) | |
| 174 | #define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9) | |
| 175 | #define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8) | |
| 176 | #define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7) | |
| 177 | #define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5) | |
| 178 | #define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4) | |
| 179 | #define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3) | |
| 180 | #define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2) | |
| 181 | #define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) | |
| 8bde7f77 WD |
182 | |
| 183 | /***PM Wake-Up from Power Down Register***/ | |
| c021880a WD |
184 | #define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010)) |
| 185 | #define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16) | |
| 186 | #define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15) | |
| 187 | #define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14) | |
| 188 | #define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13) | |
| 189 | #define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12) | |
| 190 | #define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11) | |
| 191 | #define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10) | |
| 192 | #define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9) | |
| 193 | #define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8) | |
| 194 | #define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7) | |
| 195 | #define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5) | |
| 196 | #define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4) | |
| 197 | #define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3) | |
| 198 | #define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2) | |
| 199 | #define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) | |
| 8bde7f77 WD |
200 | |
| 201 | /***PM Control Register***/ | |
| c021880a WD |
202 | #define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014)) |
| 203 | #define INCA_IP_PMU_PM_CR_AWEN (1 << 31) | |
| 204 | #define INCA_IP_PMU_PM_CR_SWRST (1 << 30) | |
| 205 | #define INCA_IP_PMU_PM_CR_SWCR (1 << 2) | |
| 8bde7f77 WD |
206 | #define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) |
| 207 | ||
| c021880a WD |
208 | /***********************************************************************/ |
| 209 | /* Module : BCU register address and bits */ | |
| 210 | /***********************************************************************/ | |
| 8bde7f77 | 211 | |
| c021880a | 212 | #define INCA_IP_BCU (0xB8000100) |
| 8bde7f77 WD |
213 | /***********************************************************************/ |
| 214 | ||
| c021880a | 215 | |
| 8bde7f77 | 216 | /***BCU Control Register (0010H)***/ |
| c021880a WD |
217 | #define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010)) |
| 218 | #define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) | |
| 219 | #define INCA_IP_BCU_BCU_CON_SPE (1 << 19) | |
| 220 | #define INCA_IP_BCU_BCU_CON_PSE (1 << 18) | |
| 221 | #define INCA_IP_BCU_BCU_CON_DBG (1 << 16) | |
| 222 | #define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
223 | |
| 224 | /***BCU Error Control Capture Register (0020H)***/ | |
| c021880a WD |
225 | #define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020)) |
| 226 | #define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) | |
| 227 | #define INCA_IP_BCU_BCU_ECON_RDN (1 << 23) | |
| 228 | #define INCA_IP_BCU_BCU_ECON_WRN (1 << 22) | |
| 229 | #define INCA_IP_BCU_BCU_ECON_SVM (1 << 21) | |
| 230 | #define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) | |
| 231 | #define INCA_IP_BCU_BCU_ECON_ABT (1 << 18) | |
| 232 | #define INCA_IP_BCU_BCU_ECON_RDY (1 << 17) | |
| 233 | #define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16) | |
| 234 | #define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 235 | #define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) | |
| 8bde7f77 WD |
236 | |
| 237 | /***BCU Error Address Capture Register (0024 H)***/ | |
| c021880a WD |
238 | #define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024)) |
| 239 | #define INCA_IP_BCU_BCU_EADD_FPIADR | |
| 8bde7f77 WD |
240 | |
| 241 | /***BCU Error Data Capture Register (0028H)***/ | |
| c021880a | 242 | #define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028)) |
| 8bde7f77 WD |
243 | #define INCA_IP_BCU_BCU_EDAT_FPIDAT |
| 244 | ||
| c021880a WD |
245 | /***********************************************************************/ |
| 246 | /* Module : MBC register address and bits */ | |
| 247 | /***********************************************************************/ | |
| 8bde7f77 | 248 | |
| c021880a | 249 | #define INCA_IP_MBC (0xBF103000) |
| 8bde7f77 | 250 | /***********************************************************************/ |
| c021880a | 251 | |
| 8bde7f77 WD |
252 | |
| 253 | /***Mailbox CPU Configuration Register***/ | |
| c021880a WD |
254 | #define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080)) |
| 255 | #define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) | |
| 256 | #define INCA_IP_MBC_MBC_CFG_RES (1 << 5) | |
| 257 | #define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) | |
| 258 | #define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0) | |
| 8bde7f77 WD |
259 | |
| 260 | /***Mailbox CPU Interrupt Status Register***/ | |
| c021880a WD |
261 | #define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084)) |
| 262 | #define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31) | |
| 263 | #define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30) | |
| 264 | #define INCA_IP_MBC_MBC_ISR_B1E (1 << 29) | |
| 265 | #define INCA_IP_MBC_MBC_ISR_B0E (1 << 28) | |
| 266 | #define INCA_IP_MBC_MBC_ISR_WDT (1 << 27) | |
| 267 | #define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
268 | |
| 269 | /***Mailbox CPU Mask Register***/ | |
| c021880a WD |
270 | #define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088)) |
| 271 | #define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31) | |
| 272 | #define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30) | |
| 273 | #define INCA_IP_MBC_MBC_MSK_B1E (1 << 29) | |
| 274 | #define INCA_IP_MBC_MBC_MSK_B0E (1 << 28) | |
| 275 | #define INCA_IP_MBC_MBC_MSK_WDT (1 << 27) | |
| 276 | #define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
277 | |
| 278 | /***Mailbox CPU Mask 01 Register***/ | |
| c021880a WD |
279 | #define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C)) |
| 280 | #define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31) | |
| 281 | #define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30) | |
| 282 | #define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29) | |
| 283 | #define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28) | |
| 284 | #define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27) | |
| 285 | #define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
286 | |
| 287 | /***Mailbox CPU Mask 10 Register***/ | |
| c021880a WD |
288 | #define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090)) |
| 289 | #define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31) | |
| 290 | #define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30) | |
| 291 | #define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29) | |
| 292 | #define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28) | |
| 293 | #define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27) | |
| 294 | #define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
295 | |
| 296 | /***Mailbox CPU Short Command Register***/ | |
| c021880a WD |
297 | #define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094)) |
| 298 | #define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
299 | |
| 300 | /***Mailbox CPU Input Data of Buffer 0***/ | |
| c021880a WD |
301 | #define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000)) |
| 302 | #define INCA_IP_MBC_MBC_ID0_INDATA | |
| 8bde7f77 WD |
303 | |
| 304 | /***Mailbox CPU Input Data of Buffer 1***/ | |
| c021880a WD |
305 | #define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020)) |
| 306 | #define INCA_IP_MBC_MBC_ID1_INDATA | |
| 8bde7f77 WD |
307 | |
| 308 | /***Mailbox CPU Output Data of Buffer 2***/ | |
| c021880a WD |
309 | #define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040)) |
| 310 | #define INCA_IP_MBC_MBC_OD2_OUTDATA | |
| 8bde7f77 WD |
311 | |
| 312 | /***Mailbox CPU Output Data of Buffer 3***/ | |
| c021880a WD |
313 | #define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060)) |
| 314 | #define INCA_IP_MBC_MBC_OD3_OUTDATA | |
| 8bde7f77 WD |
315 | |
| 316 | /***Mailbox CPU Control Register of Buffer 0***/ | |
| c021880a WD |
317 | #define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004)) |
| 318 | #define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
319 | |
| 320 | /***Mailbox CPU Control Register of Buffer 1***/ | |
| c021880a WD |
321 | #define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024)) |
| 322 | #define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
323 | |
| 324 | /***Mailbox CPU Control Register of Buffer 2***/ | |
| c021880a WD |
325 | #define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044)) |
| 326 | #define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
327 | |
| 328 | /***Mailbox CPU Control Register of Buffer 3***/ | |
| c021880a WD |
329 | #define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064)) |
| 330 | #define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
331 | |
| 332 | /***Mailbox CPU Free Space of Buffer 0***/ | |
| c021880a WD |
333 | #define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008)) |
| 334 | #define INCA_IP_MBC_MBC_FS0_FS | |
| 8bde7f77 WD |
335 | |
| 336 | /***Mailbox CPU Free Space of Buffer 1***/ | |
| c021880a WD |
337 | #define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028)) |
| 338 | #define INCA_IP_MBC_MBC_FS1_FS | |
| 8bde7f77 WD |
339 | |
| 340 | /***Mailbox CPU Free Space of Buffer 2***/ | |
| c021880a WD |
341 | #define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048)) |
| 342 | #define INCA_IP_MBC_MBC_FS2_FS | |
| 8bde7f77 WD |
343 | |
| 344 | /***Mailbox CPU Free Space of Buffer 3***/ | |
| c021880a WD |
345 | #define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068)) |
| 346 | #define INCA_IP_MBC_MBC_FS3_FS | |
| 8bde7f77 WD |
347 | |
| 348 | /***Mailbox CPU Data Available in Buffer 0***/ | |
| c021880a WD |
349 | #define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C)) |
| 350 | #define INCA_IP_MBC_MBC_DA0_DA | |
| 8bde7f77 WD |
351 | |
| 352 | /***Mailbox CPU Data Available in Buffer 1***/ | |
| c021880a WD |
353 | #define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C)) |
| 354 | #define INCA_IP_MBC_MBC_DA1_DA | |
| 8bde7f77 WD |
355 | |
| 356 | /***Mailbox CPU Data Available in Buffer 2***/ | |
| c021880a WD |
357 | #define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C)) |
| 358 | #define INCA_IP_MBC_MBC_DA2_DA | |
| 8bde7f77 WD |
359 | |
| 360 | /***Mailbox CPU Data Available in Buffer 3***/ | |
| c021880a WD |
361 | #define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C)) |
| 362 | #define INCA_IP_MBC_MBC_DA3_DA | |
| 8bde7f77 WD |
363 | |
| 364 | /***Mailbox CPU Input Absolute Pointer of Buffer 0***/ | |
| c021880a WD |
365 | #define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010)) |
| 366 | #define INCA_IP_MBC_MBC_IABS0_IABS | |
| 8bde7f77 WD |
367 | |
| 368 | /***Mailbox CPU Input Absolute Pointer of Buffer 1***/ | |
| c021880a WD |
369 | #define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030)) |
| 370 | #define INCA_IP_MBC_MBC_IABS1_IABS | |
| 8bde7f77 WD |
371 | |
| 372 | /***Mailbox CPU Input Absolute Pointer of Buffer 2***/ | |
| c021880a WD |
373 | #define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050)) |
| 374 | #define INCA_IP_MBC_MBC_IABS2_IABS | |
| 8bde7f77 WD |
375 | |
| 376 | /***Mailbox CPU Input Absolute Pointer of Buffer 3***/ | |
| c021880a WD |
377 | #define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070)) |
| 378 | #define INCA_IP_MBC_MBC_IABS3_IABS | |
| 8bde7f77 WD |
379 | |
| 380 | /***Mailbox CPU Input Temporary Pointer of Buffer 0***/ | |
| c021880a WD |
381 | #define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014)) |
| 382 | #define INCA_IP_MBC_MBC_ITMP0_ITMP | |
| 8bde7f77 WD |
383 | |
| 384 | /***Mailbox CPU Input Temporary Pointer of Buffer 1***/ | |
| c021880a WD |
385 | #define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034)) |
| 386 | #define INCA_IP_MBC_MBC_ITMP1_ITMP | |
| 8bde7f77 WD |
387 | |
| 388 | /***Mailbox CPU Input Temporary Pointer of Buffer 2***/ | |
| c021880a WD |
389 | #define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054)) |
| 390 | #define INCA_IP_MBC_MBC_ITMP2_ITMP | |
| 8bde7f77 WD |
391 | |
| 392 | /***Mailbox CPU Input Temporary Pointer of Buffer 3***/ | |
| c021880a WD |
393 | #define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074)) |
| 394 | #define INCA_IP_MBC_MBC_ITMP3_ITMP | |
| 8bde7f77 WD |
395 | |
| 396 | /***Mailbox CPU Output Absolute Pointer of Buffer 0***/ | |
| c021880a WD |
397 | #define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018)) |
| 398 | #define INCA_IP_MBC_MBC_OABS0_OABS | |
| 8bde7f77 WD |
399 | |
| 400 | /***Mailbox CPU Output Absolute Pointer of Buffer 1***/ | |
| c021880a WD |
401 | #define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038)) |
| 402 | #define INCA_IP_MBC_MBC_OABS1_OABS | |
| 8bde7f77 WD |
403 | |
| 404 | /***Mailbox CPU Output Absolute Pointer of Buffer 2***/ | |
| c021880a WD |
405 | #define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058)) |
| 406 | #define INCA_IP_MBC_MBC_OABS2_OABS | |
| 8bde7f77 WD |
407 | |
| 408 | /***Mailbox CPU Output Absolute Pointer of Buffer 3***/ | |
| c021880a WD |
409 | #define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078)) |
| 410 | #define INCA_IP_MBC_MBC_OABS3_OABS | |
| 8bde7f77 WD |
411 | |
| 412 | /***Mailbox CPU Output Temporary Pointer of Buffer 0***/ | |
| c021880a WD |
413 | #define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C)) |
| 414 | #define INCA_IP_MBC_MBC_OTMP0_OTMP | |
| 8bde7f77 WD |
415 | |
| 416 | /***Mailbox CPU Output Temporary Pointer of Buffer 1***/ | |
| c021880a WD |
417 | #define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C)) |
| 418 | #define INCA_IP_MBC_MBC_OTMP1_OTMP | |
| 8bde7f77 WD |
419 | |
| 420 | /***Mailbox CPU Output Temporary Pointer of Buffer 2***/ | |
| c021880a WD |
421 | #define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C)) |
| 422 | #define INCA_IP_MBC_MBC_OTMP2_OTMP | |
| 8bde7f77 WD |
423 | |
| 424 | /***Mailbox CPU Output Temporary Pointer of Buffer 3***/ | |
| c021880a WD |
425 | #define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C)) |
| 426 | #define INCA_IP_MBC_MBC_OTMP3_OTMP | |
| 8bde7f77 WD |
427 | |
| 428 | /***DSP Control Register***/ | |
| c021880a WD |
429 | #define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0)) |
| 430 | #define INCA_IP_MBC_DCTRL_BA (1 << 0) | |
| 431 | #define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) | |
| 432 | #define INCA_IP_MBC_DCTRL_IDL (1 << 4) | |
| 433 | #define INCA_IP_MBC_DCTRL_RES (1 << 15) | |
| 8bde7f77 WD |
434 | |
| 435 | /***DSP Status Register***/ | |
| c021880a WD |
436 | #define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4)) |
| 437 | #define INCA_IP_MBC_DSTA_IDLE (1 << 0) | |
| 438 | #define INCA_IP_MBC_DSTA_PD (1 << 1) | |
| 8bde7f77 WD |
439 | |
| 440 | /***DSP Test 1 Register***/ | |
| c021880a WD |
441 | #define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8)) |
| 442 | #define INCA_IP_MBC_DTST1_ABORT (1 << 0) | |
| 443 | #define INCA_IP_MBC_DTST1_HWF32 (1 << 1) | |
| 444 | #define INCA_IP_MBC_DTST1_HWF4M (1 << 2) | |
| 8bde7f77 WD |
445 | #define INCA_IP_MBC_DTST1_HWFOP (1 << 3) |
| 446 | ||
| c021880a WD |
447 | /***********************************************************************/ |
| 448 | /* Module : Switch register address and bits */ | |
| 449 | /***********************************************************************/ | |
| 8bde7f77 | 450 | |
| c021880a | 451 | #define INCA_IP_Switch (0xBF104000) |
| 8bde7f77 WD |
452 | /***********************************************************************/ |
| 453 | ||
| c021880a | 454 | |
| 8bde7f77 | 455 | /***Unknown Destination Register***/ |
| c021880a WD |
456 | #define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000)) |
| 457 | #define INCA_IP_Switch_UN_DEST_CB (1 << 8) | |
| 458 | #define INCA_IP_Switch_UN_DEST_LB (1 << 7) | |
| 459 | #define INCA_IP_Switch_UN_DEST_PB (1 << 6) | |
| 460 | #define INCA_IP_Switch_UN_DEST_CM (1 << 5) | |
| 461 | #define INCA_IP_Switch_UN_DEST_LM (1 << 4) | |
| 462 | #define INCA_IP_Switch_UN_DEST_PM (1 << 3) | |
| 463 | #define INCA_IP_Switch_UN_DEST_CU (1 << 2) | |
| 464 | #define INCA_IP_Switch_UN_DEST_LU (1 << 1) | |
| 465 | #define INCA_IP_Switch_UN_DEST_PU (1 << 0) | |
| 8bde7f77 WD |
466 | |
| 467 | /***VLAN Control Register***/ | |
| c021880a WD |
468 | #define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004)) |
| 469 | #define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6) | |
| 470 | #define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5) | |
| 471 | #define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4) | |
| 472 | #define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3) | |
| 473 | #define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2) | |
| 474 | #define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1) | |
| 475 | #define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0) | |
| 8bde7f77 WD |
476 | |
| 477 | /***PC VLAN Configuration Register***/ | |
| c021880a WD |
478 | #define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008)) |
| 479 | #define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) | |
| 480 | #define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
481 | |
| 482 | /***LAN VLAN Configuration Register***/ | |
| c021880a WD |
483 | #define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C)) |
| 484 | #define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) | |
| 485 | #define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
486 | |
| 487 | /***CPU VLAN Configuration Register***/ | |
| c021880a WD |
488 | #define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010)) |
| 489 | #define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) | |
| 490 | #define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
491 | |
| 492 | /***Priority CoS Mapping Register***/ | |
| c021880a WD |
493 | #define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014)) |
| 494 | #define INCA_IP_Switch_PRI_CoS_P7 (1 << 7) | |
| 495 | #define INCA_IP_Switch_PRI_CoS_P6 (1 << 6) | |
| 496 | #define INCA_IP_Switch_PRI_CoS_P5 (1 << 5) | |
| 497 | #define INCA_IP_Switch_PRI_CoS_P4 (1 << 4) | |
| 498 | #define INCA_IP_Switch_PRI_CoS_P3 (1 << 3) | |
| 499 | #define INCA_IP_Switch_PRI_CoS_P2 (1 << 2) | |
| 500 | #define INCA_IP_Switch_PRI_CoS_P1 (1 << 1) | |
| 501 | #define INCA_IP_Switch_PRI_CoS_P0 (1 << 0) | |
| 8bde7f77 WD |
502 | |
| 503 | /***Spanning Tree Port Status Register***/ | |
| c021880a WD |
504 | #define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018)) |
| 505 | #define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 506 | #define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 507 | #define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
508 | |
| 509 | /***ARL Control Register***/ | |
| c021880a WD |
510 | #define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C)) |
| 511 | #define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15) | |
| 512 | #define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14) | |
| 513 | #define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13) | |
| 514 | #define INCA_IP_Switch_ARL_CTL_CC (1 << 12) | |
| 515 | #define INCA_IP_Switch_ARL_CTL_CL (1 << 11) | |
| 516 | #define INCA_IP_Switch_ARL_CTL_CP (1 << 10) | |
| 517 | #define INCA_IP_Switch_ARL_CTL_CG (1 << 9) | |
| 518 | #define INCA_IP_Switch_ARL_CTL_PS (1 << 8) | |
| 519 | #define INCA_IP_Switch_ARL_CTL_MRO (1 << 7) | |
| 520 | #define INCA_IP_Switch_ARL_CTL_SRC (1 << 6) | |
| 521 | #define INCA_IP_Switch_ARL_CTL_ATS (1 << 5) | |
| 522 | #define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2) | |
| 523 | #define INCA_IP_Switch_ARL_CTL_MAF (1 << 1) | |
| 524 | #define INCA_IP_Switch_ARL_CTL_ENL (1 << 0) | |
| 525 | #define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13) | |
| 8bde7f77 WD |
526 | |
| 527 | /***CPU Access Control Register***/ | |
| c021880a WD |
528 | #define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020)) |
| 529 | #define INCA_IP_Switch_CPU_ACTL_RA (1 << 31) | |
| 530 | #define INCA_IP_Switch_CPU_ACTL_RW (1 << 30) | |
| 531 | #define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9) | |
| 532 | #define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8) | |
| 533 | #define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
534 | |
| 535 | /***CPU Access Data Register 1***/ | |
| c021880a WD |
536 | #define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024)) |
| 537 | #define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
538 | |
| 539 | /***CPU Access Data Register 2***/ | |
| c021880a WD |
540 | #define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028)) |
| 541 | #define INCA_IP_Switch_DATA2_Data | |
| 8bde7f77 WD |
542 | |
| 543 | /***CPU Port Control Register***/ | |
| c021880a WD |
544 | #define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C)) |
| 545 | #define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11) | |
| 546 | #define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10) | |
| 547 | #define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7) | |
| 548 | #define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6) | |
| 549 | #define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 550 | #define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2) | |
| 551 | #define INCA_IP_Switch_CPU_PCTL_EML (1 << 1) | |
| 552 | #define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0) | |
| 553 | #define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14) | |
| 8bde7f77 WD |
554 | |
| 555 | /***DSCP CoS Mapping Register 1***/ | |
| c021880a WD |
556 | #define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030)) |
| 557 | #define INCA_IP_Switch_DSCP_COS1_DSCP | |
| 8bde7f77 WD |
558 | |
| 559 | /***DSCP CoS Mapping Register 1***/ | |
| c021880a WD |
560 | #define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034)) |
| 561 | #define INCA_IP_Switch_DSCP_COS2_DSCP | |
| 8bde7f77 WD |
562 | |
| 563 | /***PC WFQ Control Register***/ | |
| c021880a WD |
564 | #define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080)) |
| 565 | #define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9) | |
| 566 | #define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8) | |
| 567 | #define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) | |
| 568 | #define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) | |
| 569 | #define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
570 | |
| 571 | /***PC TX Control Register***/ | |
| c021880a WD |
572 | #define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084)) |
| 573 | #define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1) | |
| 574 | #define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0) | |
| 8bde7f77 WD |
575 | |
| 576 | /***LAN WFQ Control Register***/ | |
| c021880a WD |
577 | #define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100)) |
| 578 | #define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9) | |
| 579 | #define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8) | |
| 580 | #define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) | |
| 581 | #define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) | |
| 582 | #define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
583 | |
| 584 | /***LAN TX Control Register***/ | |
| c021880a WD |
585 | #define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104)) |
| 586 | #define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1) | |
| 587 | #define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0) | |
| 8bde7f77 WD |
588 | |
| 589 | /***CPU WFQ Control Register***/ | |
| c021880a WD |
590 | #define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180)) |
| 591 | #define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9) | |
| 592 | #define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8) | |
| 593 | #define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) | |
| 594 | #define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) | |
| 595 | #define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
596 | |
| 597 | /***PM PC RX Watermark Register***/ | |
| c021880a WD |
598 | #define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200)) |
| 599 | #define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) | |
| 600 | #define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) | |
| 601 | #define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 602 | #define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
603 | |
| 604 | /***PM LAN RX Watermark Register***/ | |
| c021880a WD |
605 | #define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204)) |
| 606 | #define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) | |
| 607 | #define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) | |
| 608 | #define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 609 | #define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
610 | |
| 611 | /***PM CPU RX Watermark Register***/ | |
| c021880a WD |
612 | #define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208)) |
| 613 | #define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) | |
| 614 | #define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) | |
| 615 | #define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 616 | #define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
617 | |
| 618 | /***PM CPU RX Watermark Register***/ | |
| c021880a WD |
619 | #define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C)) |
| 620 | #define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) | |
| 621 | #define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) | |
| 622 | #define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 623 | #define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
624 | |
| 625 | /***PM Control Register***/ | |
| c021880a WD |
626 | #define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210)) |
| 627 | #define INCA_IP_Switch_PM_CTL_GDN (1 << 3) | |
| 628 | #define INCA_IP_Switch_PM_CTL_CDN (1 << 2) | |
| 629 | #define INCA_IP_Switch_PM_CTL_LDN (1 << 1) | |
| 630 | #define INCA_IP_Switch_PM_CTL_PDN (1 << 0) | |
| 8bde7f77 WD |
631 | |
| 632 | /***PM Header Control Register***/ | |
| c021880a WD |
633 | #define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280)) |
| 634 | #define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21) | |
| 635 | #define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20) | |
| 636 | #define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19) | |
| 637 | #define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18) | |
| 638 | #define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2) | |
| 639 | #define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1) | |
| 640 | #define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0) | |
| 8bde7f77 WD |
641 | |
| 642 | /***PM Source Address Register 1***/ | |
| c021880a WD |
643 | #define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284)) |
| 644 | #define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
645 | |
| 646 | /***PM Source Address Register 2***/ | |
| c021880a WD |
647 | #define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288)) |
| 648 | #define INCA_IP_Switch_PMAC_SA2_SA_31_0 | |
| 8bde7f77 WD |
649 | |
| 650 | /***PM Dest Address Register 1***/ | |
| c021880a WD |
651 | #define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C)) |
| 652 | #define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
653 | |
| 654 | /***PM Dest Address Register 2***/ | |
| c021880a WD |
655 | #define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290)) |
| 656 | #define INCA_IP_Switch_PMAC_DA2_DA_31_0 | |
| 8bde7f77 WD |
657 | |
| 658 | /***PM VLAN Register***/ | |
| c021880a WD |
659 | #define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294)) |
| 660 | #define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13) | |
| 661 | #define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12) | |
| 662 | #define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
663 | |
| 664 | /***PM TX IPG Counter Register***/ | |
| c021880a WD |
665 | #define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298)) |
| 666 | #define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
667 | |
| 668 | /***PM RX IPG Counter Register***/ | |
| c021880a WD |
669 | #define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C)) |
| 670 | #define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
671 | |
| 672 | /***Mirror Register***/ | |
| c021880a WD |
673 | #define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300)) |
| 674 | #define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6) | |
| 675 | #define INCA_IP_Switch_MRR_EC (1 << 5) | |
| 676 | #define INCA_IP_Switch_MRR_EL (1 << 4) | |
| 677 | #define INCA_IP_Switch_MRR_EP (1 << 3) | |
| 678 | #define INCA_IP_Switch_MRR_IC (1 << 2) | |
| 679 | #define INCA_IP_Switch_MRR_IL (1 << 1) | |
| 680 | #define INCA_IP_Switch_MRR_IP (1 << 0) | |
| 8bde7f77 WD |
681 | |
| 682 | /***Packet Length Register***/ | |
| c021880a WD |
683 | #define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304)) |
| 684 | #define INCA_IP_Switch_PKT_LEN_ADD (1 << 11) | |
| 685 | #define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
686 | |
| 687 | /***MDIO Access Register***/ | |
| c021880a WD |
688 | #define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480)) |
| 689 | #define INCA_IP_Switch_MDIO_ACC_RA (1 << 31) | |
| 690 | #define INCA_IP_Switch_MDIO_ACC_RW (1 << 30) | |
| 691 | #define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21) | |
| 692 | #define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16) | |
| 693 | #define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
694 | |
| 695 | /***Ethernet PHY Register***/ | |
| c021880a WD |
696 | #define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484)) |
| 697 | #define INCA_IP_Switch_EPHY_SL (1 << 7) | |
| 698 | #define INCA_IP_Switch_EPHY_SP (1 << 6) | |
| 699 | #define INCA_IP_Switch_EPHY_LL (1 << 5) | |
| 700 | #define INCA_IP_Switch_EPHY_LP (1 << 4) | |
| 701 | #define INCA_IP_Switch_EPHY_DL (1 << 3) | |
| 702 | #define INCA_IP_Switch_EPHY_DP (1 << 2) | |
| 703 | #define INCA_IP_Switch_EPHY_PL (1 << 1) | |
| 704 | #define INCA_IP_Switch_EPHY_PP (1 << 0) | |
| 8bde7f77 WD |
705 | |
| 706 | /***Pause Write Enable Register***/ | |
| c021880a WD |
707 | #define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488)) |
| 708 | #define INCA_IP_Switch_PWR_EN_PL (1 << 1) | |
| 709 | #define INCA_IP_Switch_PWR_EN_PP (1 << 0) | |
| 8bde7f77 WD |
710 | |
| 711 | /***MDIO Configuration Register***/ | |
| c021880a WD |
712 | #define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C)) |
| 713 | #define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14) | |
| 714 | #define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9) | |
| 715 | #define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4) | |
| 716 | #define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3) | |
| 717 | #define INCA_IP_Switch_MDIO_CFG_PS (1 << 2) | |
| 718 | #define INCA_IP_Switch_MDIO_CFG_PT (1 << 1) | |
| 719 | #define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0) | |
| 8bde7f77 WD |
720 | |
| 721 | /***Clock Configuration Register***/ | |
| c021880a WD |
722 | #define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500)) |
| 723 | #define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9) | |
| 724 | #define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8) | |
| 725 | #define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7) | |
| 726 | #define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6) | |
| 8bde7f77 WD |
727 | #define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) |
| 728 | ||
| c021880a WD |
729 | /***********************************************************************/ |
| 730 | /* Module : SSC1 register address and bits */ | |
| 731 | /***********************************************************************/ | |
| 8bde7f77 | 732 | |
| c021880a | 733 | #define INCA_IP_SSC1 (0xB8000500) |
| 8bde7f77 | 734 | /***********************************************************************/ |
| c021880a | 735 | |
| 8bde7f77 WD |
736 | |
| 737 | /***Control Register (Programming Mode)***/ | |
| c021880a WD |
738 | #define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) |
| 739 | #define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15) | |
| 740 | #define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14) | |
| 741 | #define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12) | |
| 742 | #define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11) | |
| 743 | #define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10) | |
| 744 | #define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9) | |
| 745 | #define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8) | |
| 746 | #define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7) | |
| 747 | #define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6) | |
| 748 | #define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5) | |
| 749 | #define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4) | |
| 750 | #define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
751 | |
| 752 | /***SCC Control Register (Operating Mode)***/ | |
| c021880a WD |
753 | #define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) |
| 754 | #define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15) | |
| 755 | #define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14) | |
| 756 | #define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12) | |
| 757 | #define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11) | |
| 758 | #define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10) | |
| 759 | #define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9) | |
| 760 | #define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8) | |
| 761 | #define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
762 | |
| 763 | /***SSC Write Hardware Modified Control Register***/ | |
| c021880a WD |
764 | #define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040)) |
| 765 | #define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15) | |
| 766 | #define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14) | |
| 767 | #define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13) | |
| 768 | #define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12) | |
| 769 | #define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11) | |
| 770 | #define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10) | |
| 771 | #define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9) | |
| 772 | #define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8) | |
| 8bde7f77 WD |
773 | |
| 774 | /***SSC Baudrate Timer Reload Register***/ | |
| c021880a WD |
775 | #define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014)) |
| 776 | #define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
777 | |
| 778 | /***SSC Transmitter Buffer Register***/ | |
| c021880a WD |
779 | #define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020)) |
| 780 | #define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
781 | |
| 782 | /***SSC Receiver Buffer Register***/ | |
| c021880a WD |
783 | #define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024)) |
| 784 | #define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
785 | |
| 786 | /***SSC Receive FIFO Control Register***/ | |
| c021880a WD |
787 | #define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030)) |
| 788 | #define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 789 | #define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2) | |
| 790 | #define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1) | |
| 791 | #define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0) | |
| 8bde7f77 WD |
792 | |
| 793 | /***SSC Transmit FIFO Control Register***/ | |
| c021880a WD |
794 | #define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034)) |
| 795 | #define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 796 | #define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2) | |
| 797 | #define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1) | |
| 798 | #define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0) | |
| 8bde7f77 WD |
799 | |
| 800 | /***SSC FIFO Status Register***/ | |
| c021880a WD |
801 | #define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038)) |
| 802 | #define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 803 | #define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
804 | |
| 805 | /***SSC Clock Control Register***/ | |
| c021880a WD |
806 | #define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000)) |
| 807 | #define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 808 | #define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1) | |
| 8bde7f77 WD |
809 | #define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) |
| 810 | ||
| c021880a WD |
811 | /***********************************************************************/ |
| 812 | /* Module : SSC2 register address and bits */ | |
| 813 | /***********************************************************************/ | |
| 8bde7f77 | 814 | |
| c021880a | 815 | #define INCA_IP_SSC2 (0xB8000600) |
| 8bde7f77 | 816 | /***********************************************************************/ |
| c021880a | 817 | |
| 8bde7f77 WD |
818 | |
| 819 | /***Control Register (Programming Mode)***/ | |
| c021880a WD |
820 | #define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) |
| 821 | #define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15) | |
| 822 | #define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14) | |
| 823 | #define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12) | |
| 824 | #define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11) | |
| 825 | #define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10) | |
| 826 | #define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9) | |
| 827 | #define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8) | |
| 828 | #define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7) | |
| 829 | #define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6) | |
| 830 | #define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5) | |
| 831 | #define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4) | |
| 832 | #define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
833 | |
| 834 | /***SCC Control Register (Operating Mode)***/ | |
| c021880a WD |
835 | #define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) |
| 836 | #define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15) | |
| 837 | #define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14) | |
| 838 | #define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12) | |
| 839 | #define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11) | |
| 840 | #define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10) | |
| 841 | #define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9) | |
| 842 | #define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8) | |
| 843 | #define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
844 | |
| 845 | /***SSC Write Hardware Modified Control Register***/ | |
| c021880a WD |
846 | #define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040)) |
| 847 | #define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15) | |
| 848 | #define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14) | |
| 849 | #define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13) | |
| 850 | #define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12) | |
| 851 | #define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11) | |
| 852 | #define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10) | |
| 853 | #define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9) | |
| 854 | #define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8) | |
| 8bde7f77 WD |
855 | |
| 856 | /***SSC Baudrate Timer Reload Register***/ | |
| c021880a WD |
857 | #define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014)) |
| 858 | #define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
859 | |
| 860 | /***SSC Transmitter Buffer Register***/ | |
| c021880a WD |
861 | #define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020)) |
| 862 | #define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
863 | |
| 864 | /***SSC Receiver Buffer Register***/ | |
| c021880a WD |
865 | #define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024)) |
| 866 | #define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
867 | |
| 868 | /***SSC Receive FIFO Control Register***/ | |
| c021880a WD |
869 | #define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030)) |
| 870 | #define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 871 | #define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2) | |
| 872 | #define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1) | |
| 873 | #define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0) | |
| 8bde7f77 WD |
874 | |
| 875 | /***SSC Transmit FIFO Control Register***/ | |
| c021880a WD |
876 | #define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034)) |
| 877 | #define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 878 | #define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2) | |
| 879 | #define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1) | |
| 880 | #define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0) | |
| 8bde7f77 WD |
881 | |
| 882 | /***SSC FIFO Status Register***/ | |
| c021880a WD |
883 | #define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038)) |
| 884 | #define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 885 | #define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
886 | |
| 887 | /***SSC Clock Control Register***/ | |
| c021880a WD |
888 | #define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000)) |
| 889 | #define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 890 | #define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1) | |
| 8bde7f77 WD |
891 | #define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) |
| 892 | ||
| c021880a WD |
893 | /***********************************************************************/ |
| 894 | /* Module : EBU register address and bits */ | |
| 895 | /***********************************************************************/ | |
| 8bde7f77 | 896 | |
| 3e38691e | 897 | #if defined(CONFIG_INCA_IP) |
| c021880a | 898 | #define INCA_IP_EBU (0xB8000200) |
| 3e38691e WD |
899 | #elif defined(CONFIG_PURPLE) |
| 900 | #define INCA_IP_EBU (0xB800D800) | |
| 901 | #endif | |
| 902 | ||
| 8bde7f77 WD |
903 | /***********************************************************************/ |
| 904 | ||
| c021880a | 905 | |
| 8bde7f77 | 906 | /***EBU Clock Control Register***/ |
| c021880a WD |
907 | #define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000)) |
| 908 | #define INCA_IP_EBU_EBU_CLC_DISS (1 << 1) | |
| 909 | #define INCA_IP_EBU_EBU_CLC_DISR (1 << 0) | |
| 8bde7f77 WD |
910 | |
| 911 | /***EBU Global Control Register***/ | |
| c021880a WD |
912 | #define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010)) |
| 913 | #define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) | |
| 914 | #define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) | |
| 915 | #define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 916 | #define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) | |
| 917 | #define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5) | |
| 918 | #define INCA_IP_EBU_EBU_CON_1 (1 << 3) | |
| 8bde7f77 WD |
919 | |
| 920 | /***EBU Address Select Register 0***/ | |
| c021880a WD |
921 | #define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020)) |
| 922 | #define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) | |
| 923 | #define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 924 | #define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1) | |
| 925 | #define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0) | |
| 8bde7f77 WD |
926 | |
| 927 | /***EBU Address Select Register 1***/ | |
| c021880a WD |
928 | #define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024)) |
| 929 | #define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) | |
| 930 | #define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 931 | #define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1) | |
| 932 | #define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0) | |
| 8bde7f77 WD |
933 | |
| 934 | /***EBU Address Select Register 2***/ | |
| c021880a WD |
935 | #define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028)) |
| 936 | #define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) | |
| 937 | #define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 938 | #define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1) | |
| 939 | #define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0) | |
| 8bde7f77 WD |
940 | |
| 941 | /***EBU Bus Configuration Register 0***/ | |
| c021880a WD |
942 | #define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060)) |
| 943 | #define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31) | |
| 944 | #define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) | |
| 945 | #define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) | |
| 946 | #define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) | |
| 947 | #define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) | |
| 948 | #define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) | |
| 949 | #define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19) | |
| 950 | #define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18) | |
| 951 | #define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) | |
| 952 | #define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) | |
| 953 | #define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) | |
| 954 | #define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 955 | #define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 956 | #define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
957 | |
| 958 | /***EBU Bus Configuration Register 1***/ | |
| c021880a WD |
959 | #define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064)) |
| 960 | #define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31) | |
| 961 | #define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) | |
| 962 | #define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) | |
| 963 | #define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) | |
| 964 | #define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) | |
| 965 | #define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) | |
| 966 | #define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19) | |
| 967 | #define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18) | |
| 968 | #define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) | |
| 969 | #define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) | |
| 970 | #define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) | |
| 971 | #define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 972 | #define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 973 | #define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
974 | |
| 975 | /***EBU Bus Configuration Register 2***/ | |
| c021880a WD |
976 | #define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068)) |
| 977 | #define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31) | |
| 978 | #define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) | |
| 979 | #define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) | |
| 980 | #define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) | |
| 981 | #define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) | |
| 982 | #define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) | |
| 983 | #define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19) | |
| 984 | #define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18) | |
| 985 | #define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) | |
| 986 | #define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) | |
| 987 | #define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) | |
| 988 | #define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 989 | #define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 8bde7f77 WD |
990 | #define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) |
| 991 | ||
| c021880a WD |
992 | /***********************************************************************/ |
| 993 | /* Module : SDRAM register address and bits */ | |
| 994 | /***********************************************************************/ | |
| 8bde7f77 | 995 | |
| c021880a | 996 | #define INCA_IP_SDRAM (0xBF800000) |
| 8bde7f77 WD |
997 | /***********************************************************************/ |
| 998 | ||
| c021880a | 999 | |
| 8bde7f77 | 1000 | /***MC Access Error Cause Register***/ |
| c021880a WD |
1001 | #define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100)) |
| 1002 | #define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31) | |
| 1003 | #define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) | |
| 1004 | #define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 1005 | #define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) | |
| 8bde7f77 WD |
1006 | |
| 1007 | /***MC Access Error Address Register***/ | |
| c021880a WD |
1008 | #define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108)) |
| 1009 | #define INCA_IP_SDRAM_MC_ERRADDR_ADDR | |
| 8bde7f77 WD |
1010 | |
| 1011 | /***MC I/O General Purpose Register***/ | |
| c021880a WD |
1012 | #define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800)) |
| 1013 | #define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) | |
| 1014 | #define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) | |
| 1015 | #define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) | |
| 1016 | #define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) | |
| 1017 | #define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) | |
| 1018 | #define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11) | |
| 1019 | #define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) | |
| 1020 | #define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 1021 | #define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1022 | |
| 1023 | /***MC Self Refresh Register***/ | |
| c021880a WD |
1024 | #define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00)) |
| 1025 | #define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1) | |
| 1026 | #define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0) | |
| 1027 | #define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) | |
| 8bde7f77 WD |
1028 | |
| 1029 | /***MC Enable Register***/ | |
| c021880a WD |
1030 | #define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000)) |
| 1031 | #define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0) | |
| 1032 | #define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) | |
| 8bde7f77 WD |
1033 | |
| 1034 | /***MC Mode Register Setup Code***/ | |
| c021880a WD |
1035 | #define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008)) |
| 1036 | #define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) | |
| 1037 | #define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) | |
| 1038 | #define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3) | |
| 1039 | #define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1040 | |
| 1041 | /***MC Configuration Data-word Width Register***/ | |
| c021880a WD |
1042 | #define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010)) |
| 1043 | #define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 1044 | #define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) | |
| 8bde7f77 WD |
1045 | |
| 1046 | /***MC Configuration Physical Bank 0 Register***/ | |
| c021880a WD |
1047 | #define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018)) |
| 1048 | #define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) | |
| 1049 | #define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) | |
| 1050 | #define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 1051 | #define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 1052 | #define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) | |
| 8bde7f77 WD |
1053 | |
| 1054 | /***MC Latency Register***/ | |
| c021880a WD |
1055 | #define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038)) |
| 1056 | #define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) | |
| 1057 | #define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) | |
| 1058 | #define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) | |
| 1059 | #define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 1060 | #define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 1061 | #define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) | |
| 8bde7f77 WD |
1062 | |
| 1063 | /***MC Refresh Cycle Time Register***/ | |
| c021880a WD |
1064 | #define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040)) |
| 1065 | #define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1066 | #define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) |
| 1067 | ||
| c021880a WD |
1068 | /***********************************************************************/ |
| 1069 | /* Module : GPTU register address and bits */ | |
| 1070 | /***********************************************************************/ | |
| 8bde7f77 | 1071 | |
| c021880a | 1072 | #define INCA_IP_GPTU (0xB8000300) |
| 8bde7f77 WD |
1073 | /***********************************************************************/ |
| 1074 | ||
| c021880a | 1075 | |
| 8bde7f77 | 1076 | /***GPT Clock Control Register***/ |
| c021880a WD |
1077 | #define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000)) |
| 1078 | #define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 1079 | #define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1) | |
| 1080 | #define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0) | |
| 8bde7f77 WD |
1081 | |
| 1082 | /***GPT Timer 3 Control Register***/ | |
| c021880a WD |
1083 | #define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014)) |
| 1084 | #define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15) | |
| 1085 | #define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14) | |
| 1086 | #define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13) | |
| 1087 | #define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) | |
| 1088 | #define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10) | |
| 1089 | #define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7) | |
| 1090 | #define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6) | |
| 1091 | #define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 1092 | #define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1093 | |
| 1094 | /***GPT Write Hardware Modified Timer 3 Control Register | |
| c021880a WD |
1095 | If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ |
| 1096 | #define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C)) | |
| 1097 | #define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) | |
| 1098 | #define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) | |
| 1099 | #define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) | |
| 1100 | #define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) | |
| 1101 | #define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) | |
| 1102 | #define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) | |
| 8bde7f77 WD |
1103 | |
| 1104 | /***GPT Timer 2 Control Register***/ | |
| c021880a WD |
1105 | #define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010)) |
| 1106 | #define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15) | |
| 1107 | #define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14) | |
| 1108 | #define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13) | |
| 1109 | #define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12) | |
| 1110 | #define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9) | |
| 1111 | #define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7) | |
| 1112 | #define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6) | |
| 1113 | #define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 1114 | #define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1115 | |
| 1116 | /***GPT Timer 4 Control Register***/ | |
| c021880a WD |
1117 | #define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018)) |
| 1118 | #define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15) | |
| 1119 | #define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14) | |
| 1120 | #define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13) | |
| 1121 | #define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12) | |
| 1122 | #define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9) | |
| 1123 | #define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7) | |
| 1124 | #define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6) | |
| 1125 | #define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 1126 | #define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 | 1127 | |
| c021880a WD |
1128 | /***GPT Write HW Modified Timer 2 Control Register If set |
| 1129 | and clear bit are written concurrently with 1, the associated bit is not changed.***/ | |
| 1130 | #define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048)) | |
| 1131 | #define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) | |
| 1132 | #define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) | |
| 1133 | #define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) | |
| 1134 | #define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) | |
| 8bde7f77 | 1135 | |
| c021880a WD |
1136 | /***GPT Write HW Modified Timer 4 Control Register If set |
| 1137 | and clear bit are written concurrently with 1, the associated bit is not changed.***/ | |
| 1138 | #define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050)) | |
| 1139 | #define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) | |
| 1140 | #define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) | |
| 1141 | #define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) | |
| 1142 | #define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) | |
| 8bde7f77 WD |
1143 | |
| 1144 | /***GPT Capture Reload Register***/ | |
| c021880a WD |
1145 | #define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030)) |
| 1146 | #define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1147 | |
| 1148 | /***GPT Timer 2 Register***/ | |
| c021880a WD |
1149 | #define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034)) |
| 1150 | #define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1151 | |
| 1152 | /***GPT Timer 3 Register***/ | |
| c021880a WD |
1153 | #define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038)) |
| 1154 | #define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1155 | |
| 1156 | /***GPT Timer 4 Register***/ | |
| c021880a WD |
1157 | #define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C)) |
| 1158 | #define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1159 | |
| 1160 | /***GPT Timer 5 Register***/ | |
| c021880a WD |
1161 | #define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040)) |
| 1162 | #define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1163 | |
| 1164 | /***GPT Timer 6 Register***/ | |
| c021880a WD |
1165 | #define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044)) |
| 1166 | #define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1167 | |
| 1168 | /***GPT Timer 6 Control Register***/ | |
| c021880a WD |
1169 | #define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020)) |
| 1170 | #define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15) | |
| 1171 | #define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14) | |
| 1172 | #define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) | |
| 1173 | #define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10) | |
| 1174 | #define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7) | |
| 1175 | #define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6) | |
| 1176 | #define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 1177 | #define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 | 1178 | |
| c021880a WD |
1179 | /***GPT Write HW Modified Timer 6 Control Register If set |
| 1180 | and clear bit are written concurrently with 1, the associated bit is not changed.***/ | |
| 1181 | #define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054)) | |
| 1182 | #define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) | |
| 1183 | #define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) | |
| 8bde7f77 WD |
1184 | |
| 1185 | /***GPT Timer 5 Control Register***/ | |
| c021880a WD |
1186 | #define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C)) |
| 1187 | #define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15) | |
| 1188 | #define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14) | |
| 1189 | #define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) | |
| 1190 | #define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11) | |
| 1191 | #define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10) | |
| 1192 | #define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9) | |
| 1193 | #define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8) | |
| 1194 | #define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7) | |
| 1195 | #define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6) | |
| 1196 | #define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 8bde7f77 WD |
1197 | #define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) |
| 1198 | ||
| c021880a WD |
1199 | /***********************************************************************/ |
| 1200 | /* Module : IOM register address and bits */ | |
| 1201 | /***********************************************************************/ | |
| 8bde7f77 | 1202 | |
| c021880a | 1203 | #define INCA_IP_IOM (0xBF105000) |
| 8bde7f77 | 1204 | /***********************************************************************/ |
| c021880a | 1205 | |
| 8bde7f77 WD |
1206 | |
| 1207 | /***Receive FIFO***/ | |
| c021880a WD |
1208 | #define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) |
| 1209 | #define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1210 | |
| 1211 | /***Transmit FIFO***/ | |
| c021880a WD |
1212 | #define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) |
| 1213 | #define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1214 | |
| 1215 | /***Interrupt Status Register HDLC***/ | |
| c021880a WD |
1216 | #define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) |
| 1217 | #define INCA_IP_IOM_ISTAH_RME (1 << 7) | |
| 1218 | #define INCA_IP_IOM_ISTAH_RPF (1 << 6) | |
| 1219 | #define INCA_IP_IOM_ISTAH_RFO (1 << 5) | |
| 1220 | #define INCA_IP_IOM_ISTAH_XPR (1 << 4) | |
| 1221 | #define INCA_IP_IOM_ISTAH_XMR (1 << 3) | |
| 1222 | #define INCA_IP_IOM_ISTAH_XDU (1 << 2) | |
| 8bde7f77 WD |
1223 | |
| 1224 | /***Interrupt Mask Register HDLC***/ | |
| c021880a WD |
1225 | #define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) |
| 1226 | #define INCA_IP_IOM_MASKH_RME (1 << 7) | |
| 1227 | #define INCA_IP_IOM_MASKH_RPF (1 << 6) | |
| 1228 | #define INCA_IP_IOM_MASKH_RFO (1 << 5) | |
| 1229 | #define INCA_IP_IOM_MASKH_XPR (1 << 4) | |
| 1230 | #define INCA_IP_IOM_MASKH_XMR (1 << 3) | |
| 1231 | #define INCA_IP_IOM_MASKH_XDU (1 << 2) | |
| 8bde7f77 WD |
1232 | |
| 1233 | /***Status Register***/ | |
| c021880a WD |
1234 | #define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) |
| 1235 | #define INCA_IP_IOM_STAR_XDOV (1 << 7) | |
| 1236 | #define INCA_IP_IOM_STAR_XFW (1 << 6) | |
| 1237 | #define INCA_IP_IOM_STAR_RACI (1 << 3) | |
| 1238 | #define INCA_IP_IOM_STAR_XACI (1 << 1) | |
| 8bde7f77 WD |
1239 | |
| 1240 | /***Command Register***/ | |
| c021880a WD |
1241 | #define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) |
| 1242 | #define INCA_IP_IOM_CMDR_RMC (1 << 7) | |
| 1243 | #define INCA_IP_IOM_CMDR_RRES (1 << 6) | |
| 1244 | #define INCA_IP_IOM_CMDR_XTF (1 << 3) | |
| 1245 | #define INCA_IP_IOM_CMDR_XME (1 << 1) | |
| 1246 | #define INCA_IP_IOM_CMDR_XRES (1 << 0) | |
| 8bde7f77 WD |
1247 | |
| 1248 | /***Mode Register***/ | |
| c021880a WD |
1249 | #define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088)) |
| 1250 | #define INCA_IP_IOM_MODEH_MDS2 (1 << 7) | |
| 1251 | #define INCA_IP_IOM_MODEH_MDS1 (1 << 6) | |
| 1252 | #define INCA_IP_IOM_MODEH_MDS0 (1 << 5) | |
| 1253 | #define INCA_IP_IOM_MODEH_RAC (1 << 3) | |
| 1254 | #define INCA_IP_IOM_MODEH_DIM2 (1 << 2) | |
| 1255 | #define INCA_IP_IOM_MODEH_DIM1 (1 << 1) | |
| 1256 | #define INCA_IP_IOM_MODEH_DIM0 (1 << 0) | |
| 8bde7f77 WD |
1257 | |
| 1258 | /***Extended Mode Register***/ | |
| c021880a WD |
1259 | #define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C)) |
| 1260 | #define INCA_IP_IOM_EXMR_XFBS (1 << 7) | |
| 1261 | #define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) | |
| 1262 | #define INCA_IP_IOM_EXMR_SRA (1 << 4) | |
| 1263 | #define INCA_IP_IOM_EXMR_XCRC (1 << 3) | |
| 1264 | #define INCA_IP_IOM_EXMR_RCRC (1 << 2) | |
| 1265 | #define INCA_IP_IOM_EXMR_ITF (1 << 0) | |
| 8bde7f77 WD |
1266 | |
| 1267 | /***SAPI1 Register***/ | |
| c021880a WD |
1268 | #define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094)) |
| 1269 | #define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) | |
| 1270 | #define INCA_IP_IOM_SAP1_MHA (1 << 0) | |
| 8bde7f77 WD |
1271 | |
| 1272 | /***Receive Frame Byte Count Low***/ | |
| c021880a WD |
1273 | #define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098)) |
| 1274 | #define INCA_IP_IOM_RBCL_RBC(value) (1 << value) | |
| 8bde7f77 WD |
1275 | |
| 1276 | ||
| 1277 | /***SAPI2 Register***/ | |
| c021880a WD |
1278 | #define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098)) |
| 1279 | #define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) | |
| 1280 | #define INCA_IP_IOM_SAP2_MLA (1 << 0) | |
| 8bde7f77 WD |
1281 | |
| 1282 | /***Receive Frame Byte Count High***/ | |
| c021880a WD |
1283 | #define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C)) |
| 1284 | #define INCA_IP_IOM_RBCH_OV (1 << 4) | |
| 1285 | #define INCA_IP_IOM_RBCH_RBC11 (1 << 3) | |
| 1286 | #define INCA_IP_IOM_RBCH_RBC10 (1 << 2) | |
| 1287 | #define INCA_IP_IOM_RBCH_RBC9 (1 << 1) | |
| 1288 | #define INCA_IP_IOM_RBCH_RBC8 (1 << 0) | |
| 8bde7f77 WD |
1289 | |
| 1290 | /***TEI1 Register 1***/ | |
| c021880a WD |
1291 | #define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C)) |
| 1292 | #define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) | |
| 1293 | #define INCA_IP_IOM_TEI1_EA (1 << 0) | |
| 8bde7f77 WD |
1294 | |
| 1295 | /***Receive Status Register***/ | |
| c021880a WD |
1296 | #define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) |
| 1297 | #define INCA_IP_IOM_RSTA_VFR (1 << 7) | |
| 1298 | #define INCA_IP_IOM_RSTA_RDO (1 << 6) | |
| 1299 | #define INCA_IP_IOM_RSTA_CRC (1 << 5) | |
| 1300 | #define INCA_IP_IOM_RSTA_RAB (1 << 4) | |
| 1301 | #define INCA_IP_IOM_RSTA_SA1 (1 << 3) | |
| 1302 | #define INCA_IP_IOM_RSTA_SA0 (1 << 2) | |
| 1303 | #define INCA_IP_IOM_RSTA_TA (1 << 0) | |
| 1304 | #define INCA_IP_IOM_RSTA_CR (1 << 1) | |
| 8bde7f77 WD |
1305 | |
| 1306 | /***TEI2 Register***/ | |
| c021880a WD |
1307 | #define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) |
| 1308 | #define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) | |
| 1309 | #define INCA_IP_IOM_TEI2_EA (1 << 0) | |
| 8bde7f77 WD |
1310 | |
| 1311 | /***Test Mode Register HDLC***/ | |
| c021880a WD |
1312 | #define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4)) |
| 1313 | #define INCA_IP_IOM_TMH_TLP (1 << 0) | |
| 8bde7f77 WD |
1314 | |
| 1315 | /***Command/Indication Receive 0***/ | |
| c021880a WD |
1316 | #define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) |
| 1317 | #define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 1318 | #define INCA_IP_IOM_CIR0_CIC0 (1 << 3) | |
| 1319 | #define INCA_IP_IOM_CIR0_CIC1 (1 << 2) | |
| 1320 | #define INCA_IP_IOM_CIR0_SG (1 << 1) | |
| 1321 | #define INCA_IP_IOM_CIR0_BAS (1 << 0) | |
| 8bde7f77 WD |
1322 | |
| 1323 | /***Command/Indication Transmit 0***/ | |
| c021880a WD |
1324 | #define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) |
| 1325 | #define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) | |
| 1326 | #define INCA_IP_IOM_CIX0_TBA2 (1 << 3) | |
| 1327 | #define INCA_IP_IOM_CIX0_TBA1 (1 << 2) | |
| 1328 | #define INCA_IP_IOM_CIX0_TBA0 (1 << 1) | |
| 1329 | #define INCA_IP_IOM_CIX0_BAC (1 << 0) | |
| 8bde7f77 WD |
1330 | |
| 1331 | /***Command/Indication Receive 1***/ | |
| c021880a WD |
1332 | #define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) |
| 1333 | #define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) | |
| 8bde7f77 WD |
1334 | |
| 1335 | /***Command/Indication Transmit 1***/ | |
| c021880a WD |
1336 | #define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) |
| 1337 | #define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) | |
| 1338 | #define INCA_IP_IOM_CIX1_CICW (1 << 1) | |
| 1339 | #define INCA_IP_IOM_CIX1_CI1E (1 << 0) | |
| 8bde7f77 WD |
1340 | |
| 1341 | /***Controller Data Access Reg. (CH10)***/ | |
| c021880a WD |
1342 | #define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100)) |
| 1343 | #define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1344 | |
| 1345 | /***Controller Data Access Reg. (CH11)***/ | |
| c021880a WD |
1346 | #define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104)) |
| 1347 | #define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1348 | |
| 1349 | /***Controller Data Access Reg. (CH20)***/ | |
| c021880a WD |
1350 | #define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108)) |
| 1351 | #define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1352 | |
| 1353 | /***Controller Data Access Reg. (CH21)***/ | |
| c021880a WD |
1354 | #define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C)) |
| 1355 | #define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1356 | |
| 1357 | /***Time Slot and Data Port Sel. (CH10)***/ | |
| c021880a WD |
1358 | #define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110)) |
| 1359 | #define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7) | |
| 1360 | #define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1361 | |
| 1362 | /***Time Slot and Data Port Sel. (CH11)***/ | |
| c021880a WD |
1363 | #define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114)) |
| 1364 | #define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7) | |
| 1365 | #define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1366 | |
| 1367 | /***Time Slot and Data Port Sel. (CH20)***/ | |
| c021880a WD |
1368 | #define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118)) |
| 1369 | #define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7) | |
| 1370 | #define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1371 | |
| 1372 | /***Time Slot and Data Port Sel. (CH21)***/ | |
| c021880a WD |
1373 | #define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C)) |
| 1374 | #define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7) | |
| 1375 | #define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1376 | |
| 1377 | /***Time Slot and Data Port Sel. (CH10)***/ | |
| c021880a WD |
1378 | #define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120)) |
| 1379 | #define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7) | |
| 1380 | #define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1381 | |
| 1382 | /***Time Slot and Data Port Sel. (CH11)***/ | |
| c021880a WD |
1383 | #define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124)) |
| 1384 | #define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7) | |
| 1385 | #define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1386 | |
| 1387 | /***Time Slot and Data Port Sel. (CH20)***/ | |
| c021880a WD |
1388 | #define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128)) |
| 1389 | #define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7) | |
| 1390 | #define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1391 | |
| 1392 | /***Time Slot and Data Port Sel. (CH21)***/ | |
| c021880a WD |
1393 | #define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C)) |
| 1394 | #define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7) | |
| 1395 | #define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1396 | |
| 1397 | /***Ctrl. Reg. Contr. Data Access CH1x***/ | |
| c021880a WD |
1398 | #define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138)) |
| 1399 | #define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5) | |
| 1400 | #define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4) | |
| 1401 | #define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3) | |
| 1402 | #define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2) | |
| 1403 | #define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1) | |
| 1404 | #define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0) | |
| 8bde7f77 WD |
1405 | |
| 1406 | /***Ctrl. Reg. Contr. Data Access CH1x***/ | |
| c021880a WD |
1407 | #define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C)) |
| 1408 | #define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5) | |
| 1409 | #define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4) | |
| 1410 | #define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3) | |
| 1411 | #define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2) | |
| 1412 | #define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1) | |
| 1413 | #define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0) | |
| 8bde7f77 WD |
1414 | |
| 1415 | /***Control Register B-Channel Data***/ | |
| c021880a WD |
1416 | #define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144)) |
| 1417 | #define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4) | |
| 1418 | #define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3) | |
| 8bde7f77 WD |
1419 | |
| 1420 | /***Control Register B-Channel Data***/ | |
| c021880a WD |
1421 | #define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148)) |
| 1422 | #define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4) | |
| 1423 | #define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3) | |
| 8bde7f77 WD |
1424 | |
| 1425 | /***Control Reg. for HDLC and CI1 Data***/ | |
| c021880a WD |
1426 | #define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) |
| 1427 | #define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7) | |
| 1428 | #define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6) | |
| 1429 | #define INCA_IP_IOM_DCI_CR_EN_D (1 << 5) | |
| 8bde7f77 WD |
1430 | |
| 1431 | /***Control Reg. for HDLC and CI1 Data***/ | |
| c021880a WD |
1432 | #define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) |
| 1433 | #define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7) | |
| 1434 | #define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6) | |
| 1435 | #define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5) | |
| 8bde7f77 WD |
1436 | |
| 1437 | /***Control Reg. Serial Data Strobe x***/ | |
| c021880a WD |
1438 | #define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154)) |
| 1439 | #define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7) | |
| 1440 | #define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6) | |
| 1441 | #define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5) | |
| 1442 | #define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1443 | |
| 1444 | /***Control Register IOM Data***/ | |
| c021880a WD |
1445 | #define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C)) |
| 1446 | #define INCA_IP_IOM_IOM_CR_SPU (1 << 7) | |
| 1447 | #define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5) | |
| 1448 | #define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4) | |
| 1449 | #define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3) | |
| 1450 | #define INCA_IP_IOM_IOM_CR_CLKM (1 << 2) | |
| 1451 | #define INCA_IP_IOM_IOM_CR_Res (1 << 1) | |
| 1452 | #define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0) | |
| 8bde7f77 WD |
1453 | |
| 1454 | /***Synchronous Transfer Interrupt***/ | |
| c021880a WD |
1455 | #define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) |
| 1456 | #define INCA_IP_IOM_STI_STOV21 (1 << 7) | |
| 1457 | #define INCA_IP_IOM_STI_STOV20 (1 << 6) | |
| 1458 | #define INCA_IP_IOM_STI_STOV11 (1 << 5) | |
| 1459 | #define INCA_IP_IOM_STI_STOV10 (1 << 4) | |
| 1460 | #define INCA_IP_IOM_STI_STI21 (1 << 3) | |
| 1461 | #define INCA_IP_IOM_STI_STI20 (1 << 2) | |
| 1462 | #define INCA_IP_IOM_STI_STI11 (1 << 1) | |
| 1463 | #define INCA_IP_IOM_STI_STI10 (1 << 0) | |
| 8bde7f77 WD |
1464 | |
| 1465 | /***Acknowledge Synchronous Transfer Interrupt***/ | |
| c021880a WD |
1466 | #define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) |
| 1467 | #define INCA_IP_IOM_ASTI_ACK21 (1 << 3) | |
| 1468 | #define INCA_IP_IOM_ASTI_ACK20 (1 << 2) | |
| 1469 | #define INCA_IP_IOM_ASTI_ACK11 (1 << 1) | |
| 1470 | #define INCA_IP_IOM_ASTI_ACK10 (1 << 0) | |
| 8bde7f77 WD |
1471 | |
| 1472 | /***Mask Synchronous Transfer Interrupt***/ | |
| c021880a WD |
1473 | #define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164)) |
| 1474 | #define INCA_IP_IOM_MSTI_STOV21 (1 << 7) | |
| 1475 | #define INCA_IP_IOM_MSTI_STOV20 (1 << 6) | |
| 1476 | #define INCA_IP_IOM_MSTI_STOV11 (1 << 5) | |
| 1477 | #define INCA_IP_IOM_MSTI_STOV10 (1 << 4) | |
| 1478 | #define INCA_IP_IOM_MSTI_STI21 (1 << 3) | |
| 1479 | #define INCA_IP_IOM_MSTI_STI20 (1 << 2) | |
| 1480 | #define INCA_IP_IOM_MSTI_STI11 (1 << 1) | |
| 1481 | #define INCA_IP_IOM_MSTI_STI10 (1 << 0) | |
| 8bde7f77 WD |
1482 | |
| 1483 | /***Configuration Register for Serial Data Strobes***/ | |
| c021880a WD |
1484 | #define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168)) |
| 1485 | #define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0) | |
| 8bde7f77 WD |
1486 | |
| 1487 | /***Monitoring CDA Bits***/ | |
| c021880a WD |
1488 | #define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C)) |
| 1489 | #define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) | |
| 1490 | #define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 1491 | #define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 8bde7f77 WD |
1492 | #define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) |
| 1493 | ||
| c021880a WD |
1494 | /***********************************************************************/ |
| 1495 | /* Module : ASC register address and bits */ | |
| 1496 | /***********************************************************************/ | |
| 8bde7f77 | 1497 | |
| 3e38691e | 1498 | #if defined(CONFIG_INCA_IP) |
| c021880a | 1499 | #define INCA_IP_ASC (0xB8000400) |
| 3e38691e WD |
1500 | #elif defined(CONFIG_PURPLE) |
| 1501 | #define INCA_IP_ASC (0xBE500000) | |
| 1502 | #endif | |
| 1503 | ||
| 8bde7f77 WD |
1504 | /***********************************************************************/ |
| 1505 | ||
| c021880a | 1506 | |
| 8bde7f77 | 1507 | /***ASC Port Input Select Register***/ |
| c021880a WD |
1508 | #define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004)) |
| 1509 | #define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0) | |
| 8bde7f77 WD |
1510 | |
| 1511 | /***ASC Control Register***/ | |
| c021880a WD |
1512 | #define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010)) |
| 1513 | #define INCA_IP_ASC_ASC_CON_R (1 << 15) | |
| 1514 | #define INCA_IP_ASC_ASC_CON_LB (1 << 14) | |
| 1515 | #define INCA_IP_ASC_ASC_CON_BRS (1 << 13) | |
| 1516 | #define INCA_IP_ASC_ASC_CON_ODD (1 << 12) | |
| 1517 | #define INCA_IP_ASC_ASC_CON_FDE (1 << 11) | |
| 1518 | #define INCA_IP_ASC_ASC_CON_OE (1 << 10) | |
| 1519 | #define INCA_IP_ASC_ASC_CON_FE (1 << 9) | |
| 1520 | #define INCA_IP_ASC_ASC_CON_PE (1 << 8) | |
| 1521 | #define INCA_IP_ASC_ASC_CON_OEN (1 << 7) | |
| 1522 | #define INCA_IP_ASC_ASC_CON_FEN (1 << 6) | |
| 1523 | #define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5) | |
| 1524 | #define INCA_IP_ASC_ASC_CON_REN (1 << 4) | |
| 1525 | #define INCA_IP_ASC_ASC_CON_STP (1 << 3) | |
| 1526 | #define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1527 | |
| 1528 | /***ASC Write Hardware Modified Control Register***/ | |
| c021880a WD |
1529 | #define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050)) |
| 1530 | #define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13) | |
| 1531 | #define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12) | |
| 1532 | #define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11) | |
| 1533 | #define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10) | |
| 1534 | #define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9) | |
| 1535 | #define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8) | |
| 1536 | #define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5) | |
| 1537 | #define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4) | |
| 8bde7f77 WD |
1538 | |
| 1539 | /***ASC Baudrate Timer/Reload Register***/ | |
| c021880a WD |
1540 | #define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014)) |
| 1541 | #define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1542 | |
| 1543 | /***ASC Fractional Divider Register***/ | |
| c021880a WD |
1544 | #define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018)) |
| 1545 | #define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1546 | |
| 1547 | /***ASC IrDA Pulse Mode/Width Register***/ | |
| c021880a WD |
1548 | #define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C)) |
| 1549 | #define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8) | |
| 1550 | #define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1551 | |
| 1552 | /***ASC Transmit Buffer Register***/ | |
| c021880a WD |
1553 | #define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020)) |
| 1554 | #define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1555 | |
| 1556 | /***ASC Receive Buffer Register***/ | |
| c021880a WD |
1557 | #define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024)) |
| 1558 | #define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1559 | |
| 1560 | /***ASC Autobaud Control Register***/ | |
| c021880a WD |
1561 | #define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030)) |
| 1562 | #define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11) | |
| 1563 | #define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10) | |
| 1564 | #define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8) | |
| 1565 | #define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4) | |
| 1566 | #define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3) | |
| 1567 | #define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2) | |
| 1568 | #define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1) | |
| 1569 | #define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0) | |
| 8bde7f77 WD |
1570 | |
| 1571 | /***Receive FIFO Control Register***/ | |
| c021880a WD |
1572 | #define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040)) |
| 1573 | #define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 1574 | #define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2) | |
| 1575 | #define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1) | |
| 1576 | #define INCA_IP_ASC_RXFCON_RXFEN (1 << 0) | |
| 8bde7f77 WD |
1577 | |
| 1578 | /***Transmit FIFO Control Register***/ | |
| c021880a WD |
1579 | #define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044)) |
| 1580 | #define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 1581 | #define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2) | |
| 1582 | #define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1) | |
| 1583 | #define INCA_IP_ASC_TXFCON_TXFEN (1 << 0) | |
| 8bde7f77 WD |
1584 | |
| 1585 | /***FIFO Status Register***/ | |
| c021880a WD |
1586 | #define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048)) |
| 1587 | #define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) | |
| 1588 | #define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1589 | |
| 1590 | /***ASC Write HW Modified Autobaud Control Register***/ | |
| c021880a WD |
1591 | #define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054)) |
| 1592 | #define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1) | |
| 1593 | #define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0) | |
| 8bde7f77 WD |
1594 | |
| 1595 | /***ASC Autobaud Status Register***/ | |
| c021880a WD |
1596 | #define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034)) |
| 1597 | #define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4) | |
| 1598 | #define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3) | |
| 1599 | #define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2) | |
| 1600 | #define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1) | |
| 1601 | #define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0) | |
| 8bde7f77 WD |
1602 | |
| 1603 | /***ASC Write HW Modified Autobaud Status Register***/ | |
| c021880a WD |
1604 | #define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058)) |
| 1605 | #define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9) | |
| 1606 | #define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) | |
| 1607 | #define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7) | |
| 1608 | #define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6) | |
| 1609 | #define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5) | |
| 1610 | #define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4) | |
| 1611 | #define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3) | |
| 1612 | #define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2) | |
| 1613 | #define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1) | |
| 1614 | #define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0) | |
| 8bde7f77 WD |
1615 | |
| 1616 | /***ASC Clock Control Register***/ | |
| c021880a WD |
1617 | #define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000)) |
| 1618 | #define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) | |
| 1619 | #define INCA_IP_ASC_ASC_CLC_DISS (1 << 1) | |
| 8bde7f77 WD |
1620 | #define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) |
| 1621 | ||
| c021880a WD |
1622 | /***********************************************************************/ |
| 1623 | /* Module : DMA register address and bits */ | |
| 1624 | /***********************************************************************/ | |
| 8bde7f77 | 1625 | |
| c021880a | 1626 | #define INCA_IP_DMA (0xBF108000) |
| 8bde7f77 | 1627 | /***********************************************************************/ |
| c021880a | 1628 | |
| 8bde7f77 WD |
1629 | |
| 1630 | /***DMA RX Channel 0 Command Register***/ | |
| c021880a WD |
1631 | #define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800)) |
| 1632 | #define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31) | |
| 1633 | #define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30) | |
| 1634 | #define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2) | |
| 1635 | #define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1) | |
| 1636 | #define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0) | |
| 8bde7f77 WD |
1637 | |
| 1638 | /***DMA RX Channel 1 Command Register***/ | |
| c021880a WD |
1639 | #define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804)) |
| 1640 | #define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31) | |
| 1641 | #define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30) | |
| 1642 | #define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2) | |
| 1643 | #define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1) | |
| 1644 | #define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0) | |
| 8bde7f77 WD |
1645 | |
| 1646 | /***DMA Receive Interrupt Status Register***/ | |
| c021880a WD |
1647 | #define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808)) |
| 1648 | #define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) | |
| 1649 | #define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) | |
| 1650 | #define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 1651 | #define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 1652 | #define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1653 | |
| 1654 | /***DMA Receive Interrupt Mask Register***/ | |
| c021880a WD |
1655 | #define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C)) |
| 1656 | #define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) | |
| 1657 | #define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) | |
| 1658 | #define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 1659 | #define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 1660 | #define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 | 1661 | |
| c021880a WD |
1662 | /***DMA First Receive Descriptor Addr. for Rx Channel 0 |
| 1663 | ***/ | |
| 1664 | #define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810)) | |
| 1665 | #define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) | |
| 8bde7f77 | 1666 | |
| c021880a WD |
1667 | /***DMA First Receive Descriptor Addr. for Rx Channel 1 |
| 1668 | ***/ | |
| 1669 | #define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814)) | |
| 1670 | #define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1671 | |
| 1672 | /***DMA Receive Channel Polling Time***/ | |
| c021880a WD |
1673 | #define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818)) |
| 1674 | #define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30) | |
| 1675 | #define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28) | |
| 1676 | #define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1677 | |
| 1678 | /***DMA TX Channel 0 Command Register (Voice Port)***/ | |
| c021880a WD |
1679 | #define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880)) |
| 1680 | #define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31) | |
| 1681 | #define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30) | |
| 1682 | #define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2) | |
| 1683 | #define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1) | |
| 1684 | #define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0) | |
| 8bde7f77 WD |
1685 | |
| 1686 | /***DMA TX Channel 1 Command Register (Mangmt Port)***/ | |
| c021880a WD |
1687 | #define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884)) |
| 1688 | #define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31) | |
| 1689 | #define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30) | |
| 1690 | #define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2) | |
| 1691 | #define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1) | |
| 1692 | #define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0) | |
| 8bde7f77 WD |
1693 | |
| 1694 | /***DMA TX Channel 2 Command Register (SSC Port)***/ | |
| c021880a WD |
1695 | #define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888)) |
| 1696 | #define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31) | |
| 1697 | #define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30) | |
| 1698 | #define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29) | |
| 1699 | #define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2) | |
| 1700 | #define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1) | |
| 1701 | #define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0) | |
| 8bde7f77 | 1702 | |
| c021880a WD |
1703 | /***DMA First Receive Descriptor Addr. for Tx Channel 0 |
| 1704 | ***/ | |
| 1705 | #define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0)) | |
| 1706 | #define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) | |
| 8bde7f77 | 1707 | |
| c021880a WD |
1708 | /***DMA First Receive Descriptor Addr. for Tx Channel 1 |
| 1709 | ***/ | |
| 1710 | #define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4)) | |
| 1711 | #define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) | |
| 8bde7f77 | 1712 | |
| c021880a WD |
1713 | /***DMA First Receive Descriptor Addr. for Tx Channel 2 |
| 1714 | ***/ | |
| 1715 | #define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8)) | |
| 1716 | #define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1717 | |
| 1718 | /***DMA Transmit Channel Arbitration Register***/ | |
| c021880a WD |
1719 | #define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0)) |
| 1720 | #define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4) | |
| 1721 | #define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2) | |
| 1722 | #define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1723 | |
| 1724 | /***DMA Transmit Channel Polling Time***/ | |
| c021880a WD |
1725 | #define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4)) |
| 1726 | #define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30) | |
| 1727 | #define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28) | |
| 1728 | #define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26) | |
| 1729 | #define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1730 | |
| 1731 | /***DMA Transmit Interrupt Status Register***/ | |
| c021880a WD |
1732 | #define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8)) |
| 1733 | #define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) | |
| 1734 | #define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) | |
| 1735 | #define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) | |
| 1736 | #define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 1737 | #define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1738 | |
| 1739 | /***DMA Transmit Interrupt Mask Register***/ | |
| c021880a WD |
1740 | #define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC)) |
| 1741 | #define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) | |
| 1742 | #define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) | |
| 1743 | #define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) | |
| 1744 | #define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) | |
| 8bde7f77 WD |
1745 | #define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) |
| 1746 | ||
| c021880a WD |
1747 | /***********************************************************************/ |
| 1748 | /* Module : Debug register address and bits */ | |
| 1749 | /***********************************************************************/ | |
| 8bde7f77 | 1750 | |
| c021880a | 1751 | #define INCA_IP_Debug (0xBF106000) |
| 8bde7f77 WD |
1752 | /***********************************************************************/ |
| 1753 | ||
| c021880a | 1754 | |
| 8bde7f77 | 1755 | /***MCD Break Bus Switch Register***/ |
| c021880a WD |
1756 | #define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000)) |
| 1757 | #define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19) | |
| 1758 | #define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18) | |
| 1759 | #define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17) | |
| 1760 | #define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16) | |
| 1761 | #define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15) | |
| 1762 | #define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14) | |
| 1763 | #define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13) | |
| 1764 | #define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12) | |
| 1765 | #define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7) | |
| 1766 | #define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6) | |
| 1767 | #define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5) | |
| 1768 | #define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4) | |
| 8bde7f77 WD |
1769 | |
| 1770 | /***MCD Multiplexer Control Register***/ | |
| c021880a WD |
1771 | #define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008)) |
| 1772 | #define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4) | |
| 1773 | #define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3) | |
| 8bde7f77 WD |
1774 | #define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) |
| 1775 | ||
| c021880a WD |
1776 | /***********************************************************************/ |
| 1777 | /* Module : TSF register address and bits */ | |
| 1778 | /***********************************************************************/ | |
| 8bde7f77 | 1779 | |
| c021880a | 1780 | #define INCA_IP_TSF (0xB8000900) |
| 8bde7f77 WD |
1781 | /***********************************************************************/ |
| 1782 | ||
| c021880a | 1783 | |
| 8bde7f77 | 1784 | /***TSF Configuration Register (0000H)***/ |
| c021880a WD |
1785 | #define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000)) |
| 1786 | #define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2) | |
| 1787 | #define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1) | |
| 1788 | #define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0) | |
| 8bde7f77 WD |
1789 | |
| 1790 | /***Key scan Configuration Register (0004H)***/ | |
| c021880a WD |
1791 | #define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004)) |
| 1792 | #define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1793 | |
| 1794 | /***Scan Register Line 0 and 1 (0008H)***/ | |
| c021880a WD |
1795 | #define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008)) |
| 1796 | #define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16) | |
| 1797 | #define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1798 | |
| 1799 | /***Scan Register Line 2 and 3 (000CH)***/ | |
| c021880a WD |
1800 | #define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C)) |
| 1801 | #define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16) | |
| 1802 | #define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1803 | |
| 1804 | /***Scan Register Line 4, 5 and 6 (0010H)***/ | |
| c021880a WD |
1805 | #define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010)) |
| 1806 | #define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24) | |
| 1807 | #define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16) | |
| 1808 | #define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1809 | |
| 1810 | /***Scan Register Line 7 to 12 (0014H)***/ | |
| c021880a WD |
1811 | #define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014)) |
| 1812 | #define INCA_IP_TSF_SREG7to12_RES12x (1 << 28) | |
| 1813 | #define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24) | |
| 1814 | #define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20) | |
| 1815 | #define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16) | |
| 1816 | #define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8) | |
| 1817 | #define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1818 | |
| 1819 | /***LEDMUX Configuration Register (0018H)***/ | |
| c021880a WD |
1820 | #define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018)) |
| 1821 | #define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25) | |
| 1822 | #define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24) | |
| 1823 | #define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23) | |
| 1824 | #define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22) | |
| 1825 | #define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21) | |
| 1826 | #define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20) | |
| 1827 | #define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19) | |
| 1828 | #define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18) | |
| 1829 | #define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17) | |
| 1830 | #define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16) | |
| 1831 | #define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1) | |
| 1832 | #define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0) | |
| 8bde7f77 WD |
1833 | |
| 1834 | /***LED Register (001CH)***/ | |
| c021880a WD |
1835 | #define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C)) |
| 1836 | #define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0) | |
| 8bde7f77 WD |
1837 | |
| 1838 | /***Pulse Width Modulator 1 and 2 Register (0020H)***/ | |
| c021880a | 1839 | #define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020)) |
| 8bde7f77 WD |
1840 | #define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) |
| 1841 | ||
| c021880a WD |
1842 | /***********************************************************************/ |
| 1843 | /* Module : Ports register address and bits */ | |
| 1844 | /***********************************************************************/ | |
| 8bde7f77 | 1845 | |
| c021880a | 1846 | #define INCA_IP_Ports (0xB8000A00) |
| 8bde7f77 | 1847 | /***********************************************************************/ |
| c021880a | 1848 | |
| 8bde7f77 WD |
1849 | |
| 1850 | /***Port 1 Data Output Register (0020H)***/ | |
| c021880a WD |
1851 | #define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020)) |
| 1852 | #define INCA_IP_Ports_P1_OUT_P(value) (1 << value) | |
| 8bde7f77 WD |
1853 | |
| 1854 | ||
| 1855 | /***Port 2 Data Output Register (0040H)***/ | |
| c021880a WD |
1856 | #define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040)) |
| 1857 | #define INCA_IP_Ports_P2_OUT_P(value) (1 << value) | |
| 8bde7f77 WD |
1858 | |
| 1859 | ||
| 1860 | /***Port 1 Data Input Register (0024H)***/ | |
| c021880a WD |
1861 | #define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024)) |
| 1862 | #define INCA_IP_Ports_P1_IN_P(value) (1 << value) | |
| 8bde7f77 WD |
1863 | |
| 1864 | ||
| 1865 | /***Port 2 Data Input Register (0044H)***/ | |
| c021880a WD |
1866 | #define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044)) |
| 1867 | #define INCA_IP_Ports_P2_IN_P(value) (1 << value) | |
| 8bde7f77 WD |
1868 | |
| 1869 | ||
| 1870 | /***Port 1 Direction Register (0028H)***/ | |
| c021880a WD |
1871 | #define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028)) |
| 1872 | #define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value) | |
| 8bde7f77 | 1873 | |
| c021880a | 1874 | #define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) |
| 8bde7f77 WD |
1875 | |
| 1876 | /***Port 2 Direction Register (0048H)***/ | |
| c021880a WD |
1877 | #define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048)) |
| 1878 | #define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value) | |
| 8bde7f77 | 1879 | |
| c021880a | 1880 | #define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) |
| 8bde7f77 | 1881 | |
| c021880a WD |
1882 | /***Port 0 Alternate Function Select Register 0 (000C H) |
| 1883 | ***/ | |
| 1884 | #define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C)) | |
| 1885 | #define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value) | |
| 8bde7f77 WD |
1886 | |
| 1887 | ||
| c021880a WD |
1888 | /***Port 1 Alternate Function Select Register 0 (002C H) |
| 1889 | ***/ | |
| 1890 | #define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C)) | |
| 1891 | #define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value) | |
| 8bde7f77 | 1892 | |
| c021880a | 1893 | #define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value) |
| 8bde7f77 WD |
1894 | |
| 1895 | ||
| c021880a WD |
1896 | /***Port 2 Alternate Function Select Register 0 (004C H) |
| 1897 | ***/ | |
| 1898 | #define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C)) | |
| 1899 | #define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value) | |
| 8bde7f77 | 1900 | |
| c021880a | 1901 | #define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value) |
| 8bde7f77 WD |
1902 | |
| 1903 | ||
| c021880a WD |
1904 | /***Port 0 Input Schmitt-Trigger Off Register (0010 H) |
| 1905 | ***/ | |
| 1906 | #define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010)) | |
| 1907 | #define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value) | |
| 8bde7f77 WD |
1908 | |
| 1909 | ||
| c021880a WD |
1910 | /***Port 1 Input Schmitt-Trigger Off Register (0030 H) |
| 1911 | ***/ | |
| 1912 | #define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030)) | |
| 1913 | #define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value) | |
| 8bde7f77 | 1914 | |
| c021880a | 1915 | #define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value) |
| 8bde7f77 WD |
1916 | |
| 1917 | ||
| c021880a WD |
1918 | /***Port 2 Input Schmitt-Trigger Off Register (0050 H) |
| 1919 | ***/ | |
| 1920 | #define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050)) | |
| 1921 | #define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value) | |
| 8bde7f77 | 1922 | |
| c021880a | 1923 | #define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value) |
| 8bde7f77 WD |
1924 | |
| 1925 | ||
| 1926 | /***Port 2 Open Drain Control Register (0054H)***/ | |
| c021880a WD |
1927 | #define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054)) |
| 1928 | #define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value) | |
| 8bde7f77 WD |
1929 | |
| 1930 | ||
| 1931 | /***Port 0 Pull Up Device Enable Register (0018 H)***/ | |
| c021880a WD |
1932 | #define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018)) |
| 1933 | #define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value) | |
| 8bde7f77 WD |
1934 | |
| 1935 | ||
| 1936 | /***Port 2 Pull Up Device Enable Register (0058 H)***/ | |
| c021880a WD |
1937 | #define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058)) |
| 1938 | #define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) | |
| 8bde7f77 | 1939 | |
| c021880a | 1940 | #define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) |
| 8bde7f77 WD |
1941 | |
| 1942 | ||
| 1943 | /***Port 0 Pull Up/Pull Down Select Register (001C H)***/ | |
| c021880a WD |
1944 | #define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C)) |
| 1945 | #define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value) | |
| 8bde7f77 WD |
1946 | |
| 1947 | ||
| 1948 | /***Port 2 Pull Up/Pull Down Select Register (005C H)***/ | |
| c021880a WD |
1949 | #define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C)) |
| 1950 | #define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) | |
| 8bde7f77 | 1951 | |
| c021880a | 1952 | #define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) |
| 8bde7f77 WD |
1953 | |
| 1954 | ||
| c021880a WD |
1955 | /***********************************************************************/ |
| 1956 | /* Module : DES/3DES register address and bits */ | |
| 1957 | /***********************************************************************/ | |
| 8bde7f77 | 1958 | |
| c021880a | 1959 | #define INCA_IP_DES_3DES (0xB8000800) |
| 8bde7f77 WD |
1960 | /***********************************************************************/ |
| 1961 | ||
| c021880a | 1962 | |
| 8bde7f77 | 1963 | /***DES Input Data High Register***/ |
| c021880a WD |
1964 | #define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000)) |
| 1965 | #define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value) | |
| 8bde7f77 WD |
1966 | |
| 1967 | ||
| 1968 | /***DES Input Data Low Register***/ | |
| c021880a WD |
1969 | #define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004)) |
| 1970 | #define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value) | |
| 8bde7f77 WD |
1971 | |
| 1972 | ||
| 1973 | /***DES Key #1 High Register***/ | |
| c021880a WD |
1974 | #define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008)) |
| 1975 | #define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value) | |
| 8bde7f77 WD |
1976 | |
| 1977 | ||
| 1978 | /***DES Key #1 Low Register***/ | |
| c021880a WD |
1979 | #define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C)) |
| 1980 | #define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value) | |
| 8bde7f77 WD |
1981 | |
| 1982 | ||
| 1983 | /***DES Key #2 High Register***/ | |
| c021880a WD |
1984 | #define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010)) |
| 1985 | #define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value) | |
| 8bde7f77 WD |
1986 | |
| 1987 | ||
| 1988 | /***DES Key #2 Low Register***/ | |
| c021880a WD |
1989 | #define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014)) |
| 1990 | #define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value) | |
| 8bde7f77 WD |
1991 | |
| 1992 | ||
| 1993 | /***DES Key #3 High Register***/ | |
| c021880a WD |
1994 | #define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018)) |
| 1995 | #define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value) | |
| 8bde7f77 WD |
1996 | |
| 1997 | ||
| 1998 | /***DES Key #3 Low Register***/ | |
| c021880a WD |
1999 | #define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C)) |
| 2000 | #define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value) | |
| 8bde7f77 WD |
2001 | |
| 2002 | ||
| 2003 | /***DES Initialization Vector High Register***/ | |
| c021880a WD |
2004 | #define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020)) |
| 2005 | #define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value) | |
| 8bde7f77 WD |
2006 | |
| 2007 | ||
| 2008 | /***DES Initialization Vector Low Register***/ | |
| c021880a WD |
2009 | #define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024)) |
| 2010 | #define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value) | |
| 8bde7f77 WD |
2011 | |
| 2012 | ||
| 2013 | /***DES Control Register***/ | |
| c021880a WD |
2014 | #define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028)) |
| 2015 | #define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31) | |
| 2016 | #define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16) | |
| 2017 | #define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value) | |
| 8bde7f77 | 2018 | |
| c021880a | 2019 | #define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value) |
| 8bde7f77 | 2020 | |
| c021880a WD |
2021 | #define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8) |
| 2022 | #define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7) | |
| 2023 | #define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6) | |
| 2024 | #define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5) | |
| 2025 | #define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4) | |
| 2026 | #define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3) | |
| 2027 | #define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value) | |
| 8bde7f77 WD |
2028 | |
| 2029 | ||
| 2030 | /***DES Output Data High Register***/ | |
| c021880a WD |
2031 | #define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C)) |
| 2032 | #define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value) | |
| 8bde7f77 WD |
2033 | |
| 2034 | ||
| 2035 | /***DES Output Data Low Register***/ | |
| c021880a WD |
2036 | #define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030)) |
| 2037 | #define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value) | |
| 8bde7f77 WD |
2038 | |
| 2039 | ||
| c021880a WD |
2040 | /***********************************************************************/ |
| 2041 | /* Module : AES register address and bits */ | |
| 2042 | /***********************************************************************/ | |
| 8bde7f77 | 2043 | |
| c021880a | 2044 | #define INCA_IP_AES (0xB8000880) |
| 8bde7f77 WD |
2045 | /***********************************************************************/ |
| 2046 | ||
| c021880a | 2047 | |
| 8bde7f77 | 2048 | /***AES Input Data 3 Register***/ |
| c021880a WD |
2049 | #define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2050 | #define INCA_IP_AES_AES_ID3R_I(value) (1 << value) | |
| 8bde7f77 WD |
2051 | |
| 2052 | ||
| 2053 | /***AES Input Data 2 Register***/ | |
| c021880a WD |
2054 | #define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2055 | #define INCA_IP_AES_AES_ID2R_I(value) (1 << value) | |
| 8bde7f77 WD |
2056 | |
| 2057 | ||
| 2058 | /***AES Input Data 1 Register***/ | |
| c021880a WD |
2059 | #define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2060 | #define INCA_IP_AES_AES_ID1R_I(value) (1 << value) | |
| 8bde7f77 WD |
2061 | |
| 2062 | ||
| 2063 | /***AES Input Data 0 Register***/ | |
| c021880a WD |
2064 | #define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2065 | #define INCA_IP_AES_AES_ID0R_I(value) (1 << value) | |
| 8bde7f77 WD |
2066 | |
| 2067 | ||
| 2068 | /***AES Output Data 3 Register***/ | |
| c021880a WD |
2069 | #define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2070 | #define INCA_IP_AES_AES_OD3R_O(value) (1 << value) | |
| 8bde7f77 WD |
2071 | |
| 2072 | ||
| 2073 | /***AES Output Data 2 Register***/ | |
| c021880a WD |
2074 | #define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2075 | #define INCA_IP_AES_AES_OD2R_O(value) (1 << value) | |
| 8bde7f77 WD |
2076 | |
| 2077 | ||
| 2078 | /***AES Output Data 1 Register***/ | |
| c021880a WD |
2079 | #define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2080 | #define INCA_IP_AES_AES_OD1R_O(value) (1 << value) | |
| 8bde7f77 WD |
2081 | |
| 2082 | ||
| 2083 | /***AES Output Data 0 Register***/ | |
| c021880a WD |
2084 | #define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2085 | #define INCA_IP_AES_AES_OD0R_O(value) (1 << value) | |
| 8bde7f77 WD |
2086 | |
| 2087 | ||
| 2088 | /***AES Key 7 Register***/ | |
| c021880a WD |
2089 | #define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2090 | #define INCA_IP_AES_AES_K7R_K(value) (1 << value) | |
| 8bde7f77 WD |
2091 | |
| 2092 | ||
| 2093 | /***AES Key 6 Register***/ | |
| c021880a WD |
2094 | #define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2095 | #define INCA_IP_AES_AES_K6R_K(value) (1 << value) | |
| 8bde7f77 WD |
2096 | |
| 2097 | ||
| 2098 | /***AES Key 5 Register***/ | |
| c021880a WD |
2099 | #define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2100 | #define INCA_IP_AES_AES_K5R_K(value) (1 << value) | |
| 8bde7f77 WD |
2101 | |
| 2102 | ||
| 2103 | /***AES Key 4 Register***/ | |
| c021880a WD |
2104 | #define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2105 | #define INCA_IP_AES_AES_K4R_K(value) (1 << value) | |
| 8bde7f77 WD |
2106 | |
| 2107 | ||
| 2108 | /***AES Key 3 Register***/ | |
| c021880a WD |
2109 | #define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2110 | #define INCA_IP_AES_AES_K3R_K(value) (1 << value) | |
| 8bde7f77 WD |
2111 | |
| 2112 | ||
| 2113 | /***AES Key 2 Register***/ | |
| c021880a WD |
2114 | #define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2115 | #define INCA_IP_AES_AES_K2R_K(value) (1 << value) | |
| 8bde7f77 WD |
2116 | |
| 2117 | ||
| 2118 | /***AES Key 1 Register***/ | |
| c021880a WD |
2119 | #define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2120 | #define INCA_IP_AES_AES_K1R_K(value) (1 << value) | |
| 8bde7f77 WD |
2121 | |
| 2122 | ||
| 2123 | /***AES Key 0 Register***/ | |
| c021880a WD |
2124 | #define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2125 | #define INCA_IP_AES_AES_K0R_K(value) (1 << value) | |
| 8bde7f77 WD |
2126 | |
| 2127 | ||
| 2128 | /***AES Initialization Vector 3 Register***/ | |
| c021880a WD |
2129 | #define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2130 | #define INCA_IP_AES_AES_IV3R_IV(value) (1 << value) | |
| 8bde7f77 WD |
2131 | |
| 2132 | ||
| 2133 | /***AES Initialization Vector 2 Register***/ | |
| c021880a WD |
2134 | #define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2135 | #define INCA_IP_AES_AES_IV2R_IV(value) (1 << value) | |
| 8bde7f77 WD |
2136 | |
| 2137 | ||
| 2138 | /***AES Initialization Vector 1 Register***/ | |
| c021880a WD |
2139 | #define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2140 | #define INCA_IP_AES_AES_IV1R_IV(value) (1 << value) | |
| 8bde7f77 WD |
2141 | |
| 2142 | ||
| 2143 | /***AES Initialization Vector 0 Register***/ | |
| c021880a WD |
2144 | #define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2145 | #define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0) | |
| 8bde7f77 WD |
2146 | |
| 2147 | /***AES Control Register***/ | |
| c021880a WD |
2148 | #define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000)) |
| 2149 | #define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31) | |
| 2150 | #define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16) | |
| 2151 | #define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15) | |
| 2152 | #define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value) | |
| 8bde7f77 | 2153 | |
| c021880a | 2154 | #define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value) |
| 8bde7f77 | 2155 | |
| c021880a WD |
2156 | #define INCA_IP_AES_AES_CONTROLR_GO (1 << 8) |
| 2157 | #define INCA_IP_AES_AES_CONTROLR_STP (1 << 7) | |
| 2158 | #define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6) | |
| 2159 | #define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5) | |
| 2160 | #define INCA_IP_AES_AES_CONTROLR_SM (1 << 4) | |
| 2161 | #define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3) | |
| 2162 | #define INCA_IP_AES_AES_CONTROLR_KV (1 << 2) | |
| 2163 | #define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value) | |
| 8bde7f77 WD |
2164 | |
| 2165 | ||
| c021880a WD |
2166 | /***********************************************************************/ |
| 2167 |