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1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 1995 Waldorf GmbH | |
7 | * Copyright (C) 1994 - 2000 Ralf Baechle | |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | * Copyright (C) 2000 FSMLabs, Inc. | |
10 | */ | |
11 | #ifndef _ASM_IO_H | |
12 | #define _ASM_IO_H | |
13 | ||
14 | #include <linux/config.h> | |
15 | #if 0 | |
16 | #include <linux/pagemap.h> | |
17 | #endif | |
18 | #include <asm/addrspace.h> | |
19 | #include <asm/byteorder.h> | |
20 | ||
21 | /* | |
22 | * Slowdown I/O port space accesses for antique hardware. | |
23 | */ | |
24 | #undef CONF_SLOWDOWN_IO | |
25 | ||
26 | /* | |
27 | * Sane hardware offers swapping of I/O space accesses in hardware; less | |
28 | * sane hardware forces software to fiddle with this ... | |
29 | */ | |
30 | #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) | |
31 | ||
32 | #define __ioswab8(x) (x) | |
33 | #define __ioswab16(x) swab16(x) | |
34 | #define __ioswab32(x) swab32(x) | |
35 | ||
36 | #else | |
37 | ||
38 | #define __ioswab8(x) (x) | |
39 | #define __ioswab16(x) (x) | |
40 | #define __ioswab32(x) (x) | |
41 | ||
42 | #endif | |
43 | ||
44 | /* | |
45 | * This file contains the definitions for the MIPS counterpart of the | |
46 | * x86 in/out instructions. This heap of macros and C results in much | |
47 | * better code than the approach of doing it in plain C. The macros | |
48 | * result in code that is to fast for certain hardware. On the other | |
49 | * side the performance of the string functions should be improved for | |
50 | * sake of certain devices like EIDE disks that do highspeed polled I/O. | |
51 | * | |
52 | * Ralf | |
53 | * | |
54 | * This file contains the definitions for the x86 IO instructions | |
55 | * inb/inw/inl/outb/outw/outl and the "string versions" of the same | |
56 | * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" | |
57 | * versions of the single-IO instructions (inb_p/inw_p/..). | |
58 | * | |
59 | * This file is not meant to be obfuscating: it's just complicated | |
60 | * to (a) handle it all in a way that makes gcc able to optimize it | |
61 | * as well as possible and (b) trying to avoid writing the same thing | |
62 | * over and over again with slight variations and possibly making a | |
63 | * mistake somewhere. | |
64 | */ | |
65 | ||
66 | /* | |
67 | * On MIPS I/O ports are memory mapped, so we access them using normal | |
68 | * load/store instructions. mips_io_port_base is the virtual address to | |
69 | * which all ports are being mapped. For sake of efficiency some code | |
70 | * assumes that this is an address that can be loaded with a single lui | |
71 | * instruction, so the lower 16 bits must be zero. Should be true on | |
72 | * on any sane architecture; generic code does not use this assumption. | |
73 | */ | |
74 | extern unsigned long mips_io_port_base; | |
75 | ||
76 | /* | |
77 | * Thanks to James van Artsdalen for a better timing-fix than | |
78 | * the two short jumps: using outb's to a nonexistent port seems | |
79 | * to guarantee better timings even on fast machines. | |
80 | * | |
81 | * On the other hand, I'd like to be sure of a non-existent port: | |
82 | * I feel a bit unsafe about using 0x80 (should be safe, though) | |
83 | * | |
84 | * Linus | |
85 | * | |
86 | */ | |
87 | ||
88 | #define __SLOW_DOWN_IO \ | |
89 | __asm__ __volatile__( \ | |
90 | "sb\t$0,0x80(%0)" \ | |
91 | : : "r" (mips_io_port_base)); | |
92 | ||
93 | #ifdef CONF_SLOWDOWN_IO | |
94 | #ifdef REALLY_SLOW_IO | |
95 | #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } | |
96 | #else | |
97 | #define SLOW_DOWN_IO __SLOW_DOWN_IO | |
98 | #endif | |
99 | #else | |
100 | #define SLOW_DOWN_IO | |
101 | #endif | |
102 | ||
103 | /* | |
104 | * Change virtual addresses to physical addresses and vv. | |
105 | * These are trivial on the 1:1 Linux/MIPS mapping | |
106 | */ | |
107 | extern inline unsigned long virt_to_phys(volatile void * address) | |
108 | { | |
109 | return PHYSADDR(address); | |
110 | } | |
111 | ||
112 | extern inline void * phys_to_virt(unsigned long address) | |
113 | { | |
114 | return (void *)KSEG0ADDR(address); | |
115 | } | |
116 | ||
117 | /* | |
118 | * IO bus memory addresses are also 1:1 with the physical address | |
119 | */ | |
120 | extern inline unsigned long virt_to_bus(volatile void * address) | |
121 | { | |
122 | return PHYSADDR(address); | |
123 | } | |
124 | ||
125 | extern inline void * bus_to_virt(unsigned long address) | |
126 | { | |
127 | return (void *)KSEG0ADDR(address); | |
128 | } | |
129 | ||
130 | /* | |
131 | * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped | |
132 | * for the processor. | |
133 | */ | |
134 | extern unsigned long isa_slot_offset; | |
135 | ||
136 | extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); | |
137 | ||
138 | #if 0 | |
139 | extern inline void *ioremap(unsigned long offset, unsigned long size) | |
140 | { | |
141 | return __ioremap(offset, size, _CACHE_UNCACHED); | |
142 | } | |
143 | ||
144 | extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) | |
145 | { | |
146 | return __ioremap(offset, size, _CACHE_UNCACHED); | |
147 | } | |
148 | ||
149 | extern void iounmap(void *addr); | |
150 | #endif | |
151 | ||
152 | /* | |
153 | * XXX We need system specific versions of these to handle EISA address bits | |
154 | * 24-31 on SNI. | |
155 | * XXX more SNI hacks. | |
156 | */ | |
157 | #define readb(addr) (*(volatile unsigned char *)(addr)) | |
158 | #define readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) | |
159 | #define readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) | |
160 | #define __raw_readb readb | |
161 | #define __raw_readw readw | |
162 | #define __raw_readl readl | |
163 | ||
164 | #define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) | |
165 | #define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) | |
166 | #define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) | |
167 | #define __raw_writeb writeb | |
168 | #define __raw_writew writew | |
169 | #define __raw_writel writel | |
170 | ||
171 | #define memset_io(a,b,c) memset((void *)(a),(b),(c)) | |
172 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | |
173 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | |
174 | ||
175 | /* END SNI HACKS ... */ | |
176 | ||
177 | /* | |
178 | * ISA space is 'always mapped' on currently supported MIPS systems, no need | |
179 | * to explicitly ioremap() it. The fact that the ISA IO space is mapped | |
180 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values | |
181 | * are physical addresses. The following constant pointer can be | |
182 | * used as the IO-area pointer (it can be iounmapped as well, so the | |
183 | * analogy with PCI is quite large): | |
184 | */ | |
185 | #define __ISA_IO_base ((char *)(PAGE_OFFSET)) | |
186 | ||
187 | #define isa_readb(a) readb(a) | |
188 | #define isa_readw(a) readw(a) | |
189 | #define isa_readl(a) readl(a) | |
190 | #define isa_writeb(b,a) writeb(b,a) | |
191 | #define isa_writew(w,a) writew(w,a) | |
192 | #define isa_writel(l,a) writel(l,a) | |
193 | ||
194 | #define isa_memset_io(a,b,c) memset_io((a),(b),(c)) | |
195 | #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) | |
196 | #define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) | |
197 | ||
198 | /* | |
199 | * We don't have csum_partial_copy_fromio() yet, so we cheat here and | |
200 | * just copy it. The net code will then do the checksum later. | |
201 | */ | |
202 | #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) | |
203 | #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) | |
204 | ||
205 | static inline int check_signature(unsigned long io_addr, | |
206 | const unsigned char *signature, int length) | |
207 | { | |
208 | int retval = 0; | |
209 | do { | |
210 | if (readb(io_addr) != *signature) | |
211 | goto out; | |
212 | io_addr++; | |
213 | signature++; | |
214 | length--; | |
215 | } while (length); | |
216 | retval = 1; | |
217 | out: | |
218 | return retval; | |
219 | } | |
220 | #define isa_check_signature(io, s, l) check_signature(i,s,l) | |
221 | ||
222 | /* | |
223 | * Talk about misusing macros.. | |
224 | */ | |
225 | ||
226 | #define __OUT1(s) \ | |
227 | extern inline void __out##s(unsigned int value, unsigned int port) { | |
228 | ||
229 | #define __OUT2(m) \ | |
230 | __asm__ __volatile__ ("s" #m "\t%0,%1(%2)" | |
231 | ||
232 | #define __OUT(m,s,w) \ | |
233 | __OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \ | |
234 | __OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \ | |
235 | __OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \ | |
236 | SLOW_DOWN_IO; } \ | |
237 | __OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \ | |
238 | SLOW_DOWN_IO; } | |
239 | ||
240 | #define __IN1(t,s) \ | |
241 | extern __inline__ t __in##s(unsigned int port) { t _v; | |
242 | ||
243 | /* | |
244 | * Required nops will be inserted by the assembler | |
245 | */ | |
246 | #define __IN2(m) \ | |
247 | __asm__ __volatile__ ("l" #m "\t%0,%1(%2)" | |
248 | ||
249 | #define __IN(t,m,s,w) \ | |
250 | __IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \ | |
251 | __IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \ | |
252 | __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \ | |
253 | __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } | |
254 | ||
255 | #define __INS1(s) \ | |
256 | extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) { | |
257 | ||
258 | #define __INS2(m) \ | |
259 | if (count) \ | |
260 | __asm__ __volatile__ ( \ | |
261 | ".set\tnoreorder\n\t" \ | |
262 | ".set\tnoat\n" \ | |
263 | "1:\tl" #m "\t$1,%4(%5)\n\t" \ | |
264 | "subu\t%1,1\n\t" \ | |
265 | "s" #m "\t$1,(%0)\n\t" \ | |
266 | "bne\t$0,%1,1b\n\t" \ | |
267 | "addiu\t%0,%6\n\t" \ | |
268 | ".set\tat\n\t" \ | |
269 | ".set\treorder" | |
270 | ||
271 | #define __INS(m,s,i) \ | |
272 | __INS1(s) __INS2(m) \ | |
273 | : "=r" (addr), "=r" (count) \ | |
274 | : "0" (addr), "1" (count), "i" (0), \ | |
275 | "r" (mips_io_port_base+port), "I" (i) \ | |
276 | : "$1");} \ | |
277 | __INS1(s##c) __INS2(m) \ | |
278 | : "=r" (addr), "=r" (count) \ | |
279 | : "0" (addr), "1" (count), "ir" (port), \ | |
280 | "r" (mips_io_port_base), "I" (i) \ | |
281 | : "$1");} | |
282 | ||
283 | #define __OUTS1(s) \ | |
284 | extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { | |
285 | ||
286 | #define __OUTS2(m) \ | |
287 | if (count) \ | |
288 | __asm__ __volatile__ ( \ | |
289 | ".set\tnoreorder\n\t" \ | |
290 | ".set\tnoat\n" \ | |
291 | "1:\tl" #m "\t$1,(%0)\n\t" \ | |
292 | "subu\t%1,1\n\t" \ | |
293 | "s" #m "\t$1,%4(%5)\n\t" \ | |
294 | "bne\t$0,%1,1b\n\t" \ | |
295 | "addiu\t%0,%6\n\t" \ | |
296 | ".set\tat\n\t" \ | |
297 | ".set\treorder" | |
298 | ||
299 | #define __OUTS(m,s,i) \ | |
300 | __OUTS1(s) __OUTS2(m) \ | |
301 | : "=r" (addr), "=r" (count) \ | |
302 | : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ | |
303 | : "$1");} \ | |
304 | __OUTS1(s##c) __OUTS2(m) \ | |
305 | : "=r" (addr), "=r" (count) \ | |
306 | : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ | |
307 | : "$1");} | |
308 | ||
309 | __IN(unsigned char,b,b,8) | |
310 | __IN(unsigned short,h,w,16) | |
311 | __IN(unsigned int,w,l,32) | |
312 | ||
313 | __OUT(b,b,8) | |
314 | __OUT(h,w,16) | |
315 | __OUT(w,l,32) | |
316 | ||
317 | __INS(b,b,1) | |
318 | __INS(h,w,2) | |
319 | __INS(w,l,4) | |
320 | ||
321 | __OUTS(b,b,1) | |
322 | __OUTS(h,w,2) | |
323 | __OUTS(w,l,4) | |
324 | ||
325 | ||
326 | /* | |
327 | * Note that due to the way __builtin_constant_p() works, you | |
328 | * - can't use it inside an inline function (it will never be true) | |
329 | * - you don't have to worry about side effects within the __builtin.. | |
330 | */ | |
331 | #define outb(val,port) \ | |
332 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
333 | __outbc((val),(port)) : \ | |
334 | __outb((val),(port))) | |
335 | ||
336 | #define inb(port) \ | |
337 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
338 | __inbc(port) : \ | |
339 | __inb(port)) | |
340 | ||
341 | #define outb_p(val,port) \ | |
342 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
343 | __outbc_p((val),(port)) : \ | |
344 | __outb_p((val),(port))) | |
345 | ||
346 | #define inb_p(port) \ | |
347 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
348 | __inbc_p(port) : \ | |
349 | __inb_p(port)) | |
350 | ||
351 | #define outw(val,port) \ | |
352 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
353 | __outwc((val),(port)) : \ | |
354 | __outw((val),(port))) | |
355 | ||
356 | #define inw(port) \ | |
357 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
358 | __inwc(port) : \ | |
359 | __inw(port)) | |
360 | ||
361 | #define outw_p(val,port) \ | |
362 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
363 | __outwc_p((val),(port)) : \ | |
364 | __outw_p((val),(port))) | |
365 | ||
366 | #define inw_p(port) \ | |
367 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
368 | __inwc_p(port) : \ | |
369 | __inw_p(port)) | |
370 | ||
371 | #define outl(val,port) \ | |
372 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
373 | __outlc((val),(port)) : \ | |
374 | __outl((val),(port))) | |
375 | ||
376 | #define inl(port) \ | |
377 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
378 | __inlc(port) : \ | |
379 | __inl(port)) | |
380 | ||
381 | #define outl_p(val,port) \ | |
382 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
383 | __outlc_p((val),(port)) : \ | |
384 | __outl_p((val),(port))) | |
385 | ||
386 | #define inl_p(port) \ | |
387 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
388 | __inlc_p(port) : \ | |
389 | __inl_p(port)) | |
390 | ||
391 | ||
392 | #define outsb(port,addr,count) \ | |
393 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
394 | __outsbc((port),(addr),(count)) : \ | |
395 | __outsb ((port),(addr),(count))) | |
396 | ||
397 | #define insb(port,addr,count) \ | |
398 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
399 | __insbc((port),(addr),(count)) : \ | |
400 | __insb((port),(addr),(count))) | |
401 | ||
402 | #define outsw(port,addr,count) \ | |
403 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
404 | __outswc((port),(addr),(count)) : \ | |
405 | __outsw ((port),(addr),(count))) | |
406 | ||
407 | #define insw(port,addr,count) \ | |
408 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
409 | __inswc((port),(addr),(count)) : \ | |
410 | __insw((port),(addr),(count))) | |
411 | ||
412 | #define outsl(port,addr,count) \ | |
413 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
414 | __outslc((port),(addr),(count)) : \ | |
415 | __outsl ((port),(addr),(count))) | |
416 | ||
417 | #define insl(port,addr,count) \ | |
418 | ((__builtin_constant_p((port)) && (port) < 32768) ? \ | |
419 | __inslc((port),(addr),(count)) : \ | |
420 | __insl((port),(addr),(count))) | |
421 | ||
422 | #define IO_SPACE_LIMIT 0xffff | |
423 | ||
424 | /* | |
425 | * The caches on some architectures aren't dma-coherent and have need to | |
426 | * handle this in software. There are three types of operations that | |
427 | * can be applied to dma buffers. | |
428 | * | |
429 | * - dma_cache_wback_inv(start, size) makes caches and coherent by | |
430 | * writing the content of the caches back to memory, if necessary. | |
431 | * The function also invalidates the affected part of the caches as | |
432 | * necessary before DMA transfers from outside to memory. | |
433 | * - dma_cache_wback(start, size) makes caches and coherent by | |
434 | * writing the content of the caches back to memory, if necessary. | |
435 | * The function also invalidates the affected part of the caches as | |
436 | * necessary before DMA transfers from outside to memory. | |
437 | * - dma_cache_inv(start, size) invalidates the affected parts of the | |
438 | * caches. Dirty lines of the caches may be written back or simply | |
439 | * be discarded. This operation is necessary before dma operations | |
440 | * to the memory. | |
441 | */ | |
442 | extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); | |
443 | extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); | |
444 | extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); | |
445 | ||
446 | #define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) | |
447 | #define dma_cache_wback(start,size) _dma_cache_wback(start,size) | |
448 | #define dma_cache_inv(start,size) _dma_cache_inv(start,size) | |
449 | ||
450 | #endif /* _ASM_IO_H */ |