[thirdparty/kernel/stable.git] / include / asm-powerpc / mmu.h

#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_

#ifndef CONFIG_PPC64
#include <asm-ppc/mmu.h>
#else

/*
 * PowerPC memory management structures
 *
 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
 *   PPC64 rework.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/asm-compat.h>
#include <asm/page.h>

/*
 * Segment table
 */

#define STE_ESID_V	0x80
#define STE_ESID_KS	0x20
#define STE_ESID_KP	0x10
#define STE_ESID_N	0x08

#define STE_VSID_SHIFT	12

/* Location of cpu0's segment table */
#define STAB0_PAGE	0x6
#define STAB0_OFFSET	(STAB0_PAGE << 12)
#define STAB0_PHYS_ADDR	(STAB0_OFFSET + PHYSICAL_START)

#ifndef __ASSEMBLY__
extern char initial_stab[];
#endif /* ! __ASSEMBLY */

/*
 * SLB
 */

#define SLB_NUM_BOLTED		3
#define SLB_CACHE_ENTRIES	8

/* Bits in the SLB ESID word */
#define SLB_ESID_V		ASM_CONST(0x0000000008000000) /* valid */

/* Bits in the SLB VSID word */
#define SLB_VSID_SHIFT		12
#define SLB_VSID_B		ASM_CONST(0xc000000000000000)
#define SLB_VSID_B_256M		ASM_CONST(0x0000000000000000)
#define SLB_VSID_B_1T		ASM_CONST(0x4000000000000000)
#define SLB_VSID_KS		ASM_CONST(0x0000000000000800)
#define SLB_VSID_KP		ASM_CONST(0x0000000000000400)
#define SLB_VSID_N		ASM_CONST(0x0000000000000200) /* no-execute */
#define SLB_VSID_L		ASM_CONST(0x0000000000000100)
#define SLB_VSID_C		ASM_CONST(0x0000000000000080) /* class */
#define SLB_VSID_LP		ASM_CONST(0x0000000000000030)
#define SLB_VSID_LP_00		ASM_CONST(0x0000000000000000)
#define SLB_VSID_LP_01		ASM_CONST(0x0000000000000010)
#define SLB_VSID_LP_10		ASM_CONST(0x0000000000000020)
#define SLB_VSID_LP_11		ASM_CONST(0x0000000000000030)
#define SLB_VSID_LLP		(SLB_VSID_L|SLB_VSID_LP)

#define SLB_VSID_KERNEL		(SLB_VSID_KP)
#define SLB_VSID_USER		(SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)

#define SLBIE_C			(0x08000000)

/*
 * Hash table
 */

#define HPTES_PER_GROUP 8

#define HPTE_V_AVPN_SHIFT	7
#define HPTE_V_AVPN		ASM_CONST(0xffffffffffffff80)
#define HPTE_V_AVPN_VAL(x)	(((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
#define HPTE_V_COMPARE(x,y)	(!(((x) ^ (y)) & HPTE_V_AVPN))
#define HPTE_V_BOLTED		ASM_CONST(0x0000000000000010)
#define HPTE_V_LOCK		ASM_CONST(0x0000000000000008)
#define HPTE_V_LARGE		ASM_CONST(0x0000000000000004)
#define HPTE_V_SECONDARY	ASM_CONST(0x0000000000000002)
#define HPTE_V_VALID		ASM_CONST(0x0000000000000001)

#define HPTE_R_PP0		ASM_CONST(0x8000000000000000)
#define HPTE_R_TS		ASM_CONST(0x4000000000000000)
#define HPTE_R_RPN_SHIFT	12
#define HPTE_R_RPN		ASM_CONST(0x3ffffffffffff000)
#define HPTE_R_FLAGS		ASM_CONST(0x00000000000003ff)
#define HPTE_R_PP		ASM_CONST(0x0000000000000003)
#define HPTE_R_N		ASM_CONST(0x0000000000000004)

/* Values for PP (assumes Ks=0, Kp=1) */
/* pp0 will always be 0 for linux     */
#define PP_RWXX	0	/* Supervisor read/write, User none */
#define PP_RWRX 1	/* Supervisor read/write, User read */
#define PP_RWRW 2	/* Supervisor read/write, User read/write */
#define PP_RXRX 3	/* Supervisor read,       User read */

#ifndef __ASSEMBLY__

typedef struct {
	unsigned long v;
	unsigned long r;
} hpte_t;

extern hpte_t *htab_address;
extern unsigned long htab_hash_mask;

/*
 * Page size definition
 *
 *    shift : is the "PAGE_SHIFT" value for that page size
 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 *            directly to a slbmte "vsid" value
 *    penc  : is the HPTE encoding mask for the "LP" field:
 *
 */
struct mmu_psize_def
{
	unsigned int	shift;	/* number of bits */
	unsigned int	penc;	/* HPTE encoding */
	unsigned int	tlbiel;	/* tlbiel supported for that page size */
	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
	unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
};

#endif /* __ASSEMBLY__ */

/*
 * The kernel use the constants below to index in the page sizes array.
 * The use of fixed constants for this purpose is better for performances
 * of the low level hash refill handlers.
 *
 * A non supported page size has a "shift" field set to 0
 *
 * Any new page size being implemented can get a new entry in here. Whether
 * the kernel will use it or not is a different matter though. The actual page
 * size used by hugetlbfs is not defined here and may be made variable
 */

#define MMU_PAGE_4K		0	/* 4K */
#define MMU_PAGE_64K		1	/* 64K */
#define MMU_PAGE_64K_AP		2	/* 64K Admixed (in a 4K segment) */
#define MMU_PAGE_1M		3	/* 1M */
#define MMU_PAGE_16M		4	/* 16M */
#define MMU_PAGE_16G		5	/* 16G */
#define MMU_PAGE_COUNT		6

#ifndef __ASSEMBLY__

/*
 * The current system page sizes
 */
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
extern int mmu_linear_psize;
extern int mmu_virtual_psize;

#ifdef CONFIG_HUGETLB_PAGE
/*
 * The page size index of the huge pages for use by hugetlbfs
 */
extern int mmu_huge_psize;

#endif /* CONFIG_HUGETLB_PAGE */

/*
 * This function sets the AVPN and L fields of the HPTE  appropriately
 * for the page size
 */
static inline unsigned long hpte_encode_v(unsigned long va, int psize)
{
	unsigned long v =
	v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
	v <<= HPTE_V_AVPN_SHIFT;
	if (psize != MMU_PAGE_4K)
		v |= HPTE_V_LARGE;
	return v;
}

/*
 * This function sets the ARPN, and LP fields of the HPTE appropriately
 * for the page size. We assume the pa is already "clean" that is properly
 * aligned for the requested page size
 */
static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
{
	unsigned long r;

	/* A 4K page needs no special encoding */
	if (psize == MMU_PAGE_4K)
		return pa & HPTE_R_RPN;
	else {
		unsigned int penc = mmu_psize_defs[psize].penc;
		unsigned int shift = mmu_psize_defs[psize].shift;
		return (pa & ~((1ul << shift) - 1)) | (penc << 12);
	}
	return r;
}

/*
 * This hashes a virtual address for a 256Mb segment only for now
 */

static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
{
	return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
}

extern int __hash_page_4K(unsigned long ea, unsigned long access,
			  unsigned long vsid, pte_t *ptep, unsigned long trap,
			  unsigned int local);
extern int __hash_page_64K(unsigned long ea, unsigned long access,
			   unsigned long vsid, pte_t *ptep, unsigned long trap,
			   unsigned int local);
struct mm_struct;
extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
			  unsigned long ea, unsigned long vsid, int local,
			  unsigned long trap);

extern void htab_finish_init(void);
extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
			     unsigned long pstart, unsigned long mode,
			     int psize);

extern void htab_initialize(void);
extern void htab_initialize_secondary(void);
extern void hpte_init_native(void);
extern void hpte_init_lpar(void);
extern void hpte_init_iSeries(void);
extern void mm_init_ppc64(void);

extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
				     unsigned long va, unsigned long prpn,
				     unsigned long rflags,
				     unsigned long vflags, int psize);

extern long native_hpte_insert(unsigned long hpte_group,
			       unsigned long va, unsigned long prpn,
			       unsigned long rflags,
			       unsigned long vflags, int psize);

extern long iSeries_hpte_insert(unsigned long hpte_group,
				unsigned long va, unsigned long prpn,
				unsigned long rflags,
				unsigned long vflags, int psize);

extern void stabs_alloc(void);
extern void slb_initialize(void);
extern void stab_initialize(unsigned long stab);

#endif /* __ASSEMBLY__ */

/*
 * VSID allocation
 *
 * We first generate a 36-bit "proto-VSID".  For kernel addresses this
 * is equal to the ESID, for user addresses it is:
 *	(context << 15) | (esid & 0x7fff)
 *
 * The two forms are distinguishable because the top bit is 0 for user
 * addresses, whereas the top two bits are 1 for kernel addresses.
 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
 * now.
 *
 * The proto-VSIDs are then scrambled into real VSIDs with the
 * multiplicative hash:
 *
 *	VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 *	where	VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
 *		VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
 *
 * This scramble is only well defined for proto-VSIDs below
 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
 * reserved.  VSID_MULTIPLIER is prime, so in particular it is
 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 * Because the modulus is 2^n-1 we can compute it efficiently without
 * a divide or extra multiply (see below).
 *
 * This scheme has several advantages over older methods:
 *
 * 	- We have VSIDs allocated for every kernel address
 * (i.e. everything above 0xC000000000000000), except the very top
 * segment, which simplifies several things.
 *
 * 	- We allow for 15 significant bits of ESID and 20 bits of
 * context for user addresses.  i.e. 8T (43 bits) of address space for
 * up to 1M contexts (although the page table structure and context
 * allocation will need changes to take advantage of this).
 *
 * 	- The scramble function gives robust scattering in the hash
 * table (at least based on some initial results).  The previous
 * method was more susceptible to pathological cases giving excessive
 * hash collisions.
 */
/*
 * WARNING - If you change these you must make sure the asm
 * implementations in slb_allocate (slb_low.S), do_stab_bolted
 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
 *
 * You'll also need to change the precomputed VSID values in head.S
 * which are used by the iSeries firmware.
 */

#define VSID_MULTIPLIER	ASM_CONST(200730139)	/* 28-bit prime */
#define VSID_BITS	36
#define VSID_MODULUS	((1UL<<VSID_BITS)-1)

#define CONTEXT_BITS	19
#define USER_ESID_BITS	16

#define USER_VSID_RANGE	(1UL << (USER_ESID_BITS + SID_SHIFT))

/*
 * This macro generates asm code to compute the VSID scramble
 * function.  Used in slb_allocate() and do_stab_bolted.  The function
 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 *
 *	rt = register continaing the proto-VSID and into which the
 *		VSID will be stored
 *	rx = scratch register (clobbered)
 *
 * 	- rt and rx must be different registers
 * 	- The answer will end up in the low 36 bits of rt.  The higher
 * 	  bits may contain other garbage, so you may need to mask the
 * 	  result.
 */
#define ASM_VSID_SCRAMBLE(rt, rx)	\
	lis	rx,VSID_MULTIPLIER@h;					\
	ori	rx,rx,VSID_MULTIPLIER@l;				\
	mulld	rt,rt,rx;		/* rt = rt * MULTIPLIER */	\
									\
	srdi	rx,rt,VSID_BITS;					\
	clrldi	rt,rt,(64-VSID_BITS);					\
	add	rt,rt,rx;		/* add high and low bits */	\
	/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and		\
	 * 2^36-1+2^28-1.  That in particular means that if r3 >=	\
	 * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has	\
	 * the bit clear, r3 already has the answer we want, if it	\
	 * doesn't, the answer is the low 36 bits of r3+1.  So in all	\
	 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
	addi	rx,rt,1;						\
	srdi	rx,rx,VSID_BITS;	/* extract 2^36 bit */		\
	add	rt,rt,rx


#ifndef __ASSEMBLY__

typedef unsigned long mm_context_id_t;

typedef struct {
	mm_context_id_t id;
#ifdef CONFIG_HUGETLB_PAGE
	u16 low_htlb_areas, high_htlb_areas;
#endif
} mm_context_t;


static inline unsigned long vsid_scramble(unsigned long protovsid)
{
#if 0
	/* The code below is equivalent to this function for arguments
	 * < 2^VSID_BITS, which is all this should ever be called
	 * with.  However gcc is not clever enough to compute the
	 * modulus (2^n-1) without a second multiply. */
	return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
#else /* 1 */
	unsigned long x;

	x = protovsid * VSID_MULTIPLIER;
	x = (x >> VSID_BITS) + (x & VSID_MODULUS);
	return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
#endif /* 1 */
}

/* This is only valid for addresses >= KERNELBASE */
static inline unsigned long get_kernel_vsid(unsigned long ea)
{
	return vsid_scramble(ea >> SID_SHIFT);
}

/* This is only valid for user addresses (which are below 2^41) */
static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
{
	return vsid_scramble((context << USER_ESID_BITS)
			     | (ea >> SID_SHIFT));
}

#define VSID_SCRAMBLE(pvsid)	(((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
#define KERNEL_VSID(ea)		VSID_SCRAMBLE(GET_ESID(ea))

/* Physical address used by some IO functions */
typedef unsigned long phys_addr_t;


#endif /* __ASSEMBLY */

#endif /* CONFIG_PPC64 */
#endif /* _ASM_POWERPC_MMU_H_ */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_MMU_H_
	2	#define _ASM_POWERPC_MMU_H_
	3
	4	#ifndef CONFIG_PPC64
	5	#include <asm-ppc/mmu.h>
	6	#else
	7
1da177e4 LT	8	/*
	9	* PowerPC memory management structures
	10	*
	11	* Dave Engebretsen & Mike Corrigan <{engebret\|mikejc}@us.ibm.com>
	12	* PPC64 rework.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License
	16	* as published by the Free Software Foundation; either version
	17	* 2 of the License, or (at your option) any later version.
	18	*/
	19
3ddfbcf1	20	#include <asm/asm-compat.h>
1da177e4	21	#include <asm/page.h>
1da177e4	22
1f8d419e DG	23	/*
	24	* Segment table
	25	*/
1da177e4 LT	26
	27	#define STE_ESID_V 0x80
	28	#define STE_ESID_KS 0x20
	29	#define STE_ESID_KP 0x10
	30	#define STE_ESID_N 0x08
	31
	32	#define STE_VSID_SHIFT 12
	33
1f8d419e	34	/* Location of cpu0's segment table */
c59c464a	35	#define STAB0_PAGE 0x6
758438a7 ME	36	#define STAB0_OFFSET (STAB0_PAGE << 12)
758438a7 ME	37	#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
c59c464a DG	38
	39	#ifndef __ASSEMBLY__
	40	extern char initial_stab[];
	41	#endif /* ! __ASSEMBLY */
1f8d419e DG	42
	43	/*
	44	* SLB
	45	*/
1da177e4	46
1f8d419e DG	47	#define SLB_NUM_BOLTED 3
	48	#define SLB_CACHE_ENTRIES 8
	49
	50	/* Bits in the SLB ESID word */
	51	#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
	52
	53	/* Bits in the SLB VSID word */
	54	#define SLB_VSID_SHIFT 12
3c726f8d BH	55	#define SLB_VSID_B ASM_CONST(0xc000000000000000)
	56	#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
	57	#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
1f8d419e DG	58	#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
	59	#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
	60	#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
3c726f8d	61	#define SLB_VSID_L ASM_CONST(0x0000000000000100)
1f8d419e	62	#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
3c726f8d BH	63	#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
	64	#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
	65	#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
	66	#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
	67	#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
	68	#define SLB_VSID_LLP (SLB_VSID_L\|SLB_VSID_LP)
	69
14b34661 DG	70	#define SLB_VSID_KERNEL (SLB_VSID_KP)
	71	#define SLB_VSID_USER (SLB_VSID_KP\|SLB_VSID_KS\|SLB_VSID_C)
	72
	73	#define SLBIE_C (0x08000000)
1f8d419e DG	74
	75	/*
	76	* Hash table
	77	*/
1da177e4 LT	78
	79	#define HPTES_PER_GROUP 8
	80
96e28449 DG	81	#define HPTE_V_AVPN_SHIFT 7
	82	#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
	83	#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
3c726f8d	84	#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN))
96e28449 DG	85	#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
	86	#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
	87	#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
	88	#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
	89	#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
	90
	91	#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
	92	#define HPTE_R_TS ASM_CONST(0x4000000000000000)
	93	#define HPTE_R_RPN_SHIFT 12
	94	#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
	95	#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
	96	#define HPTE_R_PP ASM_CONST(0x0000000000000003)
3c726f8d	97	#define HPTE_R_N ASM_CONST(0x0000000000000004)
96e28449	98
1f8d419e DG	99	/* Values for PP (assumes Ks=0, Kp=1) */
	100	/* pp0 will always be 0 for linux */
	101	#define PP_RWXX 0 /* Supervisor read/write, User none */
	102	#define PP_RWRX 1 /* Supervisor read/write, User read */
	103	#define PP_RWRW 2 /* Supervisor read/write, User read/write */
	104	#define PP_RXRX 3 /* Supervisor read, User read */
	105
	106	#ifndef __ASSEMBLY__
	107
1da177e4	108	typedef struct {
96e28449 DG	109	unsigned long v;
	110	unsigned long r;
	111	} hpte_t;
1da177e4	112
96e28449 DG	113	extern hpte_t *htab_address;
96e28449 DG	114	extern unsigned long htab_hash_mask;
1da177e4	115
3c726f8d BH	116	/*
	117	* Page size definition
	118	*
	119	* shift : is the "PAGE_SHIFT" value for that page size
	120	* sllp : is a bit mask with the value of SLB L \|\| LP to be or'ed
	121	* directly to a slbmte "vsid" value
	122	* penc : is the HPTE encoding mask for the "LP" field:
	123	*
	124	*/
	125	struct mmu_psize_def
1da177e4	126	{
3c726f8d BH	127	unsigned int shift; /* number of bits */
	128	unsigned int penc; /* HPTE encoding */
	129	unsigned int tlbiel; /* tlbiel supported for that page size */
	130	unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
	131	unsigned long sllp; /* SLB L\|\|LP (exact mask to use in slbmte) */
	132	};
1da177e4	133
3c726f8d	134	#endif /* __ASSEMBLY__ */
1da177e4	135
3c726f8d BH	136	/*
	137	* The kernel use the constants below to index in the page sizes array.
	138	* The use of fixed constants for this purpose is better for performances
	139	* of the low level hash refill handlers.
	140	*
	141	* A non supported page size has a "shift" field set to 0
	142	*
	143	* Any new page size being implemented can get a new entry in here. Whether
	144	* the kernel will use it or not is a different matter though. The actual page
	145	* size used by hugetlbfs is not defined here and may be made variable
	146	*/
1da177e4	147
3c726f8d BH	148	#define MMU_PAGE_4K 0 /* 4K */
	149	#define MMU_PAGE_64K 1 /* 64K */
	150	#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
	151	#define MMU_PAGE_1M 3 /* 1M */
	152	#define MMU_PAGE_16M 4 /* 16M */
	153	#define MMU_PAGE_16G 5 /* 16G */
	154	#define MMU_PAGE_COUNT 6
1da177e4	155
3c726f8d	156	#ifndef __ASSEMBLY__
1da177e4	157
3c726f8d BH	158	/*
	159	* The current system page sizes
	160	*/
	161	extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
	162	extern int mmu_linear_psize;
	163	extern int mmu_virtual_psize;
f4c82d51	164
3c726f8d BH	165	#ifdef CONFIG_HUGETLB_PAGE
	166	/*
	167	* The page size index of the huge pages for use by hugetlbfs
	168	*/
	169	extern int mmu_huge_psize;
f4c82d51	170
3c726f8d	171	#endif /* CONFIG_HUGETLB_PAGE */
f4c82d51	172
3c726f8d BH	173	/*
	174	* This function sets the AVPN and L fields of the HPTE appropriately
	175	* for the page size
	176	*/
	177	static inline unsigned long hpte_encode_v(unsigned long va, int psize)
	178	{
	179	unsigned long v =
	180	v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
	181	v <<= HPTE_V_AVPN_SHIFT;
	182	if (psize != MMU_PAGE_4K)
	183	v \|= HPTE_V_LARGE;
	184	return v;
	185	}
f4c82d51	186
3c726f8d BH	187	/*
	188	* This function sets the ARPN, and LP fields of the HPTE appropriately
	189	* for the page size. We assume the pa is already "clean" that is properly
	190	* aligned for the requested page size
	191	*/
	192	static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
	193	{
	194	unsigned long r;
f4c82d51	195
3c726f8d BH	196	/* A 4K page needs no special encoding */
	197	if (psize == MMU_PAGE_4K)
	198	return pa & HPTE_R_RPN;
	199	else {
	200	unsigned int penc = mmu_psize_defs[psize].penc;
	201	unsigned int shift = mmu_psize_defs[psize].shift;
	202	return (pa & ~((1ul << shift) - 1)) \| (penc << 12);
f4c82d51	203	}
3c726f8d	204	return r;
f4c82d51 S	205	}
f4c82d51 S	206
1da177e4	207	/*
3c726f8d	208	* This hashes a virtual address for a 256Mb segment only for now
1da177e4	209	*/
3c726f8d BH	210
	211	static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
	212	{
	213	return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
	214	}
	215
	216	extern int __hash_page_4K(unsigned long ea, unsigned long access,
	217	unsigned long vsid, pte_t *ptep, unsigned long trap,
	218	unsigned int local);
	219	extern int __hash_page_64K(unsigned long ea, unsigned long access,
	220	unsigned long vsid, pte_t *ptep, unsigned long trap,
	221	unsigned int local);
	222	struct mm_struct;
	223	extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
cbf52afd DG	224	unsigned long ea, unsigned long vsid, int local,
cbf52afd DG	225	unsigned long trap);
1da177e4 LT	226
1da177e4 LT	227	extern void htab_finish_init(void);
3c726f8d BH	228	extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
	229	unsigned long pstart, unsigned long mode,
	230	int psize);
1da177e4	231
799d6046 PM	232	extern void htab_initialize(void);
799d6046 PM	233	extern void htab_initialize_secondary(void);
1f8d419e DG	234	extern void hpte_init_native(void);
	235	extern void hpte_init_lpar(void);
	236	extern void hpte_init_iSeries(void);
49b09853	237	extern void mm_init_ppc64(void);
1f8d419e DG	238
	239	extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
	240	unsigned long va, unsigned long prpn,
3c726f8d BH	241	unsigned long rflags,
	242	unsigned long vflags, int psize);
	243
	244	extern long native_hpte_insert(unsigned long hpte_group,
	245	unsigned long va, unsigned long prpn,
	246	unsigned long rflags,
	247	unsigned long vflags, int psize);
1f8d419e	248
3c726f8d BH	249	extern long iSeries_hpte_insert(unsigned long hpte_group,
	250	unsigned long va, unsigned long prpn,
	251	unsigned long rflags,
	252	unsigned long vflags, int psize);
4c55130b	253
533f0817	254	extern void stabs_alloc(void);
3c726f8d	255	extern void slb_initialize(void);
799d6046	256	extern void stab_initialize(unsigned long stab);
533f0817	257
1da177e4 LT	258	#endif /* __ASSEMBLY__ */
	259
	260	/*
1f8d419e DG	261	* VSID allocation
	262	*
	263	* We first generate a 36-bit "proto-VSID". For kernel addresses this
	264	* is equal to the ESID, for user addresses it is:
	265	* (context << 15) \| (esid & 0x7fff)
	266	*
	267	* The two forms are distinguishable because the top bit is 0 for user
	268	* addresses, whereas the top two bits are 1 for kernel addresses.
	269	* Proto-VSIDs with the top two bits equal to 0b10 are reserved for
	270	* now.
	271	*
	272	* The proto-VSIDs are then scrambled into real VSIDs with the
	273	* multiplicative hash:
	274	*
	275	* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
	276	* where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
	277	* VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
	278	*
	279	* This scramble is only well defined for proto-VSIDs below
	280	* 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
	281	* reserved. VSID_MULTIPLIER is prime, so in particular it is
	282	* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
	283	* Because the modulus is 2^n-1 we can compute it efficiently without
	284	* a divide or extra multiply (see below).
	285	*
	286	* This scheme has several advantages over older methods:
	287	*
	288	* - We have VSIDs allocated for every kernel address
	289	* (i.e. everything above 0xC000000000000000), except the very top
	290	* segment, which simplifies several things.
	291	*
	292	* - We allow for 15 significant bits of ESID and 20 bits of
	293	* context for user addresses. i.e. 8T (43 bits) of address space for
	294	* up to 1M contexts (although the page table structure and context
	295	* allocation will need changes to take advantage of this).
	296	*
	297	* - The scramble function gives robust scattering in the hash
	298	* table (at least based on some initial results). The previous
	299	* method was more susceptible to pathological cases giving excessive
	300	* hash collisions.
	301	*/
	302	/*
	303	* WARNING - If you change these you must make sure the asm
	304	* implementations in slb_allocate (slb_low.S), do_stab_bolted
	305	* (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
	306	*
	307	* You'll also need to change the precomputed VSID values in head.S
	308	* which are used by the iSeries firmware.
1da177e4	309	*/
1da177e4 LT	310
	311	#define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
	312	#define VSID_BITS 36
	313	#define VSID_MODULUS ((1UL<<VSID_BITS)-1)
	314
e28f7faf DG	315	#define CONTEXT_BITS 19
	316	#define USER_ESID_BITS 16
	317
	318	#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
1da177e4 LT	319
	320	/*
	321	* This macro generates asm code to compute the VSID scramble
	322	* function. Used in slb_allocate() and do_stab_bolted. The function
	323	* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
	324	*
	325	* rt = register continaing the proto-VSID and into which the
	326	* VSID will be stored
	327	* rx = scratch register (clobbered)
	328	*
	329	* - rt and rx must be different registers
	330	* - The answer will end up in the low 36 bits of rt. The higher
	331	* bits may contain other garbage, so you may need to mask the
	332	* result.
	333	*/
	334	#define ASM_VSID_SCRAMBLE(rt, rx) \
	335	lis rx,VSID_MULTIPLIER@h; \
	336	ori rx,rx,VSID_MULTIPLIER@l; \
	337	mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
	338	\
	339	srdi rx,rt,VSID_BITS; \
	340	clrldi rt,rt,(64-VSID_BITS); \
	341	add rt,rt,rx; /* add high and low bits */ \
	342	/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
	343	* 2^36-1+2^28-1. That in particular means that if r3 >= \
	344	* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
	345	* the bit clear, r3 already has the answer we want, if it \
	346	* doesn't, the answer is the low 36 bits of r3+1. So in all \
	347	* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
	348	addi rx,rt,1; \
	349	srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
	350	add rt,rt,rx
	351
1f8d419e DG	352
	353	#ifndef __ASSEMBLY__
	354
	355	typedef unsigned long mm_context_id_t;
	356
	357	typedef struct {
	358	mm_context_id_t id;
	359	#ifdef CONFIG_HUGETLB_PAGE
c594adad	360	u16 low_htlb_areas, high_htlb_areas;
1f8d419e DG	361	#endif
	362	} mm_context_t;
	363
	364
	365	static inline unsigned long vsid_scramble(unsigned long protovsid)
	366	{
	367	#if 0
	368	/* The code below is equivalent to this function for arguments
	369	* < 2^VSID_BITS, which is all this should ever be called
	370	* with. However gcc is not clever enough to compute the
	371	* modulus (2^n-1) without a second multiply. */
	372	return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
	373	#else /* 1 */
	374	unsigned long x;
	375
	376	x = protovsid * VSID_MULTIPLIER;
	377	x = (x >> VSID_BITS) + (x & VSID_MODULUS);
	378	return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
	379	#endif /* 1 */
	380	}
	381
	382	/* This is only valid for addresses >= KERNELBASE */
	383	static inline unsigned long get_kernel_vsid(unsigned long ea)
	384	{
	385	return vsid_scramble(ea >> SID_SHIFT);
	386	}
	387
	388	/* This is only valid for user addresses (which are below 2^41) */
	389	static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
	390	{
	391	return vsid_scramble((context << USER_ESID_BITS)
	392	\| (ea >> SID_SHIFT));
	393	}
	394
488f8499 DG	395	#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
	396	#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
	397
d1405b86 BH	398	/* Physical address used by some IO functions */
	399	typedef unsigned long phys_addr_t;
	400
	401
1f8d419e DG	402	#endif /* __ASSEMBLY */
1f8d419e DG	403
047ea784 PM	404	#endif /* CONFIG_PPC64 */
047ea784 PM	405	#endif /* _ASM_POWERPC_MMU_H_ */