projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 416fef1a WD |
1 | /* |
| 2 | * include/asm-ppc/cache.h | |
| 3 | */ | |
| 4 | #ifndef __ARCH_PPC_CACHE_H | |
| 5 | #define __ARCH_PPC_CACHE_H | |
| 6 | ||
| 7 | #include <linux/config.h> | |
| 8 | #include <asm/processor.h> | |
| 9 | ||
| 10 | /* bytes per L1 cache line */ | |
| 9b94ac61 | 11 | #if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480)) |
| 416fef1a | 12 | #if defined(CONFIG_PPC64BRIDGE) |
| 9b94ac61 | 13 | #define L1_CACHE_SHIFT 7 |
| 416fef1a | 14 | #else |
| 9b94ac61 | 15 | #define L1_CACHE_SHIFT 5 |
| 416fef1a WD |
16 | #endif /* PPC64 */ |
| 17 | #else | |
| 9b94ac61 SR |
18 | #define L1_CACHE_SHIFT 4 |
| 19 | #endif /* !(8xx || IOP480) */ | |
| 20 | ||
| 21 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | |
| 22 | ||
| 23 | /* | |
| 24 | * For compatibility reasons support the CFG_CACHELINE_SIZE too | |
| 25 | */ | |
| 26 | #ifndef CFG_CACHELINE_SIZE | |
| 27 | #define CFG_CACHELINE_SIZE L1_CACHE_BYTES | |
| 28 | #endif | |
| 416fef1a WD |
29 | |
| 30 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) | |
| 31 | #define L1_CACHE_PAGES 8 | |
| 32 | ||
| 33 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | |
| 34 | ||
| 35 | #ifdef MODULE | |
| 36 | #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) | |
| 37 | #else | |
| 38 | #define __cacheline_aligned \ | |
| 39 | __attribute__((__aligned__(L1_CACHE_BYTES), \ | |
| 40 | __section__(".data.cacheline_aligned"))) | |
| 41 | #endif | |
| 42 | ||
| 43 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | |
| 44 | extern void flush_dcache_range(unsigned long start, unsigned long stop); | |
| 45 | extern void clean_dcache_range(unsigned long start, unsigned long stop); | |
| 46 | extern void invalidate_dcache_range(unsigned long start, unsigned long stop); | |
| 9b94ac61 SR |
47 | extern void flush_dcache(void); |
| 48 | extern void invalidate_dcache(void); | |
| 416fef1a WD |
49 | #ifdef CFG_INIT_RAM_LOCK |
| 50 | extern void unlock_ram_in_cache(void); | |
| 51 | #endif /* CFG_INIT_RAM_LOCK */ | |
| 52 | #endif /* __ASSEMBLY__ */ | |
| 53 | ||
| 54 | /* prep registers for L2 */ | |
| 55 | #define CACHECRBA 0x80000823 /* Cache configuration register address */ | |
| 56 | #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ | |
| 57 | #define L2CACHE_512KB 0x00 /* 512KB */ | |
| 58 | #define L2CACHE_256KB 0x01 /* 256KB */ | |
| 59 | #define L2CACHE_1MB 0x02 /* 1MB */ | |
| 60 | #define L2CACHE_NONE 0x03 /* NONE */ | |
| 61 | #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ | |
| 62 | ||
| 63 | #ifdef CONFIG_8xx | |
| 64 | /* Cache control on the MPC8xx is provided through some additional | |
| 65 | * special purpose registers. | |
| 66 | */ | |
| 67 | #define IC_CST 560 /* Instruction cache control/status */ | |
| 68 | #define IC_ADR 561 /* Address needed for some commands */ | |
| 69 | #define IC_DAT 562 /* Read-only data register */ | |
| 70 | #define DC_CST 568 /* Data cache control/status */ | |
| 71 | #define DC_ADR 569 /* Address needed for some commands */ | |
| 72 | #define DC_DAT 570 /* Read-only data register */ | |
| 73 | ||
| 74 | /* Commands. Only the first few are available to the instruction cache. | |
| 75 | */ | |
| 76 | #define IDC_ENABLE 0x02000000 /* Cache enable */ | |
| 77 | #define IDC_DISABLE 0x04000000 /* Cache disable */ | |
| 78 | #define IDC_LDLCK 0x06000000 /* Load and lock */ | |
| 79 | #define IDC_UNLINE 0x08000000 /* Unlock line */ | |
| 80 | #define IDC_UNALL 0x0a000000 /* Unlock all */ | |
| 81 | #define IDC_INVALL 0x0c000000 /* Invalidate all */ | |
| 82 | ||
| 83 | #define DC_FLINE 0x0e000000 /* Flush data cache line */ | |
| 84 | #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ | |
| 85 | #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ | |
| 86 | #define DC_SLES 0x05000000 /* Set little endian swap mode */ | |
| 87 | #define DC_CLES 0x07000000 /* Clear little endian swap mode */ | |
| 88 | ||
| 89 | /* Status. | |
| 90 | */ | |
| 91 | #define IDC_ENABLED 0x80000000 /* Cache is enabled */ | |
| 92 | #define IDC_CERR1 0x00200000 /* Cache error 1 */ | |
| 93 | #define IDC_CERR2 0x00100000 /* Cache error 2 */ | |
| 94 | #define IDC_CERR3 0x00080000 /* Cache error 3 */ | |
| 95 | ||
| 96 | #define DC_DFWT 0x40000000 /* Data cache is forced write through */ | |
| 97 | #define DC_LES 0x20000000 /* Caches are little endian mode */ | |
| 98 | #endif /* CONFIG_8xx */ | |
| 99 | ||
| 100 | #endif |