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Must enable timebase earlier on MPC5200
[people/ms/u-boot.git] / include / asm-ppc / cpm_8260.h
CommitLineData
121cb96d
WD		 1
2/*
3 * MPC8260 Communication Processor Module.
4 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
5 *
6 * This file contains structures and information for the communication
7 * processor channels found in the dual port RAM or parameter RAM.
8 * All CPM control and status is available through the MPC8260 internal
9 * memory map. See immap.h for details.
10 */
11#ifndef __CPM_82XX__
12#define __CPM_82XX__
13
14#include <asm/immap_8260.h>
15
16/* CPM Command register.
17*/
18#define CPM_CR_RST ((uint)0x80000000)
19#define CPM_CR_PAGE ((uint)0x7c000000)
20#define CPM_CR_SBLOCK ((uint)0x03e00000)
21#define CPM_CR_FLG ((uint)0x00010000)
22#define CPM_CR_MCN ((uint)0x00003fc0)
23#define CPM_CR_OPCODE ((uint)0x0000000f)
24
25/* Device sub-block and page codes.
26*/
27#define CPM_CR_SCC1_SBLOCK (0x04)
28#define CPM_CR_SCC2_SBLOCK (0x05)
29#define CPM_CR_SCC3_SBLOCK (0x06)
30#define CPM_CR_SCC4_SBLOCK (0x07)
31#define CPM_CR_SMC1_SBLOCK (0x08)
32#define CPM_CR_SMC2_SBLOCK (0x09)
33#define CPM_CR_SPI_SBLOCK (0x0a)
34#define CPM_CR_I2C_SBLOCK (0x0b)
35#define CPM_CR_TIMER_SBLOCK (0x0f)
36#define CPM_CR_RAND_SBLOCK (0x0e)
37#define CPM_CR_FCC1_SBLOCK (0x10)
38#define CPM_CR_FCC2_SBLOCK (0x11)
39#define CPM_CR_FCC3_SBLOCK (0x12)
40#define CPM_CR_IDMA1_SBLOCK (0x14)
41#define CPM_CR_IDMA2_SBLOCK (0x15)
42#define CPM_CR_IDMA3_SBLOCK (0x16)
43#define CPM_CR_IDMA4_SBLOCK (0x17)
44#define CPM_CR_MCC1_SBLOCK (0x1c)
45
46#define CPM_CR_SCC1_PAGE (0x00)
47#define CPM_CR_SCC2_PAGE (0x01)
48#define CPM_CR_SCC3_PAGE (0x02)
49#define CPM_CR_SCC4_PAGE (0x03)
50#define CPM_CR_SMC1_PAGE (0x07)
51#define CPM_CR_SMC2_PAGE (0x08)
52#define CPM_CR_SPI_PAGE (0x09)
53#define CPM_CR_I2C_PAGE (0x0a)
54#define CPM_CR_TIMER_PAGE (0x0a)
55#define CPM_CR_RAND_PAGE (0x0a)
56#define CPM_CR_FCC1_PAGE (0x04)
57#define CPM_CR_FCC2_PAGE (0x05)
58#define CPM_CR_FCC3_PAGE (0x06)
59#define CPM_CR_IDMA1_PAGE (0x07)
60#define CPM_CR_IDMA2_PAGE (0x08)
61#define CPM_CR_IDMA3_PAGE (0x09)
62#define CPM_CR_IDMA4_PAGE (0x0a)
63#define CPM_CR_MCC1_PAGE (0x07)
64#define CPM_CR_MCC2_PAGE (0x08)
65
66/* Some opcodes (there are more...later)
67*/
68#define CPM_CR_INIT_TRX ((ushort)0x0000)
69#define CPM_CR_INIT_RX ((ushort)0x0001)
70#define CPM_CR_INIT_TX ((ushort)0x0002)
71#define CPM_CR_HUNT_MODE ((ushort)0x0003)
72#define CPM_CR_STOP_TX ((ushort)0x0004)
73#define CPM_CR_RESTART_TX ((ushort)0x0006)
74#define CPM_CR_SET_GADDR ((ushort)0x0008)
75
76#define mk_cr_cmd(PG, SBC, MCN, OP) \
77 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
78
79/* Dual Port RAM addresses. The first 16K is available for almost
80 * any CPM use, so we put the BDs there. The first 128 bytes are
81 * used for SMC1 and SMC2 parameter RAM, so we start allocating
82 * BDs above that. All of this must change when we start
83 * downloading RAM microcode.
84 */
85#define CPM_DATAONLY_BASE ((uint)128)
86#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
87#define CPM_DP_NOSPACE ((uint)0x7fffffff)
88#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
89
90/* The number of pages of host memory we allocate for CPM. This is
91 * done early in kernel initialization to get physically contiguous
92 * pages.
93 */
94#define NUM_CPM_HOST_PAGES 2
95
96
97/* Export the base address of the communication processor registers
98 * and dual port ram.
99 */
100extern cpm8260_t *cpmp; /* Pointer to comm processor */
101uint m8260_cpm_dpalloc(uint size, uint align);
102uint m8260_cpm_hostalloc(uint size, uint align);
103void m8260_cpm_setbrg(uint brg, uint rate);
104void m8260_cpm_fastbrg(uint brg, uint rate, int div16);
105void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
106
107/* Buffer descriptors used by many of the CPM protocols.
108*/
109typedef struct cpm_buf_desc {
110 ushort cbd_sc; /* Status and Control */
111 ushort cbd_datlen; /* Data length in buffer */
112 uint cbd_bufaddr; /* Buffer address in host memory */
113} cbd_t;
114
115#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
116#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
117#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
118#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
119#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
120#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
121#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
122#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
123#define BD_SC_BR ((ushort)0x0020) /* Break received */
124#define BD_SC_FR ((ushort)0x0010) /* Framing error */
125#define BD_SC_PR ((ushort)0x0008) /* Parity error */
126#define BD_SC_OV ((ushort)0x0002) /* Overrun */
127#define BD_SC_CD ((ushort)0x0001) /* ?? */
128
129/* Function code bits, usually generic to devices.
130*/
131#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
132#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
133#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
134#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
135#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
136
137/* Parameter RAM offsets from the base.
138*/
ea909b76 139#ifndef CFG_CPM_POST_WORD_ADDR
121cb96d 140#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
ea909b76
WD		 141#else
142#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
143#endif
121cb96d
WD		 144#define PROFF_SCC1 ((uint)0x8000)
145#define PROFF_SCC2 ((uint)0x8100)
146#define PROFF_SCC3 ((uint)0x8200)
147#define PROFF_SCC4 ((uint)0x8300)
148#define PROFF_FCC1 ((uint)0x8400)
149#define PROFF_FCC2 ((uint)0x8500)
150#define PROFF_FCC3 ((uint)0x8600)
151#define PROFF_MCC1 ((uint)0x8700)
152#define PROFF_SMC1_BASE ((uint)0x87fc)
153#define PROFF_IDMA1_BASE ((uint)0x87fe)
154#define PROFF_MCC2 ((uint)0x8800)
155#define PROFF_SMC2_BASE ((uint)0x88fc)
156#define PROFF_IDMA2_BASE ((uint)0x88fe)
157#define PROFF_SPI_BASE ((uint)0x89fc)
158#define PROFF_IDMA3_BASE ((uint)0x89fe)
159#define PROFF_TIMERS ((uint)0x8ae0)
160#define PROFF_REVNUM ((uint)0x8af0)
161#define PROFF_RAND ((uint)0x8af8)
162#define PROFF_I2C_BASE ((uint)0x8afc)
163#define PROFF_IDMA4_BASE ((uint)0x8afe)
164
165/* The SMCs are relocated to any of the first eight DPRAM pages.
166 * We will fix these at the first locations of DPRAM, until we
167 * get some microcode patches :-).
168 * The parameter ram space for the SMCs is fifty-some bytes, and
169 * they are required to start on a 64 byte boundary.
170 */
171#define PROFF_SMC1 (0)
172#define PROFF_SMC2 (64)
7aa78614 173#define PROFF_SPI ((16*1024) - 128)
121cb96d
WD		 174
175/* Define enough so I can at least use the serial port as a UART.
176 */
177typedef struct smc_uart {
178 ushort smc_rbase; /* Rx Buffer descriptor base address */
179 ushort smc_tbase; /* Tx Buffer descriptor base address */
180 u_char smc_rfcr; /* Rx function code */
181 u_char smc_tfcr; /* Tx function code */
182 ushort smc_mrblr; /* Max receive buffer length */
183 uint smc_rstate; /* Internal */
184 uint smc_idp; /* Internal */
185 ushort smc_rbptr; /* Internal */
186 ushort smc_ibc; /* Internal */
187 uint smc_rxtmp; /* Internal */
188 uint smc_tstate; /* Internal */
189 uint smc_tdp; /* Internal */
190 ushort smc_tbptr; /* Internal */
191 ushort smc_tbc; /* Internal */
192 uint smc_txtmp; /* Internal */
193 ushort smc_maxidl; /* Maximum idle characters */
194 ushort smc_tmpidl; /* Temporary idle counter */
195 ushort smc_brklen; /* Last received break length */
196 ushort smc_brkec; /* rcv'd break condition counter */
197 ushort smc_brkcr; /* xmt break count register */
198 ushort smc_rmask; /* Temporary bit mask */
199 uint smc_stmp; /* SDMA Temp */
200} smc_uart_t;
201
202/* SMC uart mode register (Internal memory map).
203*/
204#define SMCMR_REN ((ushort)0x0001)
205#define SMCMR_TEN ((ushort)0x0002)
206#define SMCMR_DM ((ushort)0x000c)
207#define SMCMR_SM_GCI ((ushort)0x0000)
208#define SMCMR_SM_UART ((ushort)0x0020)
209#define SMCMR_SM_TRANS ((ushort)0x0030)
210#define SMCMR_SM_MASK ((ushort)0x0030)
211#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
212#define SMCMR_REVD SMCMR_PM_EVEN
213#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
214#define SMCMR_BS SMCMR_PEN
215#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
216#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
217#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
218
219/* SMC Event and Mask register.
220*/
221#define SMCM_TXE ((unsigned char)0x10)
222#define SMCM_BSY ((unsigned char)0x04)
223#define SMCM_TX ((unsigned char)0x02)
224#define SMCM_RX ((unsigned char)0x01)
225
226/* Baud rate generators.
227*/
228#define CPM_BRG_RST ((uint)0x00020000)
229#define CPM_BRG_EN ((uint)0x00010000)
230#define CPM_BRG_EXTC_INT ((uint)0x00000000)
231#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
232#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
233#define CPM_BRG_ATB ((uint)0x00002000)
234#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
235#define CPM_BRG_DIV16 ((uint)0x00000001)
236
237/* SCCs.
238*/
239#define SCC_GSMRH_IRP ((uint)0x00040000)
240#define SCC_GSMRH_GDE ((uint)0x00010000)
241#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
242#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
243#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
244#define SCC_GSMRH_REVD ((uint)0x00002000)
245#define SCC_GSMRH_TRX ((uint)0x00001000)
246#define SCC_GSMRH_TTX ((uint)0x00000800)
247#define SCC_GSMRH_CDP ((uint)0x00000400)
248#define SCC_GSMRH_CTSP ((uint)0x00000200)
249#define SCC_GSMRH_CDS ((uint)0x00000100)
250#define SCC_GSMRH_CTSS ((uint)0x00000080)
251#define SCC_GSMRH_TFL ((uint)0x00000040)
252#define SCC_GSMRH_RFW ((uint)0x00000020)
253#define SCC_GSMRH_TXSY ((uint)0x00000010)
254#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
255#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
256#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
257#define SCC_GSMRH_RTSM ((uint)0x00000002)
258#define SCC_GSMRH_RSYN ((uint)0x00000001)
259
260#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
261#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
262#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
263#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
264#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
265#define SCC_GSMRL_TCI ((uint)0x10000000)
266#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
267#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
268#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
269#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
270#define SCC_GSMRL_RINV ((uint)0x02000000)
271#define SCC_GSMRL_TINV ((uint)0x01000000)
272#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
273#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
274#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
275#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
276#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
277#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
278#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
279#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
280#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
281#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
282#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
283#define SCC_GSMRL_TEND ((uint)0x00040000)
284#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
285#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
286#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
287#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
288#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
289#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
290#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
291#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
292#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
293#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
294#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
295#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
296#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
297#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
298#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
299#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
300#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
301#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
302#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
303#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
304#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
305#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
306#define SCC_GSMRL_ENR ((uint)0x00000020)
307#define SCC_GSMRL_ENT ((uint)0x00000010)
308#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
309#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
310#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
311#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
312#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
313#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
314#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
315#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
316#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
317#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
318
319#define SCC_TODR_TOD ((ushort)0x8000)
320
321/* SCC Event and Mask register.
322*/
323#define SCCM_TXE ((unsigned char)0x10)
324#define SCCM_BSY ((unsigned char)0x04)
325#define SCCM_TX ((unsigned char)0x02)
326#define SCCM_RX ((unsigned char)0x01)
327
328typedef struct scc_param {
329 ushort scc_rbase; /* Rx Buffer descriptor base address */
330 ushort scc_tbase; /* Tx Buffer descriptor base address */
331 u_char scc_rfcr; /* Rx function code */
332 u_char scc_tfcr; /* Tx function code */
333 ushort scc_mrblr; /* Max receive buffer length */
334 uint scc_rstate; /* Internal */
335 uint scc_idp; /* Internal */
336 ushort scc_rbptr; /* Internal */
337 ushort scc_ibc; /* Internal */
338 uint scc_rxtmp; /* Internal */
339 uint scc_tstate; /* Internal */
340 uint scc_tdp; /* Internal */
341 ushort scc_tbptr; /* Internal */
342 ushort scc_tbc; /* Internal */
343 uint scc_txtmp; /* Internal */
344 uint scc_rcrc; /* Internal */
345 uint scc_tcrc; /* Internal */
346} sccp_t;
347
348/* CPM Ethernet through SCC1.
349 */
350typedef struct scc_enet {
351 sccp_t sen_genscc;
352 uint sen_cpres; /* Preset CRC */
353 uint sen_cmask; /* Constant mask for CRC */
354 uint sen_crcec; /* CRC Error counter */
355 uint sen_alec; /* alignment error counter */
356 uint sen_disfc; /* discard frame counter */
357 ushort sen_pads; /* Tx short frame pad character */
358 ushort sen_retlim; /* Retry limit threshold */
359 ushort sen_retcnt; /* Retry limit counter */
360 ushort sen_maxflr; /* maximum frame length register */
361 ushort sen_minflr; /* minimum frame length register */
362 ushort sen_maxd1; /* maximum DMA1 length */
363 ushort sen_maxd2; /* maximum DMA2 length */
364 ushort sen_maxd; /* Rx max DMA */
365 ushort sen_dmacnt; /* Rx DMA counter */
366 ushort sen_maxb; /* Max BD byte count */
367 ushort sen_gaddr1; /* Group address filter */
368 ushort sen_gaddr2;
369 ushort sen_gaddr3;
370 ushort sen_gaddr4;
371 uint sen_tbuf0data0; /* Save area 0 - current frame */
372 uint sen_tbuf0data1; /* Save area 1 - current frame */
373 uint sen_tbuf0rba; /* Internal */
374 uint sen_tbuf0crc; /* Internal */
375 ushort sen_tbuf0bcnt; /* Internal */
376 ushort sen_paddrh; /* physical address (MSB) */
377 ushort sen_paddrm;
378 ushort sen_paddrl; /* physical address (LSB) */
379 ushort sen_pper; /* persistence */
380 ushort sen_rfbdptr; /* Rx first BD pointer */
381 ushort sen_tfbdptr; /* Tx first BD pointer */
382 ushort sen_tlbdptr; /* Tx last BD pointer */
383 uint sen_tbuf1data0; /* Save area 0 - current frame */
384 uint sen_tbuf1data1; /* Save area 1 - current frame */
385 uint sen_tbuf1rba; /* Internal */
386 uint sen_tbuf1crc; /* Internal */
387 ushort sen_tbuf1bcnt; /* Internal */
388 ushort sen_txlen; /* Tx Frame length counter */
389 ushort sen_iaddr1; /* Individual address filter */
390 ushort sen_iaddr2;
391 ushort sen_iaddr3;
392 ushort sen_iaddr4;
393 ushort sen_boffcnt; /* Backoff counter */
394
395 /* NOTE: Some versions of the manual have the following items
396 * incorrectly documented. Below is the proper order.
397 */
398 ushort sen_taddrh; /* temp address (MSB) */
399 ushort sen_taddrm;
400 ushort sen_taddrl; /* temp address (LSB) */
401} scc_enet_t;
402
403
404/* SCC Event register as used by Ethernet.
405*/
406#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
407#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
408#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
409#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
410#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
411#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
412
413/* SCC Mode Register (PSMR) as used by Ethernet.
414*/
415#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
416#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
417#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
418#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
419#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
420#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
421#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
422#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
423#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
424#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
425#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
426#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
427#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
428
429/* Buffer descriptor control/status used by Ethernet receive.
430 * Common to SCC and FCC.
431 */
432#define BD_ENET_RX_EMPTY ((ushort)0x8000)
433#define BD_ENET_RX_WRAP ((ushort)0x2000)
434#define BD_ENET_RX_INTR ((ushort)0x1000)
435#define BD_ENET_RX_LAST ((ushort)0x0800)
436#define BD_ENET_RX_FIRST ((ushort)0x0400)
437#define BD_ENET_RX_MISS ((ushort)0x0100)
438#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
439#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
440#define BD_ENET_RX_LG ((ushort)0x0020)
441#define BD_ENET_RX_NO ((ushort)0x0010)
442#define BD_ENET_RX_SH ((ushort)0x0008)
443#define BD_ENET_RX_CR ((ushort)0x0004)
444#define BD_ENET_RX_OV ((ushort)0x0002)
445#define BD_ENET_RX_CL ((ushort)0x0001)
446#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
447
448/* Buffer descriptor control/status used by Ethernet transmit.
449 * Common to SCC and FCC.
450 */
451#define BD_ENET_TX_READY ((ushort)0x8000)
452#define BD_ENET_TX_PAD ((ushort)0x4000)
453#define BD_ENET_TX_WRAP ((ushort)0x2000)
454#define BD_ENET_TX_INTR ((ushort)0x1000)
455#define BD_ENET_TX_LAST ((ushort)0x0800)
456#define BD_ENET_TX_TC ((ushort)0x0400)
457#define BD_ENET_TX_DEF ((ushort)0x0200)
458#define BD_ENET_TX_HB ((ushort)0x0100)
459#define BD_ENET_TX_LC ((ushort)0x0080)
460#define BD_ENET_TX_RL ((ushort)0x0040)
461#define BD_ENET_TX_RCMASK ((ushort)0x003c)
462#define BD_ENET_TX_UN ((ushort)0x0002)
463#define BD_ENET_TX_CSL ((ushort)0x0001)
464#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
465
466/* SCC as UART
467*/
468typedef struct scc_uart {
469 sccp_t scc_genscc;
470 uint scc_res1; /* Reserved */
471 uint scc_res2; /* Reserved */
472 ushort scc_maxidl; /* Maximum idle chars */
473 ushort scc_idlc; /* temp idle counter */
474 ushort scc_brkcr; /* Break count register */
475 ushort scc_parec; /* receive parity error counter */
476 ushort scc_frmec; /* receive framing error counter */
477 ushort scc_nosec; /* receive noise counter */
478 ushort scc_brkec; /* receive break condition counter */
479 ushort scc_brkln; /* last received break length */
480 ushort scc_uaddr1; /* UART address character 1 */
481 ushort scc_uaddr2; /* UART address character 2 */
482 ushort scc_rtemp; /* Temp storage */
483 ushort scc_toseq; /* Transmit out of sequence char */
484 ushort scc_char1; /* control character 1 */
485 ushort scc_char2; /* control character 2 */
486 ushort scc_char3; /* control character 3 */
487 ushort scc_char4; /* control character 4 */
488 ushort scc_char5; /* control character 5 */
489 ushort scc_char6; /* control character 6 */
490 ushort scc_char7; /* control character 7 */
491 ushort scc_char8; /* control character 8 */
492 ushort scc_rccm; /* receive control character mask */
493 ushort scc_rccr; /* receive control character register */
494 ushort scc_rlbc; /* receive last break character */
495} scc_uart_t;
496
497/* SCC Event and Mask registers when it is used as a UART.
498*/
499#define UART_SCCM_GLR ((ushort)0x1000)
500#define UART_SCCM_GLT ((ushort)0x0800)
501#define UART_SCCM_AB ((ushort)0x0200)
502#define UART_SCCM_IDL ((ushort)0x0100)
503#define UART_SCCM_GRA ((ushort)0x0080)
504#define UART_SCCM_BRKE ((ushort)0x0040)
505#define UART_SCCM_BRKS ((ushort)0x0020)
506#define UART_SCCM_CCR ((ushort)0x0008)
507#define UART_SCCM_BSY ((ushort)0x0004)
508#define UART_SCCM_TX ((ushort)0x0002)
509#define UART_SCCM_RX ((ushort)0x0001)
510
511/* The SCC PSMR when used as a UART.
512*/
513#define SCU_PSMR_FLC ((ushort)0x8000)
514#define SCU_PSMR_SL ((ushort)0x4000)
515#define SCU_PSMR_CL ((ushort)0x3000)
516#define SCU_PSMR_UM ((ushort)0x0c00)
517#define SCU_PSMR_FRZ ((ushort)0x0200)
518#define SCU_PSMR_RZS ((ushort)0x0100)
519#define SCU_PSMR_SYN ((ushort)0x0080)
520#define SCU_PSMR_DRT ((ushort)0x0040)
521#define SCU_PSMR_PEN ((ushort)0x0010)
522#define SCU_PSMR_RPM ((ushort)0x000c)
523#define SCU_PSMR_REVP ((ushort)0x0008)
524#define SCU_PSMR_TPM ((ushort)0x0003)
525#define SCU_PSMR_TEVP ((ushort)0x0003)
526
527/* CPM Transparent mode SCC.
528 */
529typedef struct scc_trans {
530 sccp_t st_genscc;
531 uint st_cpres; /* Preset CRC */
532 uint st_cmask; /* Constant mask for CRC */
533} scc_trans_t;
534
535#define BD_SCC_TX_LAST ((ushort)0x0800)
536
537/* How about some FCCs.....
538*/
539#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
540#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
541#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
542#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
543#define FCC_GFMR_TCI ((uint)0x20000000)
544#define FCC_GFMR_TRX ((uint)0x10000000)
545#define FCC_GFMR_TTX ((uint)0x08000000)
546#define FCC_GFMR_TTX ((uint)0x08000000)
547#define FCC_GFMR_CDP ((uint)0x04000000)
548#define FCC_GFMR_CTSP ((uint)0x02000000)
549#define FCC_GFMR_CDS ((uint)0x01000000)
550#define FCC_GFMR_CTSS ((uint)0x00800000)
551#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
552#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
553#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
554#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
555#define FCC_GFMR_RTSM ((uint)0x00002000)
556#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
557#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
558#define FCC_GFMR_REVD ((uint)0x00000400)
559#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
560#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
561#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
562#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
563#define FCC_GFMR_ENR ((uint)0x00000020)
564#define FCC_GFMR_ENT ((uint)0x00000010)
565#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
566#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
567#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
568
569/* Generic FCC parameter ram.
570*/
571typedef struct fcc_param {
572 ushort fcc_riptr; /* Rx Internal temp pointer */
573 ushort fcc_tiptr; /* Tx Internal temp pointer */
574 ushort fcc_res1;
575 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
576 uint fcc_rstate; /* Upper byte is Func code, must be set */
577 uint fcc_rbase; /* Receive BD base */
578 ushort fcc_rbdstat; /* RxBD status */
579 ushort fcc_rbdlen; /* RxBD down counter */
580 uint fcc_rdptr; /* RxBD internal data pointer */
581 uint fcc_tstate; /* Upper byte is Func code, must be set */
582 uint fcc_tbase; /* Transmit BD base */
583 ushort fcc_tbdstat; /* TxBD status */
584 ushort fcc_tbdlen; /* TxBD down counter */
585 uint fcc_tdptr; /* TxBD internal data pointer */
586 uint fcc_rbptr; /* Rx BD Internal buf pointer */
587 uint fcc_tbptr; /* Tx BD Internal buf pointer */
588 uint fcc_rcrc; /* Rx temp CRC */
589 uint fcc_res2;
590 uint fcc_tcrc; /* Tx temp CRC */
591} fccp_t;
592
593
594/* Ethernet controller through FCC.
595*/
596typedef struct fcc_enet {
597 fccp_t fen_genfcc;
598 uint fen_statbuf; /* Internal status buffer */
599 uint fen_camptr; /* CAM address */
600 uint fen_cmask; /* Constant mask for CRC */
601 uint fen_cpres; /* Preset CRC */
602 uint fen_crcec; /* CRC Error counter */
603 uint fen_alec; /* alignment error counter */
604 uint fen_disfc; /* discard frame counter */
605 ushort fen_retlim; /* Retry limit */
606 ushort fen_retcnt; /* Retry counter */
607 ushort fen_pper; /* Persistence */
608 ushort fen_boffcnt; /* backoff counter */
609 uint fen_gaddrh; /* Group address filter, high 32-bits */
610 uint fen_gaddrl; /* Group address filter, low 32-bits */
611 ushort fen_tfcstat; /* out of sequence TxBD */
612 ushort fen_tfclen;
613 uint fen_tfcptr;
614 ushort fen_mflr; /* Maximum frame length (1518) */
615 ushort fen_paddrh; /* MAC address */
616 ushort fen_paddrm;
617 ushort fen_paddrl;
618 ushort fen_ibdcount; /* Internal BD counter */
619 ushort fen_idbstart; /* Internal BD start pointer */
620 ushort fen_ibdend; /* Internal BD end pointer */
621 ushort fen_txlen; /* Internal Tx frame length counter */
622 uint fen_ibdbase[8]; /* Internal use */
623 uint fen_iaddrh; /* Individual address filter */
624 uint fen_iaddrl;
625 ushort fen_minflr; /* Minimum frame length (64) */
626 ushort fen_taddrh; /* Filter transfer MAC address */
627 ushort fen_taddrm;
628 ushort fen_taddrl;
629 ushort fen_padptr; /* Pointer to pad byte buffer */
630 ushort fen_cftype; /* control frame type */
631 ushort fen_cfrange; /* control frame range */
632 ushort fen_maxb; /* maximum BD count */
633 ushort fen_maxd1; /* Max DMA1 length (1520) */
634 ushort fen_maxd2; /* Max DMA2 length (1520) */
635 ushort fen_maxd; /* internal max DMA count */
636 ushort fen_dmacnt; /* internal DMA counter */
637 uint fen_octc; /* Total octect counter */
638 uint fen_colc; /* Total collision counter */
639 uint fen_broc; /* Total broadcast packet counter */
640 uint fen_mulc; /* Total multicast packet count */
641 uint fen_uspc; /* Total packets < 64 bytes */
642 uint fen_frgc; /* Total packets < 64 bytes with errors */
643 uint fen_ospc; /* Total packets > 1518 */
644 uint fen_jbrc; /* Total packets > 1518 with errors */
645 uint fen_p64c; /* Total packets == 64 bytes */
646 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
647 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
648 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
649 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
650 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
651 uint fen_cambuf; /* Internal CAM buffer poiner */
652 ushort fen_rfthr; /* Received frames threshold */
653 ushort fen_rfcnt; /* Received frames count */
654} fcc_enet_t;
655
656/* FCC Event/Mask register as used by Ethernet.
657*/
658#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
659#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
660#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
661#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
662#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
663#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
664#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
665#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
666
667/* FCC Mode Register (FPSMR) as used by Ethernet.
668*/
669#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
670#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
671#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
672#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
673#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
674#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
675#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
676#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
677#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
678#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
679#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
680#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
681#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
682
683/* IIC parameter RAM.
684*/
685typedef struct iic {
686 ushort iic_rbase; /* Rx Buffer descriptor base address */
687 ushort iic_tbase; /* Tx Buffer descriptor base address */
688 u_char iic_rfcr; /* Rx function code */
689 u_char iic_tfcr; /* Tx function code */
690 ushort iic_mrblr; /* Max receive buffer length */
691 uint iic_rstate; /* Internal */
692 uint iic_rdp; /* Internal */
693 ushort iic_rbptr; /* Internal */
694 ushort iic_rbc; /* Internal */
695 uint iic_rxtmp; /* Internal */
696 uint iic_tstate; /* Internal */
697 uint iic_tdp; /* Internal */
698 ushort iic_tbptr; /* Internal */
699 ushort iic_tbc; /* Internal */
700 uint iic_txtmp; /* Internal */
701} iic_t;
702
703/* SPI parameter RAM.
704*/
705typedef struct spi {
706 ushort spi_rbase; /* Rx Buffer descriptor base address */
707 ushort spi_tbase; /* Tx Buffer descriptor base address */
708 u_char spi_rfcr; /* Rx function code */
709 u_char spi_tfcr; /* Tx function code */
710 ushort spi_mrblr; /* Max receive buffer length */
711 uint spi_rstate; /* Internal */
712 uint spi_rdp; /* Internal */
713 ushort spi_rbptr; /* Internal */
714 ushort spi_rbc; /* Internal */
715 uint spi_rxtmp; /* Internal */
716 uint spi_tstate; /* Internal */
717 uint spi_tdp; /* Internal */
718 ushort spi_tbptr; /* Internal */
719 ushort spi_tbc; /* Internal */
720 uint spi_txtmp; /* Internal */
721 uint spi_res; /* Tx temp. */
722 uint spi_res1[4]; /* SDMA temp. */
723} spi_t;
724
725/* SPI Mode register.
726*/
727#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
728#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
729#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
730#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
731#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
732#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
733#define SPMODE_EN ((ushort)0x0100) /* Enable */
734#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
735#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
736
737#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
738#define SPMODE_PM(x) ((x) &0xF)
739
7aa78614
WD		 740/* SPI Event/Mask register.
741*/
742#define SPI_EMASK 0x37 /* Event Mask */
743#define SPI_MME 0x20 /* Multi-Master Error */
744#define SPI_TXE 0x10 /* Transmit Error */
745#define SPI_BSY 0x04 /* Busy */
746#define SPI_TXB 0x02 /* Tx Buffer Empty */
747#define SPI_RXB 0x01 /* RX Buffer full/closed */
748
749#define SPI_STR 0x80 /* SPCOM: Start transmit */
750
121cb96d
WD		 751#define SPI_EB ((u_char)0x10) /* big endian byte order */
752
753#define BD_IIC_START ((ushort)0x0400)
754
755#endif /* __CPM_82XX__ */
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