projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 58e5e9af KG |
1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License | |
| 6 | * Version 2 as published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef DDR2_DIMM_PARAMS_H | |
| 10 | #define DDR2_DIMM_PARAMS_H | |
| 11 | ||
| 12 | /* Parameters for a DDR2 dimm computed from the SPD */ | |
| 13 | typedef struct dimm_params_s { | |
| 14 | ||
| 15 | /* DIMM organization parameters */ | |
| 16 | char mpart[19]; /* guaranteed null terminated */ | |
| 17 | ||
| 18 | unsigned int n_ranks; | |
| 19 | unsigned long long rank_density; | |
| 20 | unsigned long long capacity; | |
| 21 | unsigned int data_width; | |
| 22 | unsigned int primary_sdram_width; | |
| 23 | unsigned int ec_sdram_width; | |
| 24 | unsigned int registered_dimm; | |
| 25 | ||
| 26 | /* SDRAM device parameters */ | |
| 27 | unsigned int n_row_addr; | |
| 28 | unsigned int n_col_addr; | |
| 29 | unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ | |
| 30 | unsigned int n_banks_per_sdram_device; | |
| 31 | unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ | |
| 32 | unsigned int row_density; | |
| 33 | ||
| 34 | /* used in computing base address of DIMMs */ | |
| 35 | unsigned long long base_address; | |
| 36 | ||
| 37 | /* DIMM timing parameters */ | |
| 38 | ||
| 39 | /* | |
| 40 | * SDRAM clock periods | |
| 41 | * The range for these are 1000-10000 so a short should be sufficient | |
| 42 | */ | |
| 43 | unsigned int tCKmin_X_ps; | |
| 44 | unsigned int tCKmin_X_minus_1_ps; | |
| 45 | unsigned int tCKmin_X_minus_2_ps; | |
| 46 | unsigned int tCKmax_ps; | |
| 47 | ||
| 48 | /* SPD-defined CAS latencies */ | |
| 49 | unsigned int caslat_X; | |
| 50 | unsigned int caslat_X_minus_1; | |
| 51 | unsigned int caslat_X_minus_2; | |
| 52 | ||
| 53 | unsigned int caslat_lowest_derated; /* Derated CAS latency */ | |
| 54 | ||
| 55 | /* basic timing parameters */ | |
| 56 | unsigned int tRCD_ps; | |
| 57 | unsigned int tRP_ps; | |
| 58 | unsigned int tRAS_ps; | |
| 59 | ||
| 60 | unsigned int tWR_ps; /* maximum = 63750 ps */ | |
| 61 | unsigned int tWTR_ps; /* maximum = 63750 ps */ | |
| 62 | unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns | |
| 63 | = 511750 ps */ | |
| 64 | ||
| 65 | unsigned int tRRD_ps; /* maximum = 63750 ps */ | |
| 66 | unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ | |
| 67 | ||
| 68 | unsigned int refresh_rate_ps; | |
| 69 | ||
| 70 | unsigned int tIS_ps; /* byte 32, spd->ca_setup */ | |
| 71 | unsigned int tIH_ps; /* byte 33, spd->ca_hold */ | |
| 72 | unsigned int tDS_ps; /* byte 34, spd->data_setup */ | |
| 73 | unsigned int tDH_ps; /* byte 35, spd->data_hold */ | |
| 74 | unsigned int tRTP_ps; /* byte 38, spd->trtp */ | |
| 75 | unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ | |
| 76 | unsigned int tQHS_ps; /* byte 45, spd->tqhs */ | |
| 77 | } dimm_params_t; | |
| 78 | ||
| 79 | extern unsigned int ddr_compute_dimm_parameters( | |
| 80 | const generic_spd_eeprom_t *spd, | |
| 81 | dimm_params_t *pdimm, | |
| 82 | unsigned int dimm_number); | |
| 83 | ||
| 84 | #endif |