]>
Commit | Line | Data |
---|---|---|
58e5e9af KG |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef FSL_DDR_MEMCTL_H | |
10 | #define FSL_DDR_MEMCTL_H | |
11 | ||
12 | /* | |
13 | * Pick a basic DDR Technology. | |
14 | */ | |
15 | #include <ddr_spd.h> | |
16 | ||
17 | #define SDRAM_TYPE_DDR1 2 | |
18 | #define SDRAM_TYPE_DDR2 3 | |
19 | #define SDRAM_TYPE_LPDDR1 6 | |
20 | #define SDRAM_TYPE_DDR3 7 | |
21 | ||
22 | #if defined(CONFIG_FSL_DDR1) | |
23 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) | |
24 | typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; | |
25 | #ifndef CONFIG_FSL_SDRAM_TYPE | |
26 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 | |
27 | #endif | |
28 | #elif defined(CONFIG_FSL_DDR2) | |
29 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) | |
30 | typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; | |
31 | #ifndef CONFIG_FSL_SDRAM_TYPE | |
32 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 | |
33 | #endif | |
34 | #elif defined(CONFIG_FSL_DDR3) | |
35 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ | |
36 | typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; | |
37 | #endif | |
38 | ||
39 | /* Record of register values computed */ | |
40 | typedef struct fsl_ddr_cfg_regs_s { | |
41 | struct { | |
42 | unsigned int bnds; | |
43 | unsigned int config; | |
44 | unsigned int config_2; | |
45 | } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; | |
46 | unsigned int timing_cfg_3; | |
47 | unsigned int timing_cfg_0; | |
48 | unsigned int timing_cfg_1; | |
49 | unsigned int timing_cfg_2; | |
50 | unsigned int ddr_sdram_cfg; | |
51 | unsigned int ddr_sdram_cfg_2; | |
52 | unsigned int ddr_sdram_mode; | |
53 | unsigned int ddr_sdram_mode_2; | |
54 | unsigned int ddr_sdram_md_cntl; | |
55 | unsigned int ddr_sdram_interval; | |
56 | unsigned int ddr_data_init; | |
57 | unsigned int ddr_sdram_clk_cntl; | |
58 | unsigned int ddr_init_addr; | |
59 | unsigned int ddr_init_ext_addr; | |
60 | unsigned int timing_cfg_4; | |
61 | unsigned int timing_cfg_5; | |
62 | unsigned int ddr_zq_cntl; | |
63 | unsigned int ddr_wrlvl_cntl; | |
64 | unsigned int ddr_pd_cntl; | |
65 | unsigned int ddr_sr_cntr; | |
66 | unsigned int ddr_sdram_rcw_1; | |
67 | unsigned int ddr_sdram_rcw_2; | |
68 | } fsl_ddr_cfg_regs_t; | |
69 | ||
70 | typedef struct memctl_options_partial_s { | |
71 | unsigned int all_DIMMs_ECC_capable; | |
72 | unsigned int all_DIMMs_tCKmax_ps; | |
73 | unsigned int all_DIMMs_burst_lengths_bitmask; | |
74 | unsigned int all_DIMMs_registered; | |
75 | unsigned int all_DIMMs_unbuffered; | |
76 | /* unsigned int lowest_common_SPD_caslat; */ | |
77 | unsigned int all_DIMMs_minimum_tRCD_ps; | |
78 | } memctl_options_partial_t; | |
79 | ||
80 | /* | |
81 | * Generalized parameters for memory controller configuration, | |
82 | * might be a little specific to the FSL memory controller | |
83 | */ | |
84 | typedef struct memctl_options_s { | |
85 | /* | |
86 | * Memory organization parameters | |
87 | * | |
88 | * if DIMM is present in the system | |
89 | * where DIMMs are with respect to chip select | |
90 | * where chip selects are with respect to memory boundaries | |
91 | */ | |
92 | unsigned int registered_dimm_en; /* use registered DIMM support */ | |
93 | ||
94 | /* Options local to a Chip Select */ | |
95 | struct cs_local_opts_s { | |
96 | unsigned int auto_precharge; | |
97 | unsigned int odt_rd_cfg; | |
98 | unsigned int odt_wr_cfg; | |
99 | } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; | |
100 | ||
101 | /* Special configurations for chip select */ | |
102 | unsigned int memctl_interleaving; | |
103 | unsigned int memctl_interleaving_mode; | |
104 | unsigned int ba_intlv_ctl; | |
105 | ||
106 | /* Operational mode parameters */ | |
107 | unsigned int ECC_mode; /* Use ECC? */ | |
108 | /* Initialize ECC using memory controller? */ | |
109 | unsigned int ECC_init_using_memctl; | |
110 | unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ | |
111 | /* SREN - self-refresh during sleep */ | |
112 | unsigned int self_refresh_in_sleep; | |
113 | unsigned int dynamic_power; /* DYN_PWR */ | |
114 | /* memory data width to use (16-bit, 32-bit, 64-bit) */ | |
115 | unsigned int data_bus_width; | |
116 | unsigned int burst_length; /* 4, 8 */ | |
117 | ||
118 | /* Global Timing Parameters */ | |
119 | unsigned int cas_latency_override; | |
120 | unsigned int cas_latency_override_value; | |
121 | unsigned int use_derated_caslat; | |
122 | unsigned int additive_latency_override; | |
123 | unsigned int additive_latency_override_value; | |
124 | ||
125 | unsigned int clk_adjust; /* */ | |
126 | unsigned int cpo_override; | |
127 | unsigned int write_data_delay; /* DQS adjust */ | |
128 | unsigned int half_strength_driver_enable; | |
129 | unsigned int twoT_en; | |
130 | unsigned int threeT_en; | |
131 | unsigned int bstopre; | |
132 | unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ | |
133 | unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ | |
134 | } memctl_options_t; | |
135 | ||
136 | extern phys_size_t fsl_ddr_sdram(void); | |
137 | #endif |