[people/ms/u-boot.git] / include / asm-ppc / fsl_ddr_sdram.h

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 */

#ifndef FSL_DDR_MEMCTL_H
#define FSL_DDR_MEMCTL_H

/*
 * Pick a basic DDR Technology.
 */
#include <ddr_spd.h>

#define SDRAM_TYPE_DDR1    2
#define SDRAM_TYPE_DDR2    3
#define SDRAM_TYPE_LPDDR1  6
#define SDRAM_TYPE_DDR3    7

#if defined(CONFIG_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
#endif
#elif defined(CONFIG_FSL_DDR2)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
#endif
#elif defined(CONFIG_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
#endif
#endif	/* #if defined(CONFIG_FSL_DDR1) */

/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1			0x40
#define FSL_DDR_CS2_CS3			0x20
#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)

/* define memory controller interleaving mode */
#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
#define FSL_DDR_PAGE_INTERLEAVING	0x1
#define FSL_DDR_BANK_INTERLEAVING	0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3

/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
 */
#define SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG_SREN			0x40000000
#define SDRAM_CFG_ECC_EN		0x20000000
#define SDRAM_CFG_RD_EN			0x10000000
#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
#define SDRAM_CFG_DYN_PWR		0x00200000
#define SDRAM_CFG_32_BE			0x00080000
#define SDRAM_CFG_8_BE			0x00040000
#define SDRAM_CFG_NCAP			0x00020000
#define SDRAM_CFG_2T_EN			0x00008000
#define SDRAM_CFG_BI			0x00000001

/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
	struct {
		unsigned int bnds;
		unsigned int config;
		unsigned int config_2;
	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	unsigned int timing_cfg_3;
	unsigned int timing_cfg_0;
	unsigned int timing_cfg_1;
	unsigned int timing_cfg_2;
	unsigned int ddr_sdram_cfg;
	unsigned int ddr_sdram_cfg_2;
	unsigned int ddr_sdram_mode;
	unsigned int ddr_sdram_mode_2;
	unsigned int ddr_sdram_md_cntl;
	unsigned int ddr_sdram_interval;
	unsigned int ddr_data_init;
	unsigned int ddr_sdram_clk_cntl;
	unsigned int ddr_init_addr;
	unsigned int ddr_init_ext_addr;
	unsigned int timing_cfg_4;
	unsigned int timing_cfg_5;
	unsigned int ddr_zq_cntl;
	unsigned int ddr_wrlvl_cntl;
	unsigned int ddr_pd_cntl;
	unsigned int ddr_sr_cntr;
	unsigned int ddr_sdram_rcw_1;
	unsigned int ddr_sdram_rcw_2;
} fsl_ddr_cfg_regs_t;

typedef struct memctl_options_partial_s {
	unsigned int all_DIMMs_ECC_capable;
	unsigned int all_DIMMs_tCKmax_ps;
	unsigned int all_DIMMs_burst_lengths_bitmask;
	unsigned int all_DIMMs_registered;
	unsigned int all_DIMMs_unbuffered;
	/*	unsigned int lowest_common_SPD_caslat; */
	unsigned int all_DIMMs_minimum_tRCD_ps;
} memctl_options_partial_t;

/*
 * Generalized parameters for memory controller configuration,
 * might be a little specific to the FSL memory controller
 */
typedef struct memctl_options_s {
	/*
	 * Memory organization parameters
	 *
	 * if DIMM is present in the system
	 * where DIMMs are with respect to chip select
	 * where chip selects are with respect to memory boundaries
	 */
	unsigned int registered_dimm_en;    /* use registered DIMM support */

	/* Options local to a Chip Select */
	struct cs_local_opts_s {
		unsigned int auto_precharge;
		unsigned int odt_rd_cfg;
		unsigned int odt_wr_cfg;
	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];

	/* Special configurations for chip select */
	unsigned int memctl_interleaving;
	unsigned int memctl_interleaving_mode;
	unsigned int ba_intlv_ctl;

	/* Operational mode parameters */
	unsigned int ECC_mode;	 /* Use ECC? */
	/* Initialize ECC using memory controller? */
	unsigned int ECC_init_using_memctl;
	unsigned int DQS_config;	/* Use DQS? maybe only with DDR2? */
	/* SREN - self-refresh during sleep */
	unsigned int self_refresh_in_sleep;
	unsigned int dynamic_power;	/* DYN_PWR */
	/* memory data width to use (16-bit, 32-bit, 64-bit) */
	unsigned int data_bus_width;
	unsigned int burst_length;	/* 4, 8 */

	/* Global Timing Parameters */
	unsigned int cas_latency_override;
	unsigned int cas_latency_override_value;
	unsigned int use_derated_caslat;
	unsigned int additive_latency_override;
	unsigned int additive_latency_override_value;

	unsigned int clk_adjust;		/* */
	unsigned int cpo_override;
	unsigned int write_data_delay;		/* DQS adjust */
	unsigned int half_strength_driver_enable;
	unsigned int twoT_en;
	unsigned int threeT_en;
	unsigned int bstopre;
	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */

	/* Automatic self refresh */
	unsigned int auto_self_refresh_en;
	unsigned int sr_it;
} memctl_options_t;

extern phys_size_t fsl_ddr_sdram(void);
#endif
Commit	Line	Data
58e5e9af KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* Version 2 as published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef FSL_DDR_MEMCTL_H
	10	#define FSL_DDR_MEMCTL_H
	11
	12	/*
	13	* Pick a basic DDR Technology.
	14	*/
	15	#include <ddr_spd.h>
	16
	17	#define SDRAM_TYPE_DDR1 2
	18	#define SDRAM_TYPE_DDR2 3
	19	#define SDRAM_TYPE_LPDDR1 6
	20	#define SDRAM_TYPE_DDR3 7
	21
	22	#if defined(CONFIG_FSL_DDR1)
	23	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
	24	typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
	25	#ifndef CONFIG_FSL_SDRAM_TYPE
	26	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
	27	#endif
	28	#elif defined(CONFIG_FSL_DDR2)
	29	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
	30	typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
	31	#ifndef CONFIG_FSL_SDRAM_TYPE
	32	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
	33	#endif
	34	#elif defined(CONFIG_FSL_DDR3)
	35	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
	36	typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
22ff3d01 DL	37	#ifndef CONFIG_FSL_SDRAM_TYPE
22ff3d01 DL	38	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
58e5e9af	39	#endif
22ff3d01	40	#endif /* #if defined(CONFIG_FSL_DDR1) */
58e5e9af	41
dbbbb3ab HW	42	/* define bank(chip select) interleaving mode */
	43	#define FSL_DDR_CS0_CS1 0x40
	44	#define FSL_DDR_CS2_CS3 0x20
	45	#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 \| FSL_DDR_CS2_CS3)
	46	#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 \| 0x04)
	47
	48	/* define memory controller interleaving mode */
	49	#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
	50	#define FSL_DDR_PAGE_INTERLEAVING 0x1
	51	#define FSL_DDR_BANK_INTERLEAVING 0x2
	52	#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
	53
e1be0d25 P	54	/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
	55	*/
	56	#define SDRAM_CFG_MEM_EN 0x80000000
	57	#define SDRAM_CFG_SREN 0x40000000
	58	#define SDRAM_CFG_ECC_EN 0x20000000
	59	#define SDRAM_CFG_RD_EN 0x10000000
	60	#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
	61	#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
	62	#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
	63	#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
	64	#define SDRAM_CFG_DYN_PWR 0x00200000
	65	#define SDRAM_CFG_32_BE 0x00080000
	66	#define SDRAM_CFG_8_BE 0x00040000
	67	#define SDRAM_CFG_NCAP 0x00020000
	68	#define SDRAM_CFG_2T_EN 0x00008000
	69	#define SDRAM_CFG_BI 0x00000001
	70
58e5e9af KG	71	/* Record of register values computed */
	72	typedef struct fsl_ddr_cfg_regs_s {
	73	struct {
	74	unsigned int bnds;
	75	unsigned int config;
	76	unsigned int config_2;
	77	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	78	unsigned int timing_cfg_3;
	79	unsigned int timing_cfg_0;
	80	unsigned int timing_cfg_1;
	81	unsigned int timing_cfg_2;
	82	unsigned int ddr_sdram_cfg;
	83	unsigned int ddr_sdram_cfg_2;
	84	unsigned int ddr_sdram_mode;
	85	unsigned int ddr_sdram_mode_2;
	86	unsigned int ddr_sdram_md_cntl;
	87	unsigned int ddr_sdram_interval;
	88	unsigned int ddr_data_init;
	89	unsigned int ddr_sdram_clk_cntl;
	90	unsigned int ddr_init_addr;
	91	unsigned int ddr_init_ext_addr;
	92	unsigned int timing_cfg_4;
	93	unsigned int timing_cfg_5;
	94	unsigned int ddr_zq_cntl;
	95	unsigned int ddr_wrlvl_cntl;
	96	unsigned int ddr_pd_cntl;
	97	unsigned int ddr_sr_cntr;
	98	unsigned int ddr_sdram_rcw_1;
	99	unsigned int ddr_sdram_rcw_2;
	100	} fsl_ddr_cfg_regs_t;
	101
	102	typedef struct memctl_options_partial_s {
	103	unsigned int all_DIMMs_ECC_capable;
	104	unsigned int all_DIMMs_tCKmax_ps;
	105	unsigned int all_DIMMs_burst_lengths_bitmask;
	106	unsigned int all_DIMMs_registered;
	107	unsigned int all_DIMMs_unbuffered;
	108	/* unsigned int lowest_common_SPD_caslat; */
	109	unsigned int all_DIMMs_minimum_tRCD_ps;
	110	} memctl_options_partial_t;
	111
	112	/*
	113	* Generalized parameters for memory controller configuration,
	114	* might be a little specific to the FSL memory controller
	115	*/
	116	typedef struct memctl_options_s {
	117	/*
	118	* Memory organization parameters
	119	*
	120	* if DIMM is present in the system
	121	* where DIMMs are with respect to chip select
	122	* where chip selects are with respect to memory boundaries
	123	*/
	124	unsigned int registered_dimm_en; /* use registered DIMM support */
	125
	126	/* Options local to a Chip Select */
	127	struct cs_local_opts_s {
	128	unsigned int auto_precharge;
	129	unsigned int odt_rd_cfg;
	130	unsigned int odt_wr_cfg;
	131	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
	132
	133	/* Special configurations for chip select */
	134	unsigned int memctl_interleaving;
135	unsigned int memctl_interleaving_mode;
136	unsigned int ba_intlv_ctl;
137
138	/* Operational mode parameters */
139	unsigned int ECC_mode; /* Use ECC? */
140	/* Initialize ECC using memory controller? */
141	unsigned int ECC_init_using_memctl;
142	unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
143	/* SREN - self-refresh during sleep */
144	unsigned int self_refresh_in_sleep;
145	unsigned int dynamic_power; /* DYN_PWR */
146	/* memory data width to use (16-bit, 32-bit, 64-bit) */
147	unsigned int data_bus_width;
148	unsigned int burst_length; /* 4, 8 */
149
150	/* Global Timing Parameters */
151	unsigned int cas_latency_override;
152	unsigned int cas_latency_override_value;
153	unsigned int use_derated_caslat;
154	unsigned int additive_latency_override;
155	unsigned int additive_latency_override_value;
156
157	unsigned int clk_adjust; /* */
158	unsigned int cpo_override;
159	unsigned int write_data_delay; /* DQS adjust */
160	unsigned int half_strength_driver_enable;
161	unsigned int twoT_en;
162	unsigned int threeT_en;
163	unsigned int bstopre;
164	unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
165	unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
22cca7e1 DL	166
	167	/* Automatic self refresh */
	168	unsigned int auto_self_refresh_en;
	169	unsigned int sr_it;
58e5e9af KG	170	} memctl_options_t;
	171
	172	extern phys_size_t fsl_ddr_sdram(void);
	173	#endif