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23892e49 DL |
1 | /* |
2 | * QUICC Engine (QE) Internal Memory Map. | |
3 | * The Internal Memory Map for devices with QE on them. This | |
4 | * is the superset of all QE devices (8360, etc.). | |
5 | * | |
4e7b25e4 | 6 | * Copyright (c) 2006-2009 Freescale Semiconductor, Inc. |
23892e49 DL |
7 | * Author: Shlomi Gridih <gridish@freescale.com> |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
15 | #ifndef __IMMAP_QE_H__ | |
16 | #define __IMMAP_QE_H__ | |
17 | ||
18 | /* QE I-RAM | |
19 | */ | |
20 | typedef struct qe_iram { | |
21 | u32 iadd; /* I-RAM Address Register */ | |
22 | u32 idata; /* I-RAM Data Register */ | |
22b6dbc1 HW |
23 | u8 res0[0x4]; |
24 | u32 iready; | |
25 | u8 res1[0x70]; | |
23892e49 DL |
26 | } __attribute__ ((packed)) qe_iram_t; |
27 | ||
28 | /* QE Interrupt Controller | |
29 | */ | |
30 | typedef struct qe_ic { | |
31 | u32 qicr; | |
32 | u32 qivec; | |
33 | u32 qripnr; | |
34 | u32 qipnr; | |
35 | u32 qipxcc; | |
36 | u32 qipycc; | |
37 | u32 qipwcc; | |
38 | u32 qipzcc; | |
39 | u32 qimr; | |
40 | u32 qrimr; | |
41 | u32 qicnr; | |
42 | u8 res0[0x4]; | |
43 | u32 qiprta; | |
44 | u32 qiprtb; | |
45 | u8 res1[0x4]; | |
46 | u32 qricr; | |
47 | u8 res2[0x20]; | |
48 | u32 qhivec; | |
49 | u8 res3[0x1C]; | |
50 | } __attribute__ ((packed)) qe_ic_t; | |
51 | ||
52 | /* Communications Processor | |
53 | */ | |
54 | typedef struct cp_qe { | |
55 | u32 cecr; /* QE command register */ | |
56 | u32 ceccr; /* QE controller configuration register */ | |
57 | u32 cecdr; /* QE command data register */ | |
58 | u8 res0[0xA]; | |
59 | u16 ceter; /* QE timer event register */ | |
60 | u8 res1[0x2]; | |
61 | u16 cetmr; /* QE timers mask register */ | |
62 | u32 cetscr; /* QE time-stamp timer control register */ | |
63 | u32 cetsr1; /* QE time-stamp register 1 */ | |
64 | u32 cetsr2; /* QE time-stamp register 2 */ | |
65 | u8 res2[0x8]; | |
66 | u32 cevter; /* QE virtual tasks event register */ | |
67 | u32 cevtmr; /* QE virtual tasks mask register */ | |
68 | u16 cercr; /* QE RAM control register */ | |
69 | u8 res3[0x2]; | |
70 | u8 res4[0x24]; | |
71 | u16 ceexe1; /* QE external request 1 event register */ | |
72 | u8 res5[0x2]; | |
73 | u16 ceexm1; /* QE external request 1 mask register */ | |
74 | u8 res6[0x2]; | |
75 | u16 ceexe2; /* QE external request 2 event register */ | |
76 | u8 res7[0x2]; | |
77 | u16 ceexm2; /* QE external request 2 mask register */ | |
78 | u8 res8[0x2]; | |
79 | u16 ceexe3; /* QE external request 3 event register */ | |
80 | u8 res9[0x2]; | |
81 | u16 ceexm3; /* QE external request 3 mask register */ | |
82 | u8 res10[0x2]; | |
83 | u16 ceexe4; /* QE external request 4 event register */ | |
84 | u8 res11[0x2]; | |
85 | u16 ceexm4; /* QE external request 4 mask register */ | |
86 | u8 res12[0x2]; | |
87 | u8 res13[0x280]; | |
88 | } __attribute__ ((packed)) cp_qe_t; | |
89 | ||
90 | /* QE Multiplexer | |
91 | */ | |
92 | typedef struct qe_mux { | |
93 | u32 cmxgcr; /* CMX general clock route register */ | |
94 | u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ | |
95 | u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ | |
96 | u32 cmxsi1syr; /* CMX SI1 SYNC route register */ | |
97 | u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ | |
98 | u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ | |
99 | u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ | |
100 | u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ | |
101 | u32 cmxupcr; /* CMX UPC clock route register */ | |
102 | u8 res0[0x1C]; | |
103 | } __attribute__ ((packed)) qe_mux_t; | |
104 | ||
105 | /* QE Timers | |
106 | */ | |
107 | typedef struct qe_timers { | |
108 | u8 gtcfr1; /* Timer 1 2 global configuration register */ | |
109 | u8 res0[0x3]; | |
110 | u8 gtcfr2; /* Timer 3 4 global configuration register */ | |
111 | u8 res1[0xB]; | |
112 | u16 gtmdr1; /* Timer 1 mode register */ | |
113 | u16 gtmdr2; /* Timer 2 mode register */ | |
114 | u16 gtrfr1; /* Timer 1 reference register */ | |
115 | u16 gtrfr2; /* Timer 2 reference register */ | |
116 | u16 gtcpr1; /* Timer 1 capture register */ | |
117 | u16 gtcpr2; /* Timer 2 capture register */ | |
118 | u16 gtcnr1; /* Timer 1 counter */ | |
119 | u16 gtcnr2; /* Timer 2 counter */ | |
120 | u16 gtmdr3; /* Timer 3 mode register */ | |
121 | u16 gtmdr4; /* Timer 4 mode register */ | |
122 | u16 gtrfr3; /* Timer 3 reference register */ | |
123 | u16 gtrfr4; /* Timer 4 reference register */ | |
124 | u16 gtcpr3; /* Timer 3 capture register */ | |
125 | u16 gtcpr4; /* Timer 4 capture register */ | |
126 | u16 gtcnr3; /* Timer 3 counter */ | |
127 | u16 gtcnr4; /* Timer 4 counter */ | |
128 | u16 gtevr1; /* Timer 1 event register */ | |
129 | u16 gtevr2; /* Timer 2 event register */ | |
130 | u16 gtevr3; /* Timer 3 event register */ | |
131 | u16 gtevr4; /* Timer 4 event register */ | |
132 | u16 gtps; /* Timer 1 prescale register */ | |
133 | u8 res2[0x46]; | |
134 | } __attribute__ ((packed)) qe_timers_t; | |
135 | ||
136 | /* BRG | |
137 | */ | |
138 | typedef struct qe_brg { | |
139 | u32 brgc1; /* BRG1 configuration register */ | |
140 | u32 brgc2; /* BRG2 configuration register */ | |
141 | u32 brgc3; /* BRG3 configuration register */ | |
142 | u32 brgc4; /* BRG4 configuration register */ | |
143 | u32 brgc5; /* BRG5 configuration register */ | |
144 | u32 brgc6; /* BRG6 configuration register */ | |
145 | u32 brgc7; /* BRG7 configuration register */ | |
146 | u32 brgc8; /* BRG8 configuration register */ | |
147 | u32 brgc9; /* BRG9 configuration register */ | |
148 | u32 brgc10; /* BRG10 configuration register */ | |
149 | u32 brgc11; /* BRG11 configuration register */ | |
150 | u32 brgc12; /* BRG12 configuration register */ | |
151 | u32 brgc13; /* BRG13 configuration register */ | |
152 | u32 brgc14; /* BRG14 configuration register */ | |
153 | u32 brgc15; /* BRG15 configuration register */ | |
154 | u32 brgc16; /* BRG16 configuration register */ | |
155 | u8 res0[0x40]; | |
156 | } __attribute__ ((packed)) qe_brg_t; | |
157 | ||
158 | /* SPI | |
159 | */ | |
160 | typedef struct spi { | |
161 | u8 res0[0x20]; | |
162 | u32 spmode; /* SPI mode register */ | |
163 | u8 res1[0x2]; | |
164 | u8 spie; /* SPI event register */ | |
165 | u8 res2[0x1]; | |
166 | u8 res3[0x2]; | |
167 | u8 spim; /* SPI mask register */ | |
168 | u8 res4[0x1]; | |
169 | u8 res5[0x1]; | |
170 | u8 spcom; /* SPI command register */ | |
171 | u8 res6[0x2]; | |
172 | u32 spitd; /* SPI transmit data register (cpu mode) */ | |
173 | u32 spird; /* SPI receive data register (cpu mode) */ | |
174 | u8 res7[0x8]; | |
175 | } __attribute__ ((packed)) spi_t; | |
176 | ||
177 | /* SI | |
178 | */ | |
179 | typedef struct si1 { | |
180 | u16 siamr1; /* SI1 TDMA mode register */ | |
181 | u16 sibmr1; /* SI1 TDMB mode register */ | |
182 | u16 sicmr1; /* SI1 TDMC mode register */ | |
183 | u16 sidmr1; /* SI1 TDMD mode register */ | |
184 | u8 siglmr1_h; /* SI1 global mode register high */ | |
185 | u8 res0[0x1]; | |
186 | u8 sicmdr1_h; /* SI1 command register high */ | |
187 | u8 res2[0x1]; | |
188 | u8 sistr1_h; /* SI1 status register high */ | |
189 | u8 res3[0x1]; | |
190 | u16 sirsr1_h; /* SI1 RAM shadow address register high */ | |
191 | u8 sitarc1; /* SI1 RAM counter Tx TDMA */ | |
192 | u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ | |
193 | u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ | |
194 | u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ | |
195 | u8 sirarc1; /* SI1 RAM counter Rx TDMA */ | |
196 | u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ | |
197 | u8 sircrc1; /* SI1 RAM counter Rx TDMC */ | |
198 | u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ | |
199 | u8 res4[0x8]; | |
200 | u16 siemr1; /* SI1 TDME mode register 16 bits */ | |
201 | u16 sifmr1; /* SI1 TDMF mode register 16 bits */ | |
202 | u16 sigmr1; /* SI1 TDMG mode register 16 bits */ | |
203 | u16 sihmr1; /* SI1 TDMH mode register 16 bits */ | |
204 | u8 siglmg1_l; /* SI1 global mode register low 8 bits */ | |
205 | u8 res5[0x1]; | |
206 | u8 sicmdr1_l; /* SI1 command register low 8 bits */ | |
207 | u8 res6[0x1]; | |
208 | u8 sistr1_l; /* SI1 status register low 8 bits */ | |
209 | u8 res7[0x1]; | |
210 | u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ | |
211 | u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ | |
212 | u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ | |
213 | u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ | |
214 | u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ | |
215 | u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ | |
216 | u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ | |
217 | u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ | |
218 | u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ | |
219 | u8 res8[0x8]; | |
220 | u32 siml1; /* SI1 multiframe limit register */ | |
221 | u8 siedm1; /* SI1 extended diagnostic mode register */ | |
222 | u8 res9[0xBB]; | |
223 | } __attribute__ ((packed)) si1_t; | |
224 | ||
225 | /* SI Routing Tables | |
226 | */ | |
227 | typedef struct sir { | |
228 | u8 tx[0x400]; | |
229 | u8 rx[0x400]; | |
230 | u8 res0[0x800]; | |
231 | } __attribute__ ((packed)) sir_t; | |
232 | ||
233 | /* USB Controller. | |
234 | */ | |
235 | typedef struct usb_ctlr { | |
236 | u8 usb_usmod; | |
237 | u8 usb_usadr; | |
238 | u8 usb_uscom; | |
239 | u8 res1[1]; | |
240 | u16 usb_usep1; | |
241 | u16 usb_usep2; | |
242 | u16 usb_usep3; | |
243 | u16 usb_usep4; | |
244 | u8 res2[4]; | |
245 | u16 usb_usber; | |
246 | u8 res3[2]; | |
247 | u16 usb_usbmr; | |
248 | u8 res4[1]; | |
249 | u8 usb_usbs; | |
250 | u16 usb_ussft; | |
251 | u8 res5[2]; | |
252 | u16 usb_usfrn; | |
253 | u8 res6[0x22]; | |
254 | } __attribute__ ((packed)) usb_t; | |
255 | ||
256 | /* MCC | |
257 | */ | |
258 | typedef struct mcc { | |
259 | u32 mcce; /* MCC event register */ | |
260 | u32 mccm; /* MCC mask register */ | |
261 | u32 mccf; /* MCC configuration register */ | |
262 | u32 merl; /* MCC emergency request level register */ | |
263 | u8 res0[0xF0]; | |
264 | } __attribute__ ((packed)) mcc_t; | |
265 | ||
266 | /* QE UCC Slow | |
267 | */ | |
268 | typedef struct ucc_slow { | |
269 | u32 gumr_l; /* UCCx general mode register (low) */ | |
270 | u32 gumr_h; /* UCCx general mode register (high) */ | |
271 | u16 upsmr; /* UCCx protocol-specific mode register */ | |
272 | u8 res0[0x2]; | |
273 | u16 utodr; /* UCCx transmit on demand register */ | |
274 | u16 udsr; /* UCCx data synchronization register */ | |
275 | u16 ucce; /* UCCx event register */ | |
276 | u8 res1[0x2]; | |
277 | u16 uccm; /* UCCx mask register */ | |
278 | u8 res2[0x1]; | |
279 | u8 uccs; /* UCCx status register */ | |
280 | u8 res3[0x24]; | |
281 | u16 utpt; | |
282 | u8 guemr; /* UCC general extended mode register */ | |
283 | u8 res4[0x200 - 0x091]; | |
284 | } __attribute__ ((packed)) ucc_slow_t; | |
285 | ||
da9d4610 AF |
286 | typedef struct ucc_mii_mng { |
287 | u32 miimcfg; /* MII management configuration reg */ | |
288 | u32 miimcom; /* MII management command reg */ | |
289 | u32 miimadd; /* MII management address reg */ | |
290 | u32 miimcon; /* MII management control reg */ | |
291 | u32 miimstat; /* MII management status reg */ | |
292 | u32 miimind; /* MII management indication reg */ | |
293 | u32 ifctl; /* interface control reg */ | |
294 | u32 ifstat; /* interface statux reg */ | |
295 | } __attribute__ ((packed))uec_mii_t; | |
296 | ||
23892e49 DL |
297 | typedef struct ucc_ethernet { |
298 | u32 maccfg1; /* mac configuration reg. 1 */ | |
299 | u32 maccfg2; /* mac configuration reg. 2 */ | |
300 | u32 ipgifg; /* interframe gap reg. */ | |
301 | u32 hafdup; /* half-duplex reg. */ | |
302 | u8 res1[0x10]; | |
303 | u32 miimcfg; /* MII management configuration reg */ | |
304 | u32 miimcom; /* MII management command reg */ | |
305 | u32 miimadd; /* MII management address reg */ | |
306 | u32 miimcon; /* MII management control reg */ | |
307 | u32 miimstat; /* MII management status reg */ | |
308 | u32 miimind; /* MII management indication reg */ | |
309 | u32 ifctl; /* interface control reg */ | |
310 | u32 ifstat; /* interface statux reg */ | |
311 | u32 macstnaddr1; /* mac station address part 1 reg */ | |
312 | u32 macstnaddr2; /* mac station address part 2 reg */ | |
313 | u8 res2[0x8]; | |
314 | u32 uempr; /* UCC Ethernet Mac parameter reg */ | |
315 | u32 utbipar; /* UCC tbi address reg */ | |
316 | u16 uescr; /* UCC Ethernet statistics control reg */ | |
317 | u8 res3[0x180 - 0x15A]; | |
318 | u32 tx64; /* Total number of frames (including bad | |
319 | * frames) transmitted that were exactly | |
320 | * of the minimal length (64 for un tagged, | |
321 | * 68 for tagged, or with length exactly | |
322 | * equal to the parameter MINLength */ | |
323 | u32 tx127; /* Total number of frames (including bad | |
324 | * frames) transmitted that were between | |
325 | * MINLength (Including FCS length==4) | |
326 | * and 127 octets */ | |
327 | u32 tx255; /* Total number of frames (including bad | |
328 | * frames) transmitted that were between | |
329 | * 128 (Including FCS length==4) and 255 | |
330 | * octets */ | |
331 | u32 rx64; /* Total number of frames received including | |
332 | * bad frames that were exactly of the | |
333 | * mninimal length (64 bytes) */ | |
334 | u32 rx127; /* Total number of frames (including bad | |
335 | * frames) received that were between | |
336 | * MINLength (Including FCS length==4) | |
337 | * and 127 octets */ | |
338 | u32 rx255; /* Total number of frames (including | |
339 | * bad frames) received that were between | |
340 | * 128 (Including FCS length==4) and 255 | |
341 | * octets */ | |
342 | u32 txok; /* Total number of octets residing in frames | |
343 | * that where involved in succesfull | |
344 | * transmission */ | |
345 | u16 txcf; /* Total number of PAUSE control frames | |
346 | * transmitted by this MAC */ | |
347 | u8 res4[0x2]; | |
348 | u32 tmca; /* Total number of frames that were transmitted | |
349 | * succesfully with the group address bit set | |
350 | * that are not broadcast frames */ | |
351 | u32 tbca; /* Total number of frames transmitted | |
352 | * succesfully that had destination address | |
353 | * field equal to the broadcast address */ | |
354 | u32 rxfok; /* Total number of frames received OK */ | |
355 | u32 rxbok; /* Total number of octets received OK */ | |
356 | u32 rbyt; /* Total number of octets received including | |
357 | * octets in bad frames. Must be implemented | |
358 | * in HW because it includes octets in frames | |
359 | * that never even reach the UCC */ | |
360 | u32 rmca; /* Total number of frames that were received | |
361 | * succesfully with the group address bit set | |
362 | * that are not broadcast frames */ | |
363 | u32 rbca; /* Total number of frames received succesfully | |
364 | * that had destination address equal to the | |
365 | * broadcast address */ | |
366 | u32 scar; /* Statistics carry register */ | |
367 | u32 scam; /* Statistics caryy mask register */ | |
368 | u8 res5[0x200 - 0x1c4]; | |
369 | } __attribute__ ((packed)) uec_t; | |
370 | ||
371 | /* QE UCC Fast | |
372 | */ | |
373 | typedef struct ucc_fast { | |
374 | u32 gumr; /* UCCx general mode register */ | |
375 | u32 upsmr; /* UCCx protocol-specific mode register */ | |
376 | u16 utodr; /* UCCx transmit on demand register */ | |
377 | u8 res0[0x2]; | |
378 | u16 udsr; /* UCCx data synchronization register */ | |
379 | u8 res1[0x2]; | |
380 | u32 ucce; /* UCCx event register */ | |
381 | u32 uccm; /* UCCx mask register. */ | |
382 | u8 uccs; /* UCCx status register */ | |
383 | u8 res2[0x7]; | |
384 | u32 urfb; /* UCC receive FIFO base */ | |
385 | u16 urfs; /* UCC receive FIFO size */ | |
386 | u8 res3[0x2]; | |
387 | u16 urfet; /* UCC receive FIFO emergency threshold */ | |
388 | u16 urfset; /* UCC receive FIFO special emergency | |
389 | * threshold */ | |
390 | u32 utfb; /* UCC transmit FIFO base */ | |
391 | u16 utfs; /* UCC transmit FIFO size */ | |
392 | u8 res4[0x2]; | |
393 | u16 utfet; /* UCC transmit FIFO emergency threshold */ | |
394 | u8 res5[0x2]; | |
395 | u16 utftt; /* UCC transmit FIFO transmit threshold */ | |
396 | u8 res6[0x2]; | |
397 | u16 utpt; /* UCC transmit polling timer */ | |
398 | u8 res7[0x2]; | |
399 | u32 urtry; /* UCC retry counter register */ | |
400 | u8 res8[0x4C]; | |
401 | u8 guemr; /* UCC general extended mode register */ | |
402 | u8 res9[0x100 - 0x091]; | |
403 | uec_t ucc_eth; | |
404 | } __attribute__ ((packed)) ucc_fast_t; | |
405 | ||
406 | /* QE UCC | |
407 | */ | |
408 | typedef struct ucc_common { | |
409 | u8 res1[0x90]; | |
410 | u8 guemr; | |
411 | u8 res2[0x200 - 0x091]; | |
412 | } __attribute__ ((packed)) ucc_common_t; | |
413 | ||
414 | typedef struct ucc { | |
415 | union { | |
416 | ucc_slow_t slow; | |
417 | ucc_fast_t fast; | |
418 | ucc_common_t common; | |
419 | }; | |
420 | } __attribute__ ((packed)) ucc_t; | |
421 | ||
422 | /* MultiPHY UTOPIA POS Controllers (UPC) | |
423 | */ | |
424 | typedef struct upc { | |
425 | u32 upgcr; /* UTOPIA/POS general configuration register */ | |
426 | u32 uplpa; /* UTOPIA/POS last PHY address */ | |
427 | u32 uphec; /* ATM HEC register */ | |
428 | u32 upuc; /* UTOPIA/POS UCC configuration */ | |
429 | u32 updc1; /* UTOPIA/POS device 1 configuration */ | |
430 | u32 updc2; /* UTOPIA/POS device 2 configuration */ | |
431 | u32 updc3; /* UTOPIA/POS device 3 configuration */ | |
432 | u32 updc4; /* UTOPIA/POS device 4 configuration */ | |
433 | u32 upstpa; /* UTOPIA/POS STPA threshold */ | |
434 | u8 res0[0xC]; | |
435 | u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ | |
436 | u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ | |
437 | u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ | |
438 | u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ | |
439 | u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ | |
440 | u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ | |
441 | u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ | |
442 | u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ | |
443 | u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ | |
444 | u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ | |
445 | u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ | |
446 | u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ | |
447 | u32 upde1; /* UTOPIA/POS device 1 event */ | |
448 | u32 upde2; /* UTOPIA/POS device 2 event */ | |
449 | u32 upde3; /* UTOPIA/POS device 3 event */ | |
450 | u32 upde4; /* UTOPIA/POS device 4 event */ | |
451 | u16 uprp1; | |
452 | u16 uprp2; | |
453 | u16 uprp3; | |
454 | u16 uprp4; | |
455 | u8 res1[0x8]; | |
456 | u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ | |
457 | u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ | |
458 | u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ | |
459 | u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ | |
460 | u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ | |
461 | u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ | |
462 | u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ | |
463 | u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ | |
464 | u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ | |
465 | u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ | |
466 | u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ | |
467 | u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ | |
468 | u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ | |
469 | u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ | |
470 | u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ | |
471 | u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ | |
472 | u32 uper1; /* Device 1 port enable register */ | |
473 | u32 uper2; /* Device 2 port enable register */ | |
474 | u32 uper3; /* Device 3 port enable register */ | |
475 | u32 uper4; /* Device 4 port enable register */ | |
476 | u8 res2[0x150]; | |
477 | } __attribute__ ((packed)) upc_t; | |
478 | ||
479 | /* SDMA | |
480 | */ | |
481 | typedef struct sdma { | |
482 | u32 sdsr; /* Serial DMA status register */ | |
483 | u32 sdmr; /* Serial DMA mode register */ | |
484 | u32 sdtr1; /* SDMA system bus threshold register */ | |
485 | u32 sdtr2; /* SDMA secondary bus threshold register */ | |
486 | u32 sdhy1; /* SDMA system bus hysteresis register */ | |
487 | u32 sdhy2; /* SDMA secondary bus hysteresis register */ | |
488 | u32 sdta1; /* SDMA system bus address register */ | |
489 | u32 sdta2; /* SDMA secondary bus address register */ | |
490 | u32 sdtm1; /* SDMA system bus MSNUM register */ | |
491 | u32 sdtm2; /* SDMA secondary bus MSNUM register */ | |
492 | u8 res0[0x10]; | |
493 | u32 sdaqr; /* SDMA address bus qualify register */ | |
494 | u32 sdaqmr; /* SDMA address bus qualify mask register */ | |
495 | u8 res1[0x4]; | |
496 | u32 sdwbcr; /* SDMA CAM entries base register */ | |
497 | u8 res2[0x38]; | |
498 | } __attribute__ ((packed)) sdma_t; | |
499 | ||
500 | /* Debug Space | |
501 | */ | |
502 | typedef struct dbg { | |
503 | u32 bpdcr; /* Breakpoint debug command register */ | |
504 | u32 bpdsr; /* Breakpoint debug status register */ | |
505 | u32 bpdmr; /* Breakpoint debug mask register */ | |
506 | u32 bprmrr0; /* Breakpoint request mode risc register 0 */ | |
507 | u32 bprmrr1; /* Breakpoint request mode risc register 1 */ | |
508 | u8 res0[0x8]; | |
509 | u32 bprmtr0; /* Breakpoint request mode trb register 0 */ | |
510 | u32 bprmtr1; /* Breakpoint request mode trb register 1 */ | |
511 | u8 res1[0x8]; | |
512 | u32 bprmir; /* Breakpoint request mode immediate register */ | |
513 | u32 bprmsr; /* Breakpoint request mode serial register */ | |
514 | u32 bpemr; /* Breakpoint exit mode register */ | |
515 | u8 res2[0x48]; | |
516 | } __attribute__ ((packed)) dbg_t; | |
517 | ||
b8ec2385 TT |
518 | /* |
519 | * RISC Special Registers (Trap and Breakpoint). These are described in | |
520 | * the QE Developer's Handbook. | |
23892e49 DL |
521 | */ |
522 | typedef struct rsp { | |
b8ec2385 TT |
523 | u32 tibcr[16]; /* Trap/instruction breakpoint control regs */ |
524 | u8 res0[64]; | |
525 | u32 ibcr0; | |
526 | u32 ibs0; | |
527 | u32 ibcnr0; | |
528 | u8 res1[4]; | |
529 | u32 ibcr1; | |
530 | u32 ibs1; | |
531 | u32 ibcnr1; | |
532 | u32 npcr; | |
533 | u32 dbcr; | |
534 | u32 dbar; | |
535 | u32 dbamr; | |
536 | u32 dbsr; | |
537 | u32 dbcnr; | |
538 | u8 res2[12]; | |
539 | u32 dbdr_h; | |
540 | u32 dbdr_l; | |
541 | u32 dbdmr_h; | |
542 | u32 dbdmr_l; | |
543 | u32 bsr; | |
544 | u32 bor; | |
545 | u32 bior; | |
546 | u8 res3[4]; | |
547 | u32 iatr[4]; | |
548 | u32 eccr; /* Exception control configuration register */ | |
549 | u32 eicr; | |
550 | u8 res4[0x100-0xf8]; | |
23892e49 DL |
551 | } __attribute__ ((packed)) rsp_t; |
552 | ||
553 | typedef struct qe_immap { | |
554 | qe_iram_t iram; /* I-RAM */ | |
555 | qe_ic_t ic; /* Interrupt Controller */ | |
556 | cp_qe_t cp; /* Communications Processor */ | |
557 | qe_mux_t qmx; /* QE Multiplexer */ | |
558 | qe_timers_t qet; /* QE Timers */ | |
559 | spi_t spi[0x2]; /* spi */ | |
560 | mcc_t mcc; /* mcc */ | |
561 | qe_brg_t brg; /* brg */ | |
562 | usb_t usb; /* USB */ | |
563 | si1_t si1; /* SI */ | |
564 | u8 res11[0x800]; | |
565 | sir_t sir; /* SI Routing Tables */ | |
566 | ucc_t ucc1; /* ucc1 */ | |
567 | ucc_t ucc3; /* ucc3 */ | |
568 | ucc_t ucc5; /* ucc5 */ | |
569 | ucc_t ucc7; /* ucc7 */ | |
570 | u8 res12[0x600]; | |
571 | upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ | |
572 | ucc_t ucc2; /* ucc2 */ | |
573 | ucc_t ucc4; /* ucc4 */ | |
574 | ucc_t ucc6; /* ucc6 */ | |
575 | ucc_t ucc8; /* ucc8 */ | |
576 | u8 res13[0x600]; | |
577 | upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ | |
578 | sdma_t sdma; /* SDMA */ | |
579 | dbg_t dbg; /* Debug Space */ | |
580 | rsp_t rsp[0x2]; /* RISC Special Registers | |
581 | * (Trap and Breakpoint) */ | |
582 | u8 res14[0x300]; | |
583 | u8 res15[0x3A00]; | |
584 | u8 res16[0x8000]; /* 0x108000 - 0x110000 */ | |
c7f60fd2 | 585 | #if defined(CONFIG_MPC8568) |
da9d4610 AF |
586 | u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ |
587 | u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ | |
c7f60fd2 HW |
588 | #elif defined(CONFIG_MPC8569) |
589 | u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */ | |
590 | u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */ | |
da9d4610 | 591 | #else |
23892e49 DL |
592 | u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ |
593 | u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ | |
594 | u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ | |
da9d4610 | 595 | #endif |
23892e49 DL |
596 | } __attribute__ ((packed)) qe_map_t; |
597 | ||
598 | extern qe_map_t *qe_immr; | |
599 | ||
c7f60fd2 | 600 | #if defined(CONFIG_MPC8568) |
da9d4610 | 601 | #define QE_MURAM_SIZE 0x10000UL |
c7f60fd2 HW |
602 | #elif defined(CONFIG_MPC8569) |
603 | #define QE_MURAM_SIZE 0x20000UL | |
da9d4610 | 604 | #elif defined(CONFIG_MPC8360) |
24c3aca3 | 605 | #define QE_MURAM_SIZE 0xc000UL |
2c7920af | 606 | #elif defined(CONFIG_MPC832x) |
24c3aca3 DL |
607 | #define QE_MURAM_SIZE 0x4000UL |
608 | #endif | |
609 | ||
7211fbfa HW |
610 | #if defined(CONFIG_MPC8323) |
611 | #define MAX_QE_RISC 1 | |
4e7b25e4 | 612 | #define QE_NUM_OF_SNUM 28 |
7211fbfa HW |
613 | #elif defined(CONFIG_MPC8569) |
614 | #define MAX_QE_RISC 4 | |
4e7b25e4 | 615 | #define QE_NUM_OF_SNUM 46 |
7211fbfa HW |
616 | #else |
617 | #define MAX_QE_RISC 2 | |
4e7b25e4 | 618 | #define QE_NUM_OF_SNUM 28 |
7211fbfa HW |
619 | #endif |
620 | ||
23892e49 | 621 | #endif /* __IMMAP_QE_H__ */ |