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Patch by Tom Guilliams, 20 Jun 2003:
[people/ms/u-boot.git] / include / asm-ppc / processor.h
CommitLineData
935ecca1
WD		 1#ifndef __ASM_PPC_PROCESSOR_H
2#define __ASM_PPC_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <linux/config.h>
11
12#include <asm/ptrace.h>
13#include <asm/types.h>
14
15/* Machine State Register (MSR) Fields */
16
17#ifdef CONFIG_PPC64BRIDGE
18#define MSR_SF (1<<63)
19#define MSR_ISF (1<<61)
20#endif /* CONFIG_PPC64BRIDGE */
21#define MSR_VEC (1<<25) /* Enable AltiVec */
22#define MSR_POW (1<<18) /* Enable Power Management */
23#define MSR_WE (1<<18) /* Wait State Enable */
24#define MSR_TGPR (1<<17) /* TLB Update registers in use */
25#define MSR_CE (1<<17) /* Critical Interrupt Enable */
26#define MSR_ILE (1<<16) /* Interrupt Little Endian */
27#define MSR_EE (1<<15) /* External Interrupt Enable */
28#define MSR_PR (1<<14) /* Problem State / Privilege Level */
29#define MSR_FP (1<<13) /* Floating Point enable */
30#define MSR_ME (1<<12) /* Machine Check Enable */
31#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
32#define MSR_SE (1<<10) /* Single Step */
33#define MSR_BE (1<<9) /* Branch Trace */
34#define MSR_DE (1<<9) /* Debug Exception Enable */
35#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
36#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
37#define MSR_IR (1<<5) /* Instruction Relocate */
38#define MSR_DR (1<<4) /* Data Relocate */
39#define MSR_PE (1<<3) /* Protection Enable */
40#define MSR_PX (1<<2) /* Protection Exclusive Mode */
41#define MSR_RI (1<<1) /* Recoverable Exception */
42#define MSR_LE (1<<0) /* Little Endian */
43
44#ifdef CONFIG_APUS_FAST_EXCEPT
45#define MSR_ MSR_ME|MSR_IP|MSR_RI
46#else
47#define MSR_ MSR_ME|MSR_RI
48#endif
49#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
50#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
51
52/* Floating Point Status and Control Register (FPSCR) Fields */
53
54#define FPSCR_FX 0x80000000 /* FPU exception summary */
55#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
56#define FPSCR_VX 0x20000000 /* Invalid operation summary */
57#define FPSCR_OX 0x10000000 /* Overflow exception summary */
58#define FPSCR_UX 0x08000000 /* Underflow exception summary */
59#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
60#define FPSCR_XX 0x02000000 /* Inexact exception summary */
61#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
62#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
63#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
64#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
65#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
66#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
67#define FPSCR_FR 0x00040000 /* Fraction rounded */
68#define FPSCR_FI 0x00020000 /* Fraction inexact */
69#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
70#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
71#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
72#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
73#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
74#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
75#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
76#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
77#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
78#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
79#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
80#define FPSCR_RN 0x00000003 /* FPU rounding control */
81
82/* Special Purpose Registers (SPRNs)*/
83
84#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
85#define SPRN_CTR 0x009 /* Count Register */
86#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
87#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
88#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
89#define SPRN_DAR 0x013 /* Data Address Register */
90#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
91#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
92#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
93#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
94#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
95#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
96#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
97#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
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WD		 98#define SPRN_DBAT4L 0x238 /* Data BAT 4 Lower Register */
99#define SPRN_DBAT4U 0x239 /* Data BAT 4 Upper Register */
100#define SPRN_DBAT5L 0x23A /* Data BAT 5 Lower Register */
101#define SPRN_DBAT5U 0x23B /* Data BAT 5 Upper Register */
102#define SPRN_DBAT6L 0x23C /* Data BAT 6 Lower Register */
103#define SPRN_DBAT6U 0x23D /* Data BAT 6 Upper Register */
104#define SPRN_DBAT7L 0x23E /* Data BAT 7 Lower Register */
105#define SPRN_DBAT7U 0x23F /* Data BAT 7 Lower Register */
935ecca1
WD		 106#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
107#define DBCR_EDM 0x80000000
108#define DBCR_IDM 0x40000000
109#define DBCR_RST(x) (((x) & 0x3) << 28)
110#define DBCR_RST_NONE 0
111#define DBCR_RST_CORE 1
112#define DBCR_RST_CHIP 2
113#define DBCR_RST_SYSTEM 3
114#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
115#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
116#define DBCR_EDE 0x02000000 /* Exception Debug Event */
117#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
118#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
119#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
120#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
121#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
122#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
123#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
124#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
125#define DAC_BYTE 0
126#define DAC_HALF 1
127#define DAC_WORD 2
128#define DAC_QUAD 3
129#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
130#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
131#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
132#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
133#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
134#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
135#define DBCR_SIA 0x00000008 /* Second IAC Enable */
136#define DBCR_SDA 0x00000004 /* Second DAC Enable */
137#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
138#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
139#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
140#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
141#define SPRN_DBSR 0x3F0 /* Debug Status Register */
142#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
143#define DCCR_NOCACHE 0 /* Noncacheable */
144#define DCCR_CACHE 1 /* Cacheable */
145#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
146#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
147#define DCWR_COPY 0 /* Copy-back */
148#define DCWR_WRITE 1 /* Write-through */
149#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
150#define SPRN_DEC 0x016 /* Decrement Register */
151#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
152#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
153#define SPRN_EAR 0x11A /* External Address Register */
154#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
155#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
156#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
157#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
158#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
159#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
160#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
161#define ESR_PTR 0x02000000 /* Program Exception - Trap */
162#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
163#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
164#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
165#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
166#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
167#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
168#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
169#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
170#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
171#define HID0_SBCLK (1<<27)
172#define HID0_EICE (1<<26)
173#define HID0_ECLK (1<<25)
174#define HID0_PAR (1<<24)
175#define HID0_DOZE (1<<23)
176#define HID0_NAP (1<<22)
177#define HID0_SLEEP (1<<21)
178#define HID0_DPM (1<<20)
179#define HID0_ICE (1<<15) /* Instruction Cache Enable */
180#define HID0_DCE (1<<14) /* Data Cache Enable */
181#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
182#define HID0_DLOCK (1<<12) /* Data Cache Lock */
183#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
184#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
185#define HID0_DCI HID0_DCFI
186#define HID0_SPD (1<<9) /* Speculative disable */
187#define HID0_SGE (1<<7) /* Store Gathering Enable */
188#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
189#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
190#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
191#define HID0_ABE (1<<3) /* Address Broadcast Enable */
192#define HID0_BHTE (1<<2) /* Branch History Table Enable */
193#define HID0_BTCD (1<<1) /* Branch target cache disable */
194#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
195#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
196#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
197#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
198#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
199#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
200#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
201#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
202#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
203#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
204#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
205#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
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WD		 206#define SPRN_IBAT4L 0x230 /* Instruction BAT 4 Lower Register */
207#define SPRN_IBAT4U 0x231 /* Instruction BAT 4 Upper Register */
208#define SPRN_IBAT5L 0x232 /* Instruction BAT 5 Lower Register */
209#define SPRN_IBAT5U 0x233 /* Instruction BAT 5 Upper Register */
210#define SPRN_IBAT6L 0x234 /* Instruction BAT 6 Lower Register */
211#define SPRN_IBAT6U 0x235 /* Instruction BAT 6 Upper Register */
212#define SPRN_IBAT7L 0x236 /* Instruction BAT 7 Lower Register */
213#define SPRN_IBAT7U 0x237 /* Instruction BAT 7 Lower Register */
935ecca1
WD		 214#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
215#define ICCR_NOCACHE 0 /* Noncacheable */
216#define ICCR_CACHE 1 /* Cacheable */
217#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
218#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
219#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
220#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
221#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
222#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
223#define SPRN_LR 0x008 /* Link Register */
224#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
225#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
226#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
227#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
228#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
229#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
230#define SPRN_PID 0x3B1 /* Process ID */
231#define SPRN_PIR 0x3FF /* Processor Identification Register */
232#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
233#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
234#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
235#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
236#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
237#define SPRN_PVR 0x11F /* Processor Version Register */
238#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
239#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
240#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
241#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
242#define SGR_NORMAL 0
243#define SGR_GUARDED 1
244#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
245#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
246#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
247#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
248#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
249#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
250#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
251#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
252#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
253#define SPRN_TBHI 0x3DC /* Time Base High */
254#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
255#define SPRN_TBLO 0x3DD /* Time Base Low */
256#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
257#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */
258#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
259#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
260#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
261#define SPRN_TCR 0x3DA /* Timer Control Register */
262#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
263#define WP_2_17 0 /* 2^17 clocks */
264#define WP_2_21 1 /* 2^21 clocks */
265#define WP_2_25 2 /* 2^25 clocks */
266#define WP_2_29 3 /* 2^29 clocks */
267#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
268#define WRC_NONE 0 /* No reset will occur */
269#define WRC_CORE 1 /* Core reset will occur */
270#define WRC_CHIP 2 /* Chip reset will occur */
271#define WRC_SYSTEM 3 /* System reset will occur */
272#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
273#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
274#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
275#define FP_2_9 0 /* 2^9 clocks */
276#define FP_2_13 1 /* 2^13 clocks */
277#define FP_2_17 2 /* 2^17 clocks */
278#define FP_2_21 3 /* 2^21 clocks */
279#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
280#define TCR_ARE 0x00400000 /* Auto Reload Enable */
281#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
282#define THRM1_TIN (1<<0)
283#define THRM1_TIV (1<<1)
284#define THRM1_THRES (0x7f<<2)
285#define THRM1_TID (1<<29)
286#define THRM1_TIE (1<<30)
287#define THRM1_V (1<<31)
288#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
289#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
290#define THRM3_E (1<<31)
291#define SPRN_TSR 0x3D8 /* Timer Status Register */
292#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
293#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
294#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
295#define WRS_NONE 0 /* No WDT reset occurred */
296#define WRS_CORE 1 /* WDT forced core reset */
297#define WRS_CHIP 2 /* WDT forced chip reset */
298#define WRS_SYSTEM 3 /* WDT forced system reset */
299#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
300#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
301#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
302#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
303#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
304#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
305#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
306#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
307#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
308#define SPRN_XER 0x001 /* Fixed Point Exception Register */
309#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
310
311/* Short-hand versions for a number of the above SPRNs */
312
313#define CTR SPRN_CTR /* Counter Register */
314#define DAR SPRN_DAR /* Data Address Register */
315#define DABR SPRN_DABR /* Data Address Breakpoint Register */
316#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
317#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
318#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
319#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
320#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
321#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
322#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
323#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
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WD		 324#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
325#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
326#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
327#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
328#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
329#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
330#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
331#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
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WD		 332#define DCMP SPRN_DCMP /* Data TLB Compare Register */
333#define DEC SPRN_DEC /* Decrement Register */
334#define DMISS SPRN_DMISS /* Data TLB Miss Register */
335#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
336#define EAR SPRN_EAR /* External Address Register */
337#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
338#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
339#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
340#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
341#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
342#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
343#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
344#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
345#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
346#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
347#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
348#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
349#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
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WD		 350#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
351#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
352#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
353#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
354#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
355#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
356#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
357#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
935ecca1
WD		 358#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
359#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
360#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
361#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
362#define LR SPRN_LR
363#define PVR SPRN_PVR /* Processor Version */
364#define RPA SPRN_RPA /* Required Physical Address Register */
365#define SDR1 SPRN_SDR1 /* MMU hash base register */
366#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
367#define SPR1 SPRN_SPRG1
368#define SPR2 SPRN_SPRG2
369#define SPR3 SPRN_SPRG3
370#define SPRG0 SPRN_SPRG0
371#define SPRG1 SPRN_SPRG1
372#define SPRG2 SPRN_SPRG2
373#define SPRG3 SPRN_SPRG3
374#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
375#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
376#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
377#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
378#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
379#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
380#define ICTC 1019
381#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
382#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
383#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
384#define XER SPRN_XER
385
386
387/* Device Control Registers */
388
389#define DCRN_BEAR 0x090 /* Bus Error Address Register */
390#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
391#define BESR_DSES 0x80000000 /* Data-Side Error Status */
392#define BESR_DMES 0x40000000 /* DMA Error Status */
393#define BESR_RWS 0x20000000 /* Read/Write Status */
394#define BESR_ETMASK 0x1C000000 /* Error Type */
395#define ET_PROT 0
396#define ET_PARITY 1
397#define ET_NCFG 2
398#define ET_BUSERR 4
399#define ET_BUSTO 6
400#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
401#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
402#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
403#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
404#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
405#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
406#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
407#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
408#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
409#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
410#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
411#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
412#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
413#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
414#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
415#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
416#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
417#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
418#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
419#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
420#define DCRN_DMASR 0x0E0 /* DMA Status Register */
421#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
422#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
423#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
424#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
425#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
426#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
427#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
428#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
429#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
430#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
431#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
432#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
433#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
434#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
435#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
436#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
437#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
438#define IOCR_E0TE 0x80000000
439#define IOCR_E0LP 0x40000000
440#define IOCR_E1TE 0x20000000
441#define IOCR_E1LP 0x10000000
442#define IOCR_E2TE 0x08000000
443#define IOCR_E2LP 0x04000000
444#define IOCR_E3TE 0x02000000
445#define IOCR_E3LP 0x01000000
446#define IOCR_E4TE 0x00800000
447#define IOCR_E4LP 0x00400000
448#define IOCR_EDT 0x00080000
449#define IOCR_SOR 0x00040000
450#define IOCR_EDO 0x00008000
451#define IOCR_2XC 0x00004000
452#define IOCR_ATC 0x00002000
453#define IOCR_SPD 0x00001000
454#define IOCR_BEM 0x00000800
455#define IOCR_PTD 0x00000400
456#define IOCR_ARE 0x00000080
457#define IOCR_DRC 0x00000020
458#define IOCR_RDM(x) (((x) & 0x3) << 3)
459#define IOCR_TCS 0x00000004
460#define IOCR_SCS 0x00000002
461#define IOCR_SPC 0x00000001
462
463
464/* Processor Version Register */
465
466/* Processor Version Register (PVR) field extraction */
467
468#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
469#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
470
471/*
472 * IBM has further subdivided the standard PowerPC 16-bit version and
473 * revision subfields of the PVR for the PowerPC 403s into the following:
474 */
475
476#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
477#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
478#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
479#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
480#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
481#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
482
483/* Processor Version Numbers */
484
485#define PVR_403GA 0x00200000
486#define PVR_403GB 0x00200100
487#define PVR_403GC 0x00200200
488#define PVR_403GCX 0x00201400
489#define PVR_405GP 0x40110000
490#define PVR_405GP_RB 0x40110040
491#define PVR_405GP_RC 0x40110082
492#define PVR_405GP_RD 0x401100C4
493#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
494#define PVR_405CR_RA 0x40110041
495#define PVR_405CR_RB 0x401100C5
496#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
baa3d528 497#define PVR_405GPR_RB 0x50910951
935ecca1
WD		 498#define PVR_440GP_RB 0x40120440
499#define PVR_440GP_RC 0x40120481
b867d705 500#define PVR_405EP_RB 0x51210950
935ecca1
WD		 501#define PVR_601 0x00010000
502#define PVR_602 0x00050000
503#define PVR_603 0x00030000
504#define PVR_603e 0x00060000
505#define PVR_603ev 0x00070000
506#define PVR_603r 0x00071000
507#define PVR_604 0x00040000
508#define PVR_604e 0x00090000
509#define PVR_604r 0x000A0000
510#define PVR_620 0x00140000
511#define PVR_740 0x00080000
512#define PVR_750 PVR_740
513#define PVR_740P 0x10080000
514#define PVR_750P PVR_740P
515/*
516 * For the 8xx processors, all of them report the same PVR family for
517 * the PowerPC core. The various versions of these processors must be
518 * differentiated by the version number in the Communication Processor
519 * Module (CPM).
520 */
521#define PVR_821 0x00500000
522#define PVR_823 PVR_821
523#define PVR_850 PVR_821
524#define PVR_860 PVR_821
525#define PVR_7400 0x000C0000
526#define PVR_8240 0x00810100
527#define PVR_8260 PVR_8240
528
529
530/* I am just adding a single entry for 8260 boards. I think we may be
531 * able to combine mbx, fads, rpxlite, bseip, and classic into a single
532 * generic 8xx as well. The boards containing these processors are either
533 * identical at the processor level (due to the high integration) or so
534 * wildly different that testing _machine at run time is best replaced by
535 * conditional compilation by board type (found in their respective .h file).
536 * -- Dan
537 */
538#define _MACH_prep 0x00000001
539#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
540#define _MACH_chrp 0x00000004 /* chrp machine */
541#define _MACH_mbx 0x00000008 /* Motorola MBX board */
542#define _MACH_apus 0x00000010 /* amiga with phase5 powerup */
543#define _MACH_fads 0x00000020 /* Motorola FADS board */
544#define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */
545#define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */
546#define _MACH_yk 0x00000100 /* Motorola Yellowknife */
547#define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */
548#define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */
549#define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */
550#define _MACH_walnut 0x00001000 /* IBM "Walnut" 405GP eval. board */
551#define _MACH_8260 0x00002000 /* Generic 8260 */
552#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
553#define _MACH_tqm860 0x00008000 /* TQM860/L */
554#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
555
556
557/* see residual.h for these */
558#define _PREP_Motorola 0x01 /* motorola prep */
559#define _PREP_Firm 0x02 /* firmworks prep */
560#define _PREP_IBM 0x00 /* ibm prep */
561#define _PREP_Bull 0x03 /* bull prep */
562#define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */
563
564/*
565 * Radstone board types
566 */
567#define RS_SYS_TYPE_PPC1 0
568#define RS_SYS_TYPE_PPC2 1
569#define RS_SYS_TYPE_PPC1a 2
570#define RS_SYS_TYPE_PPC2a 3
571#define RS_SYS_TYPE_PPC4 4
572#define RS_SYS_TYPE_PPC4a 5
573#define RS_SYS_TYPE_PPC2ep 6
574
575/* these are arbitrary */
576#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
577#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
578
579#define _GLOBAL(n)\
580 .globl n;\
581n:
582
583/* Macros for setting and retrieving special purpose registers */
584
585#define stringify(s) tostring(s)
586#define tostring(s) #s
587
588#define mfdcr(rn) ({unsigned int rval; \
589 asm volatile("mfdcr %0," stringify(rn) \
590 : "=r" (rval)); rval;})
591#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
592
593#define mfmsr() ({unsigned int rval; \
594 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
595#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
596
597#define mfspr(rn) ({unsigned int rval; \
598 asm volatile("mfspr %0," stringify(rn) \
599 : "=r" (rval)); rval;})
600#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
601
602#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
603
604/* Segment Registers */
605
606#define SR0 0
607#define SR1 1
608#define SR2 2
609#define SR3 3
610#define SR4 4
611#define SR5 5
612#define SR6 6
613#define SR7 7
614#define SR8 8
615#define SR9 9
616#define SR10 10
617#define SR11 11
618#define SR12 12
619#define SR13 13
620#define SR14 14
621#define SR15 15
622
623#ifndef __ASSEMBLY__
624#ifndef CONFIG_MACH_SPECIFIC
625extern int _machine;
626extern int have_of;
627#endif /* CONFIG_MACH_SPECIFIC */
628
629/* what kind of prep workstation we are */
630extern int _prep_type;
631/*
632 * This is used to identify the board type from a given PReP board
633 * vendor. Board revision is also made available.
634 */
635extern unsigned char ucSystemType;
636extern unsigned char ucBoardRev;
637extern unsigned char ucBoardRevMaj, ucBoardRevMin;
638
639struct task_struct;
640void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
641void release_thread(struct task_struct *);
642
643/*
644 * Create a new kernel thread.
645 */
646extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
647
648/*
649 * Bus types
650 */
651#define EISA_bus 0
652#define EISA_bus__is_a_macro /* for versions in ksyms.c */
653#define MCA_bus 0
654#define MCA_bus__is_a_macro /* for versions in ksyms.c */
655
656/* Lazy FPU handling on uni-processor */
657extern struct task_struct *last_task_used_math;
658extern struct task_struct *last_task_used_altivec;
659
660/*
661 * this is the minimum allowable io space due to the location
662 * of the io areas on prep (first one at 0x80000000) but
663 * as soon as I get around to remapping the io areas with the BATs
664 * to match the mac we can raise this. -- Cort
665 */
666#define TASK_SIZE (0x80000000UL)
667
668/* This decides where the kernel will search for a free chunk of vm
669 * space during mmap's.
670 */
671#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
672
673typedef struct {
674 unsigned long seg;
675} mm_segment_t;
676
677struct thread_struct {
678 unsigned long ksp; /* Kernel stack pointer */
679 unsigned long wchan; /* Event task is sleeping on */
680 struct pt_regs *regs; /* Pointer to saved register state */
681 mm_segment_t fs; /* for get_fs() validation */
682 void *pgdir; /* root of page-table tree */
683 signed long last_syscall;
684 double fpr[32]; /* Complete floating point set */
685 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
686 unsigned long fpscr; /* Floating point status */
687#ifdef CONFIG_ALTIVEC
688 vector128 vr[32]; /* Complete AltiVec set */
689 vector128 vscr; /* AltiVec status */
690 unsigned long vrsave;
691#endif /* CONFIG_ALTIVEC */
692};
693
694#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
695
696#define INIT_THREAD { \
697 INIT_SP, /* ksp */ \
698 0, /* wchan */ \
699 (struct pt_regs *)INIT_SP - 1, /* regs */ \
700 KERNEL_DS, /*fs*/ \
701 swapper_pg_dir, /* pgdir */ \
702 0, /* last_syscall */ \
703 {0}, 0, 0 \
704}
705
706/*
707 * Note: the vm_start and vm_end fields here should *not*
708 * be in kernel space. (Could vm_end == vm_start perhaps?)
709 */
710#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
711 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
712 1, NULL, NULL }
713
714/*
715 * Return saved PC of a blocked thread. For now, this is the "user" PC
716 */
717static inline unsigned long thread_saved_pc(struct thread_struct *t)
718{
719 return (t->regs) ? t->regs->nip : 0;
720}
721
722#define copy_segments(tsk, mm) do { } while (0)
723#define release_segments(mm) do { } while (0)
724#define forget_segments() do { } while (0)
725
726unsigned long get_wchan(struct task_struct *p);
727
728#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
729#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
730
731/*
732 * NOTE! The task struct and the stack go together
733 */
734#define THREAD_SIZE (2*PAGE_SIZE)
735#define alloc_task_struct() \
736 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
737#define free_task_struct(p) free_pages((unsigned long)(p),1)
738#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
739
740/* in process.c - for early bootup debug -- Cort */
741int ll_printk(const char *, ...);
742void ll_puts(const char *);
743
744#define init_task (init_task_union.task)
745#define init_stack (init_task_union.stack)
746
747/* In misc.c */
748void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
749
750#endif /* ndef ASSEMBLY*/
751
752#ifdef CONFIG_MACH_SPECIFIC
753#if defined(CONFIG_8xx)
754#define _machine _MACH_8xx
755#define have_of 0
756#elif defined(CONFIG_OAK)
757#define _machine _MACH_oak
758#define have_of 0
759#elif defined(CONFIG_WALNUT)
760#define _machine _MACH_walnut
761#define have_of 0
762#elif defined(CONFIG_APUS)
763#define _machine _MACH_apus
764#define have_of 0
765#elif defined(CONFIG_GEMINI)
766#define _machine _MACH_gemini
767#define have_of 0
768#elif defined(CONFIG_8260)
769#define _machine _MACH_8260
770#define have_of 0
771#elif defined(CONFIG_SANDPOINT)
772#define _machine _MACH_sandpoint
773#define have_of 0
774#else
775#error "Machine not defined correctly"
776#endif
777#endif /* CONFIG_MACH_SPECIFIC */
778
779#endif /* __ASM_PPC_PROCESSOR_H */
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