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fe8c2806 WD |
1 | /* |
2 | * MPC8xx Communication Processor Module. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
8cba090c | 5 | * (C) Copyright 2000-2006 |
d4ca31c4 WD |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
fe8c2806 WD |
8 | * This file contains structures and information for the communication |
9 | * processor channels. Some CPM control and status is available | |
10 | * throught the MPC8xx internal memory map. See immap.h for details. | |
11 | * This file only contains what I need for the moment, not the total | |
12 | * CPM capabilities. I (or someone else) will add definitions as they | |
13 | * are needed. -- Dan | |
14 | * | |
15 | * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 | |
16 | * bytes of the DP RAM and relocates the I2C parameter area to the | |
17 | * IDMA1 space. The remaining DP RAM is available for buffer descriptors | |
18 | * or other use. | |
19 | */ | |
20 | #ifndef __CPM_8XX__ | |
21 | #define __CPM_8XX__ | |
22 | ||
23 | #include <linux/config.h> | |
24 | #include <asm/8xx_immap.h> | |
25 | ||
26 | /* CPM Command register. | |
27 | */ | |
7c7a23bd WD |
28 | #define CPM_CR_RST ((ushort)0x8000) |
29 | #define CPM_CR_OPCODE ((ushort)0x0f00) | |
30 | #define CPM_CR_CHAN ((ushort)0x00f0) | |
31 | #define CPM_CR_FLG ((ushort)0x0001) | |
fe8c2806 WD |
32 | |
33 | /* Some commands (there are more...later) | |
34 | */ | |
35 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | |
36 | #define CPM_CR_INIT_RX ((ushort)0x0001) | |
37 | #define CPM_CR_INIT_TX ((ushort)0x0002) | |
38 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | |
39 | #define CPM_CR_STOP_TX ((ushort)0x0004) | |
40 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | |
41 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | |
42 | ||
43 | /* Channel numbers. | |
44 | */ | |
7c7a23bd WD |
45 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) |
46 | #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ | |
47 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) | |
48 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ | |
49 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) | |
50 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ | |
51 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) | |
52 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ | |
fe8c2806 WD |
53 | |
54 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) | |
55 | ||
56 | /* | |
57 | * DPRAM defines and allocation functions | |
58 | */ | |
59 | ||
60 | /* The dual ported RAM is multi-functional. Some areas can be (and are | |
61 | * being) used for microcode. There is an area that can only be used | |
62 | * as data ram for buffer descriptors, which is all we use right now. | |
63 | * Currently the first 512 and last 256 bytes are used for microcode. | |
64 | */ | |
6d0f6bcf | 65 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
fe8c2806 WD |
66 | |
67 | #define CPM_DATAONLY_BASE ((uint)0x0800) | |
68 | #define CPM_DATAONLY_SIZE ((uint)0x0700) | |
69 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | |
70 | ||
71 | #else | |
72 | ||
73 | #define CPM_SERIAL_BASE 0x0800 | |
74 | #define CPM_I2C_BASE 0x0820 | |
75 | #define CPM_SPI_BASE 0x0840 | |
76 | #define CPM_FEC_BASE 0x0860 | |
79536a6e | 77 | #define CPM_SERIAL2_BASE 0x08E0 |
fe8c2806 WD |
78 | #define CPM_SCC_BASE 0x0900 |
79 | #define CPM_POST_BASE 0x0980 | |
281e00a3 | 80 | #define CPM_WLKBD_BASE 0x0a00 |
fe8c2806 WD |
81 | |
82 | #endif | |
83 | ||
6d0f6bcf | 84 | #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR |
fe8c2806 | 85 | #define CPM_POST_WORD_ADDR 0x07FC |
ea909b76 | 86 | #else |
6d0f6bcf | 87 | #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR |
ea909b76 | 88 | #endif |
fe8c2806 | 89 | |
6d0f6bcf | 90 | #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR |
bdccc4fe WD |
91 | #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) |
92 | #else | |
6d0f6bcf | 93 | #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR |
bdccc4fe WD |
94 | #endif |
95 | ||
fe8c2806 WD |
96 | #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ |
97 | ||
98 | /* Export the base address of the communication processor registers | |
99 | * and dual port ram. | |
100 | */ | |
101 | extern cpm8xx_t *cpmp; /* Pointer to comm processor */ | |
102 | ||
103 | /* Buffer descriptors used by many of the CPM protocols. | |
104 | */ | |
105 | typedef struct cpm_buf_desc { | |
106 | ushort cbd_sc; /* Status and Control */ | |
107 | ushort cbd_datlen; /* Data length in buffer */ | |
108 | uint cbd_bufaddr; /* Buffer address in host memory */ | |
109 | } cbd_t; | |
110 | ||
16263087 | 111 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ |
fe8c2806 WD |
112 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ |
113 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | |
114 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | |
115 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | |
116 | #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ | |
117 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | |
118 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | |
119 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | |
120 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | |
121 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | |
122 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | |
123 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | |
124 | #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ | |
125 | ||
126 | /* Parameter RAM offsets. | |
127 | */ | |
128 | #define PROFF_SCC1 ((uint)0x0000) | |
129 | #define PROFF_IIC ((uint)0x0080) | |
130 | #define PROFF_SCC2 ((uint)0x0100) | |
131 | #define PROFF_SPI ((uint)0x0180) | |
132 | #define PROFF_SCC3 ((uint)0x0200) | |
133 | #define PROFF_SMC1 ((uint)0x0280) | |
134 | #define PROFF_SCC4 ((uint)0x0300) | |
135 | #define PROFF_SMC2 ((uint)0x0380) | |
136 | ||
137 | /* Define enough so I can at least use the serial port as a UART. | |
138 | * The MBX uses SMC1 as the host serial port. | |
139 | */ | |
140 | typedef struct smc_uart { | |
141 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | |
142 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | |
143 | u_char smc_rfcr; /* Rx function code */ | |
144 | u_char smc_tfcr; /* Tx function code */ | |
145 | ushort smc_mrblr; /* Max receive buffer length */ | |
146 | uint smc_rstate; /* Internal */ | |
147 | uint smc_idp; /* Internal */ | |
148 | ushort smc_rbptr; /* Internal */ | |
149 | ushort smc_ibc; /* Internal */ | |
150 | uint smc_rxtmp; /* Internal */ | |
151 | uint smc_tstate; /* Internal */ | |
152 | uint smc_tdp; /* Internal */ | |
153 | ushort smc_tbptr; /* Internal */ | |
154 | ushort smc_tbc; /* Internal */ | |
155 | uint smc_txtmp; /* Internal */ | |
156 | ushort smc_maxidl; /* Maximum idle characters */ | |
157 | ushort smc_tmpidl; /* Temporary idle counter */ | |
158 | ushort smc_brklen; /* Last received break length */ | |
159 | ushort smc_brkec; /* rcv'd break condition counter */ | |
160 | ushort smc_brkcr; /* xmt break count register */ | |
161 | ushort smc_rmask; /* Temporary bit mask */ | |
b423d055 HS |
162 | u_char res1[8]; |
163 | ushort smc_rpbase; /* Relocation pointer */ | |
fe8c2806 WD |
164 | } smc_uart_t; |
165 | ||
166 | /* Function code bits. | |
167 | */ | |
168 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ | |
169 | ||
170 | /* SMC uart mode register. | |
171 | */ | |
172 | #define SMCMR_REN ((ushort)0x0001) | |
173 | #define SMCMR_TEN ((ushort)0x0002) | |
174 | #define SMCMR_DM ((ushort)0x000c) | |
175 | #define SMCMR_SM_GCI ((ushort)0x0000) | |
176 | #define SMCMR_SM_UART ((ushort)0x0020) | |
177 | #define SMCMR_SM_TRANS ((ushort)0x0030) | |
178 | #define SMCMR_SM_MASK ((ushort)0x0030) | |
179 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | |
180 | #define SMCMR_REVD SMCMR_PM_EVEN | |
181 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | |
182 | #define SMCMR_BS SMCMR_PEN | |
183 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | |
184 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | |
185 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | |
186 | ||
187 | /* SMC2 as Centronics parallel printer. It is half duplex, in that | |
188 | * it can only receive or transmit. The parameter ram values for | |
189 | * each direction are either unique or properly overlap, so we can | |
190 | * include them in one structure. | |
191 | */ | |
192 | typedef struct smc_centronics { | |
193 | ushort scent_rbase; | |
194 | ushort scent_tbase; | |
195 | u_char scent_cfcr; | |
196 | u_char scent_smask; | |
197 | ushort scent_mrblr; | |
198 | uint scent_rstate; | |
199 | uint scent_r_ptr; | |
200 | ushort scent_rbptr; | |
201 | ushort scent_r_cnt; | |
202 | uint scent_rtemp; | |
203 | uint scent_tstate; | |
204 | uint scent_t_ptr; | |
205 | ushort scent_tbptr; | |
206 | ushort scent_t_cnt; | |
207 | uint scent_ttemp; | |
208 | ushort scent_max_sl; | |
209 | ushort scent_sl_cnt; | |
210 | ushort scent_character1; | |
211 | ushort scent_character2; | |
212 | ushort scent_character3; | |
213 | ushort scent_character4; | |
214 | ushort scent_character5; | |
215 | ushort scent_character6; | |
216 | ushort scent_character7; | |
217 | ushort scent_character8; | |
218 | ushort scent_rccm; | |
219 | ushort scent_rccr; | |
220 | } smc_cent_t; | |
221 | ||
222 | /* Centronics Status Mask Register. | |
223 | */ | |
224 | #define SMC_CENT_F ((u_char)0x08) | |
225 | #define SMC_CENT_PE ((u_char)0x04) | |
226 | #define SMC_CENT_S ((u_char)0x02) | |
227 | ||
228 | /* SMC Event and Mask register. | |
229 | */ | |
230 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | |
231 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | |
232 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ | |
233 | #define SMCM_BSY ((unsigned char)0x04) | |
234 | #define SMCM_TX ((unsigned char)0x02) | |
235 | #define SMCM_RX ((unsigned char)0x01) | |
236 | ||
237 | /* Baud rate generators. | |
238 | */ | |
239 | #define CPM_BRG_RST ((uint)0x00020000) | |
240 | #define CPM_BRG_EN ((uint)0x00010000) | |
241 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | |
242 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) | |
243 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) | |
244 | #define CPM_BRG_ATB ((uint)0x00002000) | |
245 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | |
246 | #define CPM_BRG_DIV16 ((uint)0x00000001) | |
247 | ||
248 | /* SI Clock Route Register | |
249 | */ | |
250 | #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) | |
251 | #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) | |
252 | #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) | |
253 | #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) | |
254 | #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) | |
255 | #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) | |
256 | #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) | |
257 | #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) | |
258 | ||
259 | /* SCCs. | |
260 | */ | |
261 | #define SCC_GSMRH_IRP ((uint)0x00040000) | |
262 | #define SCC_GSMRH_GDE ((uint)0x00010000) | |
263 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | |
264 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | |
265 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | |
266 | #define SCC_GSMRH_REVD ((uint)0x00002000) | |
267 | #define SCC_GSMRH_TRX ((uint)0x00001000) | |
268 | #define SCC_GSMRH_TTX ((uint)0x00000800) | |
269 | #define SCC_GSMRH_CDP ((uint)0x00000400) | |
270 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | |
271 | #define SCC_GSMRH_CDS ((uint)0x00000100) | |
272 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | |
273 | #define SCC_GSMRH_TFL ((uint)0x00000040) | |
274 | #define SCC_GSMRH_RFW ((uint)0x00000020) | |
275 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | |
276 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | |
277 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | |
278 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | |
279 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | |
280 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | |
281 | ||
282 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | |
283 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | |
284 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | |
285 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | |
286 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | |
287 | #define SCC_GSMRL_TCI ((uint)0x10000000) | |
288 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | |
289 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | |
290 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | |
291 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | |
292 | #define SCC_GSMRL_RINV ((uint)0x02000000) | |
293 | #define SCC_GSMRL_TINV ((uint)0x01000000) | |
294 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | |
295 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | |
296 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | |
297 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | |
298 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | |
299 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | |
300 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | |
301 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | |
302 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | |
303 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | |
304 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | |
305 | #define SCC_GSMRL_TEND ((uint)0x00040000) | |
306 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | |
307 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | |
308 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | |
309 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | |
310 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | |
311 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | |
312 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | |
313 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | |
314 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | |
315 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | |
316 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | |
317 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | |
318 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | |
319 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | |
320 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | |
321 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | |
322 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | |
323 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | |
324 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | |
325 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | |
326 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | |
327 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | |
328 | #define SCC_GSMRL_ENR ((uint)0x00000020) | |
329 | #define SCC_GSMRL_ENT ((uint)0x00000010) | |
330 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | |
331 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | |
332 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | |
333 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | |
334 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | |
335 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | |
336 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | |
337 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | |
338 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | |
339 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | |
340 | ||
341 | #define SCC_TODR_TOD ((ushort)0x8000) | |
342 | ||
343 | /* SCC Event and Mask register. | |
344 | */ | |
345 | #define SCCM_TXE ((unsigned char)0x10) | |
346 | #define SCCM_BSY ((unsigned char)0x04) | |
347 | #define SCCM_TX ((unsigned char)0x02) | |
348 | #define SCCM_RX ((unsigned char)0x01) | |
349 | ||
350 | typedef struct scc_param { | |
351 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | |
352 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | |
353 | u_char scc_rfcr; /* Rx function code */ | |
354 | u_char scc_tfcr; /* Tx function code */ | |
355 | ushort scc_mrblr; /* Max receive buffer length */ | |
356 | uint scc_rstate; /* Internal */ | |
357 | uint scc_idp; /* Internal */ | |
358 | ushort scc_rbptr; /* Internal */ | |
359 | ushort scc_ibc; /* Internal */ | |
360 | uint scc_rxtmp; /* Internal */ | |
361 | uint scc_tstate; /* Internal */ | |
362 | uint scc_tdp; /* Internal */ | |
363 | ushort scc_tbptr; /* Internal */ | |
364 | ushort scc_tbc; /* Internal */ | |
365 | uint scc_txtmp; /* Internal */ | |
366 | uint scc_rcrc; /* Internal */ | |
367 | uint scc_tcrc; /* Internal */ | |
368 | } sccp_t; | |
369 | ||
370 | /* Function code bits. | |
371 | */ | |
372 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ | |
373 | ||
374 | /* CPM Ethernet through SCCx. | |
375 | */ | |
376 | typedef struct scc_enet { | |
377 | sccp_t sen_genscc; | |
378 | uint sen_cpres; /* Preset CRC */ | |
379 | uint sen_cmask; /* Constant mask for CRC */ | |
380 | uint sen_crcec; /* CRC Error counter */ | |
381 | uint sen_alec; /* alignment error counter */ | |
382 | uint sen_disfc; /* discard frame counter */ | |
383 | ushort sen_pads; /* Tx short frame pad character */ | |
384 | ushort sen_retlim; /* Retry limit threshold */ | |
385 | ushort sen_retcnt; /* Retry limit counter */ | |
386 | ushort sen_maxflr; /* maximum frame length register */ | |
387 | ushort sen_minflr; /* minimum frame length register */ | |
388 | ushort sen_maxd1; /* maximum DMA1 length */ | |
389 | ushort sen_maxd2; /* maximum DMA2 length */ | |
390 | ushort sen_maxd; /* Rx max DMA */ | |
391 | ushort sen_dmacnt; /* Rx DMA counter */ | |
392 | ushort sen_maxb; /* Max BD byte count */ | |
393 | ushort sen_gaddr1; /* Group address filter */ | |
394 | ushort sen_gaddr2; | |
395 | ushort sen_gaddr3; | |
396 | ushort sen_gaddr4; | |
397 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | |
398 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | |
399 | uint sen_tbuf0rba; /* Internal */ | |
400 | uint sen_tbuf0crc; /* Internal */ | |
401 | ushort sen_tbuf0bcnt; /* Internal */ | |
402 | ushort sen_paddrh; /* physical address (MSB) */ | |
403 | ushort sen_paddrm; | |
404 | ushort sen_paddrl; /* physical address (LSB) */ | |
405 | ushort sen_pper; /* persistence */ | |
406 | ushort sen_rfbdptr; /* Rx first BD pointer */ | |
407 | ushort sen_tfbdptr; /* Tx first BD pointer */ | |
408 | ushort sen_tlbdptr; /* Tx last BD pointer */ | |
409 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | |
410 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | |
411 | uint sen_tbuf1rba; /* Internal */ | |
412 | uint sen_tbuf1crc; /* Internal */ | |
413 | ushort sen_tbuf1bcnt; /* Internal */ | |
414 | ushort sen_txlen; /* Tx Frame length counter */ | |
415 | ushort sen_iaddr1; /* Individual address filter */ | |
416 | ushort sen_iaddr2; | |
417 | ushort sen_iaddr3; | |
418 | ushort sen_iaddr4; | |
419 | ushort sen_boffcnt; /* Backoff counter */ | |
420 | ||
421 | /* NOTE: Some versions of the manual have the following items | |
422 | * incorrectly documented. Below is the proper order. | |
423 | */ | |
424 | ushort sen_taddrh; /* temp address (MSB) */ | |
425 | ushort sen_taddrm; | |
426 | ushort sen_taddrl; /* temp address (LSB) */ | |
427 | } scc_enet_t; | |
428 | ||
429 | /********************************************************************** | |
430 | * | |
431 | * Board specific configuration settings. | |
432 | * | |
433 | * Please note that we use the presence of a #define SCC_ENET and/or | |
434 | * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. | |
435 | **********************************************************************/ | |
436 | ||
437 | ||
438 | /*** ADS *************************************************************/ | |
439 | ||
440 | #if defined(CONFIG_MPC860) && defined(CONFIG_ADS) | |
441 | /* This ENET stuff is for the MPC860ADS with ethernet on SCC1. | |
442 | */ | |
443 | ||
444 | #define PROFF_ENET PROFF_SCC1 | |
445 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
446 | #define SCC_ENET 0 | |
447 | ||
448 | #define PA_ENET_RXD ((ushort)0x0001) | |
449 | #define PA_ENET_TXD ((ushort)0x0002) | |
450 | #define PA_ENET_TCLK ((ushort)0x0100) | |
451 | #define PA_ENET_RCLK ((ushort)0x0200) | |
452 | ||
453 | #define PB_ENET_TENA ((uint)0x00001000) | |
454 | ||
455 | #define PC_ENET_CLSN ((ushort)0x0010) | |
456 | #define PC_ENET_RENA ((ushort)0x0020) | |
457 | ||
458 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
459 | #define SICR_ENET_CLKRT ((uint)0x0000002c) | |
460 | ||
461 | /* 68160 PHY control */ | |
462 | ||
463 | #define PC_ENET_ETHLOOP ((ushort)0x0800) | |
464 | #define PC_ENET_TPFLDL ((ushort)0x0400) | |
465 | #define PC_ENET_TPSQEL ((ushort)0x0200) | |
466 | ||
467 | #endif /* MPC860ADS */ | |
468 | ||
fe8c2806 WD |
469 | /*** BSEIP **********************************************************/ |
470 | ||
471 | #ifdef CONFIG_BSEIP | |
472 | /* This ENET stuff is for the MPC823 with ethernet on SCC2. | |
473 | * This is unique to the BSE ip-Engine board. | |
474 | */ | |
475 | #define PROFF_ENET PROFF_SCC2 | |
476 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
477 | #define SCC_ENET 1 | |
478 | #define PA_ENET_RXD ((ushort)0x0004) | |
479 | #define PA_ENET_TXD ((ushort)0x0008) | |
480 | #define PA_ENET_TCLK ((ushort)0x0100) | |
481 | #define PA_ENET_RCLK ((ushort)0x0200) | |
482 | #define PB_ENET_TENA ((uint)0x00002000) | |
483 | #define PC_ENET_CLSN ((ushort)0x0040) | |
484 | #define PC_ENET_RENA ((ushort)0x0080) | |
485 | ||
486 | /* BSE uses port B and C bits for PHY control also. | |
487 | */ | |
488 | #define PB_BSE_POWERUP ((uint)0x00000004) | |
489 | #define PB_BSE_FDXDIS ((uint)0x00008000) | |
490 | #define PC_BSE_LOOPBACK ((ushort)0x0800) | |
491 | ||
492 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
493 | #define SICR_ENET_CLKRT ((uint)0x00002c00) | |
494 | #endif /* CONFIG_BSEIP */ | |
495 | ||
496 | /*** BSEIP **********************************************************/ | |
497 | ||
498 | #ifdef CONFIG_FLAGADM | |
499 | /* Enet configuration for the FLAGADM */ | |
500 | /* Enet on SCC2 */ | |
501 | ||
502 | #define PROFF_ENET PROFF_SCC2 | |
503 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
504 | #define SCC_ENET 1 | |
7c7a23bd WD |
505 | #define PA_ENET_RXD ((ushort)0x0004) |
506 | #define PA_ENET_TXD ((ushort)0x0008) | |
fe8c2806 WD |
507 | #define PA_ENET_TCLK ((ushort)0x0100) |
508 | #define PA_ENET_RCLK ((ushort)0x0400) | |
509 | #define PB_ENET_TENA ((uint)0x00002000) | |
510 | #define PC_ENET_CLSN ((ushort)0x0040) | |
511 | #define PC_ENET_RENA ((ushort)0x0080) | |
512 | ||
513 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
514 | #define SICR_ENET_CLKRT ((uint)0x00003400) | |
515 | #endif /* CONFIG_FLAGADM */ | |
516 | ||
3bac3513 WD |
517 | /*** ELPT860 *********************************************************/ |
518 | ||
519 | #ifdef CONFIG_ELPT860 | |
520 | /* Bits in parallel I/O port registers that have to be set/cleared | |
521 | * to configure the pins for SCC1 use. | |
522 | */ | |
523 | # define PROFF_ENET PROFF_SCC1 | |
524 | # define CPM_CR_ENET CPM_CR_CH_SCC1 | |
525 | # define SCC_ENET 0 | |
526 | ||
527 | # define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ | |
528 | # define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ | |
529 | # define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
530 | # define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ | |
531 | ||
532 | # define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ | |
533 | # define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ | |
534 | # define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ | |
535 | ||
536 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to | |
537 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
538 | */ | |
539 | # define SICR_ENET_MASK ((uint)0x000000FF) | |
540 | # define SICR_ENET_CLKRT ((uint)0x00000025) | |
541 | #endif /* CONFIG_ELPT860 */ | |
542 | ||
fe8c2806 WD |
543 | /*** ESTEEM 192E **************************************************/ |
544 | #ifdef CONFIG_ESTEEM192E | |
545 | /* ESTEEM192E | |
546 | * This ENET stuff is for the MPC850 with ethernet on SCC2. This | |
547 | * is very similar to the RPX-Lite configuration. | |
548 | * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. | |
549 | */ | |
550 | ||
551 | #define PROFF_ENET PROFF_SCC2 | |
552 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
553 | #define SCC_ENET 1 | |
554 | ||
555 | #define PA_ENET_RXD ((ushort)0x0004) | |
556 | #define PA_ENET_TXD ((ushort)0x0008) | |
557 | #define PA_ENET_TCLK ((ushort)0x0200) | |
558 | #define PA_ENET_RCLK ((ushort)0x0800) | |
559 | #define PB_ENET_TENA ((uint)0x00002000) | |
560 | #define PC_ENET_CLSN ((ushort)0x0040) | |
561 | #define PC_ENET_RENA ((ushort)0x0080) | |
562 | ||
563 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
564 | #define SICR_ENET_CLKRT ((uint)0x00003d00) | |
565 | ||
566 | #define PB_ENET_LOOPBACK ((uint)0x00004000) | |
567 | #define PB_ENET_FDPLEX_DIS ((uint)0x00008000) | |
568 | ||
569 | #endif | |
570 | ||
571 | /*** FADS823 ********************************************************/ | |
572 | ||
573 | #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) | |
574 | /* This ENET stuff is for the MPC823FADS with ethernet on SCC2. | |
575 | */ | |
576 | #ifdef CONFIG_SCC2_ENET | |
577 | #define PROFF_ENET PROFF_SCC2 | |
578 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
579 | #define SCC_ENET 1 | |
580 | #define CPMVEC_ENET CPMVEC_SCC2 | |
581 | #endif | |
582 | ||
583 | #ifdef CONFIG_SCC1_ENET | |
584 | #define PROFF_ENET PROFF_SCC1 | |
585 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
586 | #define SCC_ENET 0 | |
587 | #define CPMVEC_ENET CPMVEC_SCC1 | |
588 | #endif | |
589 | ||
590 | #define PA_ENET_RXD ((ushort)0x0004) | |
591 | #define PA_ENET_TXD ((ushort)0x0008) | |
592 | #define PA_ENET_TCLK ((ushort)0x0400) | |
593 | #define PA_ENET_RCLK ((ushort)0x0200) | |
594 | ||
595 | #define PB_ENET_TENA ((uint)0x00002000) | |
596 | ||
597 | #define PC_ENET_CLSN ((ushort)0x0040) | |
598 | #define PC_ENET_RENA ((ushort)0x0080) | |
599 | ||
600 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
601 | #define SICR_ENET_CLKRT ((uint)0x00002e00) | |
602 | ||
603 | #endif /* CONFIG_FADS823FADS */ | |
604 | ||
605 | /*** FADS850SAR ********************************************************/ | |
606 | ||
607 | #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) | |
608 | /* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of | |
609 | * this may be unique to the FADS850SAR configuration. | |
610 | * Note TENA is on Port B. | |
611 | */ | |
612 | #define PROFF_ENET PROFF_SCC2 | |
613 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
614 | #define SCC_ENET 1 | |
615 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
616 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
617 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
618 | #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ | |
619 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
620 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
621 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
622 | ||
623 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
624 | #define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ | |
625 | #endif /* CONFIG_FADS850SAR */ | |
626 | ||
627 | /*** FADS860T********************************************************/ | |
628 | ||
180d3f74 WD |
629 | #if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) |
630 | /* | |
631 | * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. | |
fe8c2806 | 632 | */ |
fe8c2806 | 633 | #ifdef CONFIG_SCC1_ENET |
180d3f74 | 634 | |
fe8c2806 | 635 | #define SCC_ENET 0 |
180d3f74 | 636 | |
fe8c2806 WD |
637 | #define PROFF_ENET PROFF_SCC1 |
638 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
639 | ||
640 | #define PA_ENET_RXD ((ushort)0x0001) | |
641 | #define PA_ENET_TXD ((ushort)0x0002) | |
642 | #define PA_ENET_TCLK ((ushort)0x0100) | |
643 | #define PA_ENET_RCLK ((ushort)0x0200) | |
644 | ||
645 | #define PB_ENET_TENA ((uint)0x00001000) | |
646 | ||
647 | #define PC_ENET_CLSN ((ushort)0x0010) | |
648 | #define PC_ENET_RENA ((ushort)0x0020) | |
649 | ||
650 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
651 | #define SICR_ENET_CLKRT ((uint)0x0000002c) | |
652 | ||
180d3f74 WD |
653 | #endif /* CONFIG_SCC1_ETHERNET */ |
654 | ||
655 | /* | |
1114257c WD |
656 | * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS |
657 | * with ethernet on FEC. | |
fe8c2806 WD |
658 | */ |
659 | ||
660 | #ifdef CONFIG_FEC_ENET | |
180d3f74 WD |
661 | #define FEC_ENET /* Use FEC for Ethernet */ |
662 | #endif /* CONFIG_FEC_ENET */ | |
fe8c2806 | 663 | |
180d3f74 | 664 | #endif /* CONFIG_FADS && CONFIG_MPC86x */ |
fe8c2806 | 665 | |
384ae025 | 666 | /*** FPS850L, FPS860L ************************************************/ |
fe8c2806 | 667 | |
384ae025 | 668 | #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) |
fe8c2806 | 669 | /* Bits in parallel I/O port registers that have to be set/cleared |
384ae025 | 670 | * to configure the pins for SCC2 use. |
fe8c2806 WD |
671 | */ |
672 | #define PROFF_ENET PROFF_SCC2 | |
673 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
674 | #define SCC_ENET 1 | |
675 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
676 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
677 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
678 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
679 | ||
680 | #define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ | |
681 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
682 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
683 | ||
684 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to | |
685 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
686 | */ | |
687 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
688 | #define SICR_ENET_CLKRT ((uint)0x00002600) | |
384ae025 | 689 | #endif /* CONFIG_FPS850L, CONFIG_FPS860L */ |
fe8c2806 WD |
690 | |
691 | /*** GEN860T **********************************************************/ | |
692 | #if defined(CONFIG_GEN860T) | |
693 | #undef SCC_ENET | |
694 | #define FEC_ENET | |
695 | ||
53677ef1 WD |
696 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ |
697 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
698 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
699 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
700 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
701 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
702 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
703 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
704 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
705 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
706 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
707 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
708 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
fe8c2806 WD |
709 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ |
710 | #endif /* CONFIG_GEN860T */ | |
711 | ||
712 | /*** GENIETV ********************************************************/ | |
713 | ||
714 | #if defined(CONFIG_GENIETV) | |
715 | /* Ethernet is only on SCC2 */ | |
716 | ||
717 | #define CONFIG_SCC2_ENET | |
718 | #define PROFF_ENET PROFF_SCC2 | |
719 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
720 | #define SCC_ENET 1 | |
721 | #define CPMVEC_ENET CPMVEC_SCC2 | |
722 | ||
723 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
724 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
725 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
726 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
727 | ||
728 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
729 | ||
730 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
731 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
732 | ||
733 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
734 | #define SICR_ENET_CLKRT ((uint)0x00002e00) | |
735 | ||
736 | #endif /* CONFIG_GENIETV */ | |
737 | ||
fe8c2806 WD |
738 | /*** HERMES-PRO ******************************************************/ |
739 | ||
740 | /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ | |
741 | ||
742 | #ifdef CONFIG_HERMES | |
743 | ||
744 | #define FEC_ENET /* use FEC for EThernet */ | |
745 | #undef SCC_ENET | |
746 | ||
747 | ||
748 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
749 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
750 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
751 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
752 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
753 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
754 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
755 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
756 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
757 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
758 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
759 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
760 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
761 | ||
762 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
763 | ||
764 | #endif /* CONFIG_HERMES */ | |
765 | ||
fe8c2806 WD |
766 | /*** ICU862 **********************************************************/ |
767 | ||
768 | #if defined(CONFIG_ICU862) | |
769 | ||
770 | #ifdef CONFIG_FEC_ENET | |
771 | #define FEC_ENET /* use FEC for EThernet */ | |
772 | #endif /* CONFIG_FEC_ETHERNET */ | |
773 | ||
774 | #endif /* CONFIG_ICU862 */ | |
775 | ||
776 | /*** IP860 **********************************************************/ | |
777 | ||
778 | #if defined(CONFIG_IP860) | |
779 | /* Bits in parallel I/O port registers that have to be set/cleared | |
780 | * to configure the pins for SCC1 use. | |
781 | */ | |
782 | #define PROFF_ENET PROFF_SCC1 | |
783 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
784 | #define SCC_ENET 0 | |
785 | #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ | |
786 | #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ | |
787 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
788 | #define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ | |
789 | ||
790 | #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ | |
791 | #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ | |
792 | #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ | |
793 | ||
794 | #define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ | |
795 | #define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ | |
796 | ||
797 | /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to | |
798 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
799 | */ | |
800 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
801 | #define SICR_ENET_CLKRT ((uint)0x0000002C) | |
802 | #endif /* CONFIG_IP860 */ | |
803 | ||
804 | /*** IVMS8 **********************************************************/ | |
805 | ||
806 | /* The IVMS8 uses the FEC on a MPC860T for Ethernet */ | |
807 | ||
808 | #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) | |
809 | ||
810 | #define FEC_ENET /* use FEC for EThernet */ | |
811 | #undef SCC_ENET | |
812 | ||
813 | #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ | |
814 | ||
815 | #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ | |
816 | ||
817 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
818 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
819 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
820 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
821 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
822 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
823 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
824 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
825 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
826 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
827 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
828 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
829 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
830 | ||
831 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
832 | ||
833 | #endif /* CONFIG_IVMS8, CONFIG_IVML24 */ | |
834 | ||
0608e04d WD |
835 | /*** KUP4K, KUP4X ****************************************************/ |
836 | /* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ | |
56f94be3 | 837 | |
0608e04d | 838 | #if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) |
56f94be3 WD |
839 | |
840 | #define FEC_ENET /* use FEC for EThernet */ | |
841 | #undef SCC_ENET | |
842 | ||
843 | #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ | |
844 | ||
845 | #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ | |
846 | ||
847 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
848 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
849 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
850 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
851 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
852 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
853 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
854 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
855 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
856 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
857 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
858 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
859 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
860 | ||
861 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
862 | ||
863 | #endif /* CONFIG_KUP4K */ | |
864 | ||
fe8c2806 WD |
865 | /*** LWMON **********************************************************/ |
866 | ||
281e00a3 | 867 | #if defined(CONFIG_LWMON) |
fe8c2806 WD |
868 | /* Bits in parallel I/O port registers that have to be set/cleared |
869 | * to configure the pins for SCC2 use. | |
870 | */ | |
871 | #define PROFF_ENET PROFF_SCC2 | |
872 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
873 | #define SCC_ENET 1 | |
874 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
875 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
876 | #define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ | |
877 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
878 | ||
879 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
880 | ||
881 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
882 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
883 | ||
884 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to | |
885 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
886 | */ | |
887 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
888 | #define SICR_ENET_CLKRT ((uint)0x00003E00) | |
889 | #endif /* CONFIG_LWMON */ | |
890 | ||
891 | /*** NX823 ***********************************************/ | |
892 | ||
893 | #if defined(CONFIG_NX823) | |
894 | /* Bits in parallel I/O port registers that have to be set/cleared | |
895 | * to configure the pins for SCC1 use. | |
896 | */ | |
897 | #define PROFF_ENET PROFF_SCC2 | |
898 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
899 | #define SCC_ENET 1 | |
7c7a23bd WD |
900 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ |
901 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
902 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
903 | #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ | |
fe8c2806 | 904 | |
7c7a23bd | 905 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ |
fe8c2806 | 906 | |
7c7a23bd WD |
907 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ |
908 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
fe8c2806 WD |
909 | |
910 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
911 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
912 | */ | |
7c7a23bd WD |
913 | #define SICR_ENET_MASK ((uint)0x0000ff00) |
914 | #define SICR_ENET_CLKRT ((uint)0x00002f00) | |
fe8c2806 WD |
915 | |
916 | #endif /* CONFIG_NX823 */ | |
917 | ||
918 | /*** MBX ************************************************************/ | |
919 | ||
920 | #ifdef CONFIG_MBX | |
921 | /* Bits in parallel I/O port registers that have to be set/cleared | |
922 | * to configure the pins for SCC1 use. The TCLK and RCLK seem unique | |
923 | * to the MBX860 board. Any two of the four available clocks could be | |
924 | * used, and the MPC860 cookbook manual has an example using different | |
925 | * clock pins. | |
926 | */ | |
927 | #define PROFF_ENET PROFF_SCC1 | |
928 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
929 | #define SCC_ENET 0 | |
930 | #define PA_ENET_RXD ((ushort)0x0001) | |
931 | #define PA_ENET_TXD ((ushort)0x0002) | |
932 | #define PA_ENET_TCLK ((ushort)0x0200) | |
933 | #define PA_ENET_RCLK ((ushort)0x0800) | |
934 | #define PC_ENET_TENA ((ushort)0x0001) | |
935 | #define PC_ENET_CLSN ((ushort)0x0010) | |
936 | #define PC_ENET_RENA ((ushort)0x0020) | |
937 | ||
938 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to | |
939 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
940 | */ | |
941 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
942 | #define SICR_ENET_CLKRT ((uint)0x0000003d) | |
943 | #endif /* CONFIG_MBX */ | |
944 | ||
d044954f | 945 | /*** KM8XX *********************************************************/ |
381e4e63 | 946 | |
d044954f | 947 | /* The KM8XX Service Module uses SCC3 for Ethernet */ |
381e4e63 | 948 | |
d044954f | 949 | #ifdef CONFIG_KM8XX |
381e4e63 HS |
950 | #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ |
951 | #define CPM_CR_ENET CPM_CR_CH_SCC3 | |
952 | #define SCC_ENET 2 | |
953 | #define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ | |
954 | #define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ | |
955 | #define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ | |
956 | #define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ | |
957 | ||
958 | #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ | |
959 | ||
960 | #define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ | |
961 | #define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ | |
962 | ||
963 | /* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to | |
964 | * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. | |
965 | */ | |
966 | #define SICR_ENET_MASK ((uint)0x00FF0000) | |
967 | #define SICR_ENET_CLKRT ((uint)0x00250000) | |
d044954f | 968 | #endif /* CONFIG_KM8XX */ |
381e4e63 HS |
969 | |
970 | ||
fe8c2806 WD |
971 | /*** MHPC ********************************************************/ |
972 | ||
973 | #if defined(CONFIG_MHPC) | |
974 | /* This ENET stuff is for the MHPC with ethernet on SCC2. | |
975 | * Note TENA is on Port B. | |
976 | */ | |
977 | #define PROFF_ENET PROFF_SCC2 | |
978 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
979 | #define SCC_ENET 1 | |
980 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
981 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
982 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
983 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
984 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
985 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
986 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
987 | ||
988 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
989 | #define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ | |
990 | #endif /* CONFIG_MHPC */ | |
991 | ||
608c9146 WD |
992 | /*** NETVIA *******************************************************/ |
993 | ||
dc7c9a1a WD |
994 | /* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ |
995 | #if ( defined CONFIG_SVM_SC8xx ) | |
996 | # ifndef CONFIG_FEC_ENET | |
997 | ||
998 | #define PROFF_ENET PROFF_SCC2 | |
999 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
1000 | #define SCC_ENET 1 | |
1001 | ||
1002 | /* Bits in parallel I/O port registers that have to be set/cleared | |
1003 | * * * * to configure the pins for SCC2 use. | |
1004 | * * * */ | |
1005 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
1006 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
1007 | #define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ | |
1008 | #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ | |
1009 | ||
1010 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
1011 | ||
1012 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
1013 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
1014 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
1015 | * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
1016 | * * * */ | |
1017 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
1018 | #define SICR_ENET_CLKRT ((uint)0x00003700) | |
1019 | ||
1020 | # else /* Use FEC for Fast Ethernet */ | |
1021 | ||
1022 | #undef SCC_ENET | |
1023 | #define FEC_ENET | |
1024 | ||
1025 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
1026 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
1027 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
1028 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
1029 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
1030 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
1031 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
1032 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
1033 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
1034 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
1035 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
1036 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
1037 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
1038 | ||
1039 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
1040 | ||
1041 | # endif /* CONFIG_FEC_ENET */ | |
1042 | #endif /* CONFIG_SVM_SC8xx */ | |
8bde7f77 WD |
1043 | |
1044 | ||
608c9146 WD |
1045 | #if defined(CONFIG_NETVIA) |
1046 | /* Bits in parallel I/O port registers that have to be set/cleared | |
1047 | * to configure the pins for SCC2 use. | |
1048 | */ | |
1049 | #define PROFF_ENET PROFF_SCC2 | |
1050 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
1051 | #define SCC_ENET 1 | |
1052 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
1053 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
1054 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
1055 | #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ | |
1056 | ||
993cad93 WD |
1057 | #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 |
1058 | # define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ | |
1059 | #elif CONFIG_NETVIA_VERSION >= 2 | |
1060 | # define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ | |
1061 | #endif | |
1062 | ||
608c9146 WD |
1063 | #define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ |
1064 | ||
1065 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
1066 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
1067 | ||
1068 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
1069 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
1070 | */ | |
1071 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
1072 | #define SICR_ENET_CLKRT ((uint)0x00002f00) | |
1073 | ||
1074 | #endif /* CONFIG_NETVIA */ | |
1075 | ||
3bbc899f WD |
1076 | /*** QS850/QS823 ***************************************************/ |
1077 | ||
1078 | #if defined(CONFIG_QS850) || defined(CONFIG_QS823) | |
1079 | #undef FEC_ENET /* Don't use FEC for EThernet */ | |
1080 | ||
1081 | #define PROFF_ENET PROFF_SCC2 | |
1082 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
1083 | #define SCC_ENET 1 | |
1084 | ||
1085 | #define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ | |
1086 | #define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ | |
1087 | #define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ | |
1088 | #define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ | |
1089 | #define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ | |
1090 | #define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ | |
1091 | #define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ | |
1092 | #define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ | |
1093 | #define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ | |
1094 | #define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ | |
1095 | ||
1096 | /* SCC2 TXCLK from CLK2 | |
1097 | * SCC2 RXCLK from CLK4 | |
1098 | * SCC2 Connected to NMSI */ | |
1099 | #define SICR_ENET_MASK ((uint)0x00007F00) | |
1100 | #define SICR_ENET_CLKRT ((uint)0x00003D00) | |
1101 | ||
1102 | #endif /* CONFIG_QS850/QS823 */ | |
1103 | ||
1104 | /*** QS860T ***************************************************/ | |
1105 | ||
1106 | #ifdef CONFIG_QS860T | |
1107 | #ifdef CONFIG_FEC_ENET | |
1108 | #define FEC_ENET /* use FEC for EThernet */ | |
1109 | #endif /* CONFIG_FEC_ETHERNET */ | |
1110 | ||
1111 | /* This ENET stuff is for GTH 10 Mbit ( SCC ) */ | |
1112 | #define PROFF_ENET PROFF_SCC1 | |
1113 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
1114 | #define SCC_ENET 0 | |
1115 | ||
1116 | #define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ | |
1117 | #define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ | |
1118 | #define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ | |
1119 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ | |
1120 | #define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ | |
1121 | #define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ | |
1122 | #define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ | |
1123 | ||
1124 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
1125 | /* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ | |
1126 | #define SICR_ENET_CLKRT ((uint)0x0000003D) | |
1127 | ||
1128 | #endif /* CONFIG_QS860T */ | |
1129 | ||
fe8c2806 WD |
1130 | /*** RPXCLASSIC *****************************************************/ |
1131 | ||
1132 | #ifdef CONFIG_RPXCLASSIC | |
1133 | ||
1134 | #ifdef CONFIG_FEC_ENET | |
1135 | ||
1136 | # define FEC_ENET /* use FEC for EThernet */ | |
1137 | # undef SCC_ENET | |
1138 | ||
1139 | #else /* ! CONFIG_FEC_ENET */ | |
1140 | ||
1141 | /* Bits in parallel I/O port registers that have to be set/cleared | |
1142 | * to configure the pins for SCC1 use. | |
1143 | */ | |
1144 | #define PROFF_ENET PROFF_SCC1 | |
1145 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
1146 | #define SCC_ENET 0 | |
1147 | #define PA_ENET_RXD ((ushort)0x0001) | |
1148 | #define PA_ENET_TXD ((ushort)0x0002) | |
1149 | #define PA_ENET_TCLK ((ushort)0x0200) | |
1150 | #define PA_ENET_RCLK ((ushort)0x0800) | |
1151 | #define PB_ENET_TENA ((uint)0x00001000) | |
1152 | #define PC_ENET_CLSN ((ushort)0x0010) | |
1153 | #define PC_ENET_RENA ((ushort)0x0020) | |
1154 | ||
1155 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to | |
1156 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
1157 | */ | |
1158 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
1159 | #define SICR_ENET_CLKRT ((uint)0x0000003d) | |
1160 | ||
1161 | #endif /* CONFIG_FEC_ENET */ | |
1162 | ||
1163 | #endif /* CONFIG_RPXCLASSIC */ | |
1164 | ||
1165 | /*** RPXLITE ********************************************************/ | |
1166 | ||
1167 | #ifdef CONFIG_RPXLITE | |
1168 | /* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of | |
1169 | * this may be unique to the RPX-Lite configuration. | |
1170 | * Note TENA is on Port B. | |
1171 | */ | |
1172 | #define PROFF_ENET PROFF_SCC2 | |
1173 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
1174 | #define SCC_ENET 1 | |
1175 | #define PA_ENET_RXD ((ushort)0x0004) | |
1176 | #define PA_ENET_TXD ((ushort)0x0008) | |
1177 | #define PA_ENET_TCLK ((ushort)0x0200) | |
1178 | #define PA_ENET_RCLK ((ushort)0x0800) | |
73a8b27c WD |
1179 | #if defined(CONFIG_RMU) |
1180 | #define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ | |
1181 | #else | |
fe8c2806 | 1182 | #define PB_ENET_TENA ((uint)0x00002000) |
73a8b27c | 1183 | #endif |
fe8c2806 WD |
1184 | #define PC_ENET_CLSN ((ushort)0x0040) |
1185 | #define PC_ENET_RENA ((ushort)0x0080) | |
1186 | ||
1187 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
1188 | #define SICR_ENET_CLKRT ((uint)0x00003d00) | |
1189 | #endif /* CONFIG_RPXLITE */ | |
1190 | ||
1191 | /*** SM850 *********************************************************/ | |
1192 | ||
1193 | /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ | |
1194 | ||
1195 | #ifdef CONFIG_SM850 | |
1196 | #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ | |
1197 | #define CPM_CR_ENET CPM_CR_CH_SCC3 | |
1198 | #define SCC_ENET 2 | |
1199 | #define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ | |
1200 | #define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ | |
1201 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
1202 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
1203 | ||
1204 | #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ | |
1205 | #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ | |
1206 | ||
1207 | #define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ | |
1208 | #define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ | |
1209 | ||
1210 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
1211 | * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. | |
1212 | */ | |
1213 | #define SICR_ENET_MASK ((uint)0x00FF0000) | |
1214 | #define SICR_ENET_CLKRT ((uint)0x00260000) | |
1215 | #endif /* CONFIG_SM850 */ | |
1216 | ||
1217 | /*** SPD823TS ******************************************************/ | |
1218 | ||
1219 | #ifdef CONFIG_SPD823TS | |
1220 | /* Bits in parallel I/O port registers that have to be set/cleared | |
1221 | * to configure the pins for SCC2 use. | |
1222 | */ | |
1223 | #define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ | |
1224 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
1225 | #define SCC_ENET 1 | |
1226 | #define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ | |
1227 | #define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ | |
1228 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
1229 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
1230 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
1231 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
1232 | ||
1233 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
1234 | ||
1235 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
1236 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
1237 | #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ | |
1238 | ||
1239 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to | |
1240 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
1241 | */ | |
1242 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
1243 | #define SICR_ENET_CLKRT ((uint)0x00002E00) | |
1244 | #endif /* CONFIG_SPD823TS */ | |
1245 | ||
1246 | /*** SXNI855T ******************************************************/ | |
1247 | ||
1248 | #if defined(CONFIG_SXNI855T) | |
1249 | ||
1250 | #ifdef CONFIG_FEC_ENET | |
1251 | #define FEC_ENET /* use FEC for Ethernet */ | |
1252 | #endif /* CONFIG_FEC_ETHERNET */ | |
1253 | ||
1254 | #endif /* CONFIG_SXNI855T */ | |
1255 | ||
1b0757ec | 1256 | /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ |
fe8c2806 WD |
1257 | |
1258 | #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ | |
71f95118 | 1259 | defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ |
1b0757ec WD |
1260 | defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ |
1261 | defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ | |
1262 | defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ | |
1263 | defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2) | |
090eb735 | 1264 | |
fe8c2806 WD |
1265 | /* Bits in parallel I/O port registers that have to be set/cleared |
1266 | * to configure the pins for SCC2 use. | |
1267 | */ | |
1268 | #define PROFF_ENET PROFF_SCC2 | |
1269 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
2b4f778f | 1270 | #if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ |
fe8c2806 | 1271 | #define SCC_ENET 1 |
2b4f778f | 1272 | #endif |
fe8c2806 WD |
1273 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ |
1274 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
1275 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
1276 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
1277 | ||
1278 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
1279 | ||
1280 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
1281 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
1282 | #if defined(CONFIG_R360MPI) | |
1283 | #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ | |
1284 | #endif /* CONFIG_R360MPI */ | |
1285 | ||
1286 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
1287 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
1288 | */ | |
1289 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
1290 | #define SICR_ENET_CLKRT ((uint)0x00002600) | |
090eb735 MK |
1291 | |
1292 | # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ | |
1293 | #define FEC_ENET | |
1294 | # endif /* CONFIG_FEC_ENET */ | |
1295 | ||
71f95118 | 1296 | #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ |
fe8c2806 | 1297 | |
d4ca31c4 | 1298 | /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ |
fe8c2806 | 1299 | |
71f95118 WD |
1300 | #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ |
1301 | defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ | |
d4ca31c4 WD |
1302 | defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ |
1303 | defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) | |
fe8c2806 WD |
1304 | |
1305 | # ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ | |
1306 | ||
1307 | /* Bits in parallel I/O port registers that have to be set/cleared | |
1308 | * to configure the pins for SCC1 use. | |
1309 | */ | |
1310 | #define PROFF_ENET PROFF_SCC1 | |
1311 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
1312 | #define SCC_ENET 0 | |
1313 | #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ | |
1314 | #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ | |
1315 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
1316 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
1317 | ||
1318 | #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ | |
1319 | #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ | |
1320 | #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ | |
1321 | ||
1322 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
1323 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
1324 | */ | |
1325 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
1326 | #define SICR_ENET_CLKRT ((uint)0x00000026) | |
1327 | ||
1328 | # endif /* CONFIG_SCC1_ENET */ | |
1329 | ||
1330 | # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ | |
1331 | ||
1332 | #define FEC_ENET | |
1333 | ||
1334 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
1335 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
1336 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
1337 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
1338 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
1339 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
1340 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
1341 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
1342 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
1343 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
1344 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
1345 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
1346 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
1347 | ||
1348 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
1349 | ||
1350 | # endif /* CONFIG_FEC_ENET */ | |
71f95118 | 1351 | #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ |
fe8c2806 | 1352 | |
608c9146 WD |
1353 | /*** V37 **********************************************************/ |
1354 | ||
1355 | #ifdef CONFIG_V37 | |
1356 | /* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of | |
1357 | * this may be unique to the Marel V37 configuration. | |
1358 | * Note TENA is on Port B. | |
fe8c2806 WD |
1359 | */ |
1360 | #define PROFF_ENET PROFF_SCC2 | |
1361 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
1362 | #define SCC_ENET 1 | |
608c9146 WD |
1363 | #define PA_ENET_RXD ((ushort)0x0004) |
1364 | #define PA_ENET_TXD ((ushort)0x0008) | |
1365 | #define PA_ENET_TCLK ((ushort)0x0400) | |
1366 | #define PA_ENET_RCLK ((ushort)0x0200) | |
1367 | #define PB_ENET_TENA ((uint)0x00002000) | |
1368 | #define PC_ENET_CLSN ((ushort)0x0040) | |
1369 | #define PC_ENET_RENA ((ushort)0x0080) | |
fe8c2806 | 1370 | |
fe8c2806 | 1371 | #define SICR_ENET_MASK ((uint)0x0000ff00) |
608c9146 WD |
1372 | #define SICR_ENET_CLKRT ((uint)0x00002e00) |
1373 | #endif /* CONFIG_V37 */ | |
fe8c2806 | 1374 | |
3bbc899f | 1375 | |
fe8c2806 WD |
1376 | /*********************************************************************/ |
1377 | ||
1378 | /* SCC Event register as used by Ethernet. | |
1379 | */ | |
1380 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | |
1381 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | |
1382 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | |
1383 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | |
1384 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | |
1385 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | |
1386 | ||
1387 | /* SCC Mode Register (PSMR) as used by Ethernet. | |
1388 | */ | |
1389 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | |
1390 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | |
1391 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | |
1392 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | |
1393 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | |
1394 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | |
1395 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | |
1396 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | |
1397 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | |
1398 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | |
1399 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | |
1400 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | |
1401 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | |
1402 | ||
1403 | /* Buffer descriptor control/status used by Ethernet receive. | |
1404 | */ | |
1405 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | |
1406 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | |
1407 | #define BD_ENET_RX_INTR ((ushort)0x1000) | |
1408 | #define BD_ENET_RX_LAST ((ushort)0x0800) | |
1409 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | |
1410 | #define BD_ENET_RX_MISS ((ushort)0x0100) | |
1411 | #define BD_ENET_RX_LG ((ushort)0x0020) | |
1412 | #define BD_ENET_RX_NO ((ushort)0x0010) | |
1413 | #define BD_ENET_RX_SH ((ushort)0x0008) | |
1414 | #define BD_ENET_RX_CR ((ushort)0x0004) | |
1415 | #define BD_ENET_RX_OV ((ushort)0x0002) | |
1416 | #define BD_ENET_RX_CL ((ushort)0x0001) | |
1417 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | |
1418 | ||
1419 | /* Buffer descriptor control/status used by Ethernet transmit. | |
1420 | */ | |
1421 | #define BD_ENET_TX_READY ((ushort)0x8000) | |
1422 | #define BD_ENET_TX_PAD ((ushort)0x4000) | |
1423 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | |
1424 | #define BD_ENET_TX_INTR ((ushort)0x1000) | |
1425 | #define BD_ENET_TX_LAST ((ushort)0x0800) | |
1426 | #define BD_ENET_TX_TC ((ushort)0x0400) | |
1427 | #define BD_ENET_TX_DEF ((ushort)0x0200) | |
1428 | #define BD_ENET_TX_HB ((ushort)0x0100) | |
1429 | #define BD_ENET_TX_LC ((ushort)0x0080) | |
1430 | #define BD_ENET_TX_RL ((ushort)0x0040) | |
1431 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | |
1432 | #define BD_ENET_TX_UN ((ushort)0x0002) | |
1433 | #define BD_ENET_TX_CSL ((ushort)0x0001) | |
1434 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | |
1435 | ||
1436 | /* SCC as UART | |
1437 | */ | |
1438 | typedef struct scc_uart { | |
1439 | sccp_t scc_genscc; | |
1440 | uint scc_res1; /* Reserved */ | |
1441 | uint scc_res2; /* Reserved */ | |
1442 | ushort scc_maxidl; /* Maximum idle chars */ | |
1443 | ushort scc_idlc; /* temp idle counter */ | |
1444 | ushort scc_brkcr; /* Break count register */ | |
1445 | ushort scc_parec; /* receive parity error counter */ | |
1446 | ushort scc_frmec; /* receive framing error counter */ | |
1447 | ushort scc_nosec; /* receive noise counter */ | |
1448 | ushort scc_brkec; /* receive break condition counter */ | |
1449 | ushort scc_brkln; /* last received break length */ | |
1450 | ushort scc_uaddr1; /* UART address character 1 */ | |
1451 | ushort scc_uaddr2; /* UART address character 2 */ | |
1452 | ushort scc_rtemp; /* Temp storage */ | |
1453 | ushort scc_toseq; /* Transmit out of sequence char */ | |
1454 | ushort scc_char1; /* control character 1 */ | |
1455 | ushort scc_char2; /* control character 2 */ | |
1456 | ushort scc_char3; /* control character 3 */ | |
1457 | ushort scc_char4; /* control character 4 */ | |
1458 | ushort scc_char5; /* control character 5 */ | |
1459 | ushort scc_char6; /* control character 6 */ | |
1460 | ushort scc_char7; /* control character 7 */ | |
1461 | ushort scc_char8; /* control character 8 */ | |
1462 | ushort scc_rccm; /* receive control character mask */ | |
1463 | ushort scc_rccr; /* receive control character register */ | |
1464 | ushort scc_rlbc; /* receive last break character */ | |
1465 | } scc_uart_t; | |
1466 | ||
1467 | /* SCC Event and Mask registers when it is used as a UART. | |
1468 | */ | |
1469 | #define UART_SCCM_GLR ((ushort)0x1000) | |
1470 | #define UART_SCCM_GLT ((ushort)0x0800) | |
1471 | #define UART_SCCM_AB ((ushort)0x0200) | |
1472 | #define UART_SCCM_IDL ((ushort)0x0100) | |
1473 | #define UART_SCCM_GRA ((ushort)0x0080) | |
1474 | #define UART_SCCM_BRKE ((ushort)0x0040) | |
1475 | #define UART_SCCM_BRKS ((ushort)0x0020) | |
1476 | #define UART_SCCM_CCR ((ushort)0x0008) | |
1477 | #define UART_SCCM_BSY ((ushort)0x0004) | |
1478 | #define UART_SCCM_TX ((ushort)0x0002) | |
1479 | #define UART_SCCM_RX ((ushort)0x0001) | |
1480 | ||
1481 | /* The SCC PSMR when used as a UART. | |
1482 | */ | |
1483 | #define SCU_PSMR_FLC ((ushort)0x8000) | |
1484 | #define SCU_PSMR_SL ((ushort)0x4000) | |
1485 | #define SCU_PSMR_CL ((ushort)0x3000) | |
1486 | #define SCU_PSMR_UM ((ushort)0x0c00) | |
1487 | #define SCU_PSMR_FRZ ((ushort)0x0200) | |
1488 | #define SCU_PSMR_RZS ((ushort)0x0100) | |
1489 | #define SCU_PSMR_SYN ((ushort)0x0080) | |
1490 | #define SCU_PSMR_DRT ((ushort)0x0040) | |
1491 | #define SCU_PSMR_PEN ((ushort)0x0010) | |
1492 | #define SCU_PSMR_RPM ((ushort)0x000c) | |
1493 | #define SCU_PSMR_REVP ((ushort)0x0008) | |
1494 | #define SCU_PSMR_TPM ((ushort)0x0003) | |
1495 | #define SCU_PSMR_TEVP ((ushort)0x0003) | |
1496 | ||
1497 | /* CPM Transparent mode SCC. | |
1498 | */ | |
1499 | typedef struct scc_trans { | |
1500 | sccp_t st_genscc; | |
1501 | uint st_cpres; /* Preset CRC */ | |
1502 | uint st_cmask; /* Constant mask for CRC */ | |
1503 | } scc_trans_t; | |
1504 | ||
1505 | #define BD_SCC_TX_LAST ((ushort)0x0800) | |
1506 | ||
1507 | /* IIC parameter RAM. | |
1508 | */ | |
1509 | typedef struct iic { | |
1510 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | |
1511 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | |
1512 | u_char iic_rfcr; /* Rx function code */ | |
1513 | u_char iic_tfcr; /* Tx function code */ | |
1514 | ushort iic_mrblr; /* Max receive buffer length */ | |
1515 | uint iic_rstate; /* Internal */ | |
1516 | uint iic_rdp; /* Internal */ | |
1517 | ushort iic_rbptr; /* Internal */ | |
1518 | ushort iic_rbc; /* Internal */ | |
1519 | uint iic_rxtmp; /* Internal */ | |
1520 | uint iic_tstate; /* Internal */ | |
1521 | uint iic_tdp; /* Internal */ | |
1522 | ushort iic_tbptr; /* Internal */ | |
1523 | ushort iic_tbc; /* Internal */ | |
1524 | uint iic_txtmp; /* Internal */ | |
1525 | uint iic_res; /* reserved */ | |
1526 | ushort iic_rpbase; /* Relocation pointer */ | |
1527 | ushort iic_res2; /* reserved */ | |
1528 | } iic_t; | |
1529 | ||
1530 | /* SPI parameter RAM. | |
1531 | */ | |
1532 | typedef struct spi { | |
1533 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | |
1534 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | |
1535 | u_char spi_rfcr; /* Rx function code */ | |
1536 | u_char spi_tfcr; /* Tx function code */ | |
1537 | ushort spi_mrblr; /* Max receive buffer length */ | |
1538 | uint spi_rstate; /* Internal */ | |
1539 | uint spi_rdp; /* Internal */ | |
1540 | ushort spi_rbptr; /* Internal */ | |
1541 | ushort spi_rbc; /* Internal */ | |
1542 | uint spi_rxtmp; /* Internal */ | |
1543 | uint spi_tstate; /* Internal */ | |
1544 | uint spi_tdp; /* Internal */ | |
1545 | ushort spi_tbptr; /* Internal */ | |
1546 | ushort spi_tbc; /* Internal */ | |
1547 | uint spi_txtmp; /* Internal */ | |
1548 | uint spi_res; | |
1549 | ushort spi_rpbase; /* Relocation pointer */ | |
1550 | ushort spi_res2; | |
1551 | } spi_t; | |
1552 | ||
1553 | /* SPI Mode register. | |
1554 | */ | |
1555 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | |
1556 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | |
1557 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | |
1558 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | |
1559 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | |
1560 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | |
1561 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | |
1562 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | |
1563 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | |
1564 | ||
1565 | #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) | |
1566 | #define SPMODE_PM(x) ((x) &0xF) | |
1567 | ||
1568 | /* HDLC parameter RAM. | |
1569 | */ | |
1570 | ||
1571 | typedef struct hdlc_pram_s { | |
1572 | /* | |
1573 | * SCC parameter RAM | |
1574 | */ | |
1575 | ushort rbase; /* Rx Buffer descriptor base address */ | |
1576 | ushort tbase; /* Tx Buffer descriptor base address */ | |
1577 | uchar rfcr; /* Rx function code */ | |
1578 | uchar tfcr; /* Tx function code */ | |
1579 | ushort mrblr; /* Rx buffer length */ | |
1580 | ulong rstate; /* Rx internal state */ | |
1581 | ulong rptr; /* Rx internal data pointer */ | |
1582 | ushort rbptr; /* rb BD Pointer */ | |
1583 | ushort rcount; /* Rx internal byte count */ | |
1584 | ulong rtemp; /* Rx temp */ | |
1585 | ulong tstate; /* Tx internal state */ | |
1586 | ulong tptr; /* Tx internal data pointer */ | |
1587 | ushort tbptr; /* Tx BD pointer */ | |
1588 | ushort tcount; /* Tx byte count */ | |
1589 | ulong ttemp; /* Tx temp */ | |
1590 | ulong rcrc; /* temp receive CRC */ | |
1591 | ulong tcrc; /* temp transmit CRC */ | |
1592 | /* | |
1593 | * HDLC specific parameter RAM | |
1594 | */ | |
1595 | uchar res[4]; /* reserved */ | |
1596 | ulong c_mask; /* CRC constant */ | |
1597 | ulong c_pres; /* CRC preset */ | |
1598 | ushort disfc; /* discarded frame counter */ | |
1599 | ushort crcec; /* CRC error counter */ | |
1600 | ushort abtsc; /* abort sequence counter */ | |
1601 | ushort nmarc; /* nonmatching address rx cnt */ | |
1602 | ushort retrc; /* frame retransmission cnt */ | |
1603 | ushort mflr; /* maximum frame length reg */ | |
1604 | ushort max_cnt; /* maximum length counter */ | |
1605 | ushort rfthr; /* received frames threshold */ | |
1606 | ushort rfcnt; /* received frames count */ | |
1607 | ushort hmask; /* user defined frm addr mask */ | |
1608 | ushort haddr1; /* user defined frm address 1 */ | |
1609 | ushort haddr2; /* user defined frm address 2 */ | |
1610 | ushort haddr3; /* user defined frm address 3 */ | |
1611 | ushort haddr4; /* user defined frm address 4 */ | |
1612 | ushort tmp; /* temp */ | |
1613 | ushort tmp_mb; /* temp */ | |
1614 | } hdlc_pram_t; | |
1615 | ||
1616 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM | |
1617 | * channels or devices. All of these are presented to the PPC core | |
1618 | * as a single interrupt. The CPM interrupt handler dispatches its | |
1619 | * own handlers, in a similar fashion to the PPC core handler. We | |
1620 | * use the table as defined in the manuals (i.e. no special high | |
1621 | * priority and SCC1 == SCCa, etc...). | |
1622 | */ | |
1623 | #define CPMVEC_NR 32 | |
7c7a23bd WD |
1624 | #define CPMVEC_OFFSET 0x00010000 |
1625 | #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) | |
1626 | #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) | |
1627 | #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) | |
1628 | #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) | |
1629 | #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) | |
1630 | #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) | |
1631 | #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) | |
1632 | #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) | |
1633 | #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) | |
1634 | #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) | |
1635 | #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) | |
1636 | #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) | |
1637 | #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) | |
1638 | #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) | |
1639 | #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) | |
1640 | #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) | |
1641 | #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) | |
1642 | #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) | |
1643 | #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) | |
1644 | #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) | |
1645 | #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) | |
1646 | #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) | |
1647 | #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) | |
1648 | #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) | |
1649 | #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) | |
1650 | #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) | |
1651 | #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) | |
1652 | #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) | |
1653 | #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) | |
fe8c2806 WD |
1654 | |
1655 | extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); | |
1656 | ||
1657 | /* CPM interrupt configuration vector. | |
1658 | */ | |
1659 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | |
1660 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | |
1661 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | |
1662 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | |
1663 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ | |
1664 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ | |
1665 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | |
1666 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | |
1667 | #endif /* __CPM_8XX__ */ |