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fe8c2806 WD |
1 | /* |
2 | * MPC8xx Communication Processor Module. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
8cba090c | 5 | * (C) Copyright 2000-2006 |
d4ca31c4 WD |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
fe8c2806 WD |
8 | * This file contains structures and information for the communication |
9 | * processor channels. Some CPM control and status is available | |
10 | * throught the MPC8xx internal memory map. See immap.h for details. | |
11 | * This file only contains what I need for the moment, not the total | |
12 | * CPM capabilities. I (or someone else) will add definitions as they | |
13 | * are needed. -- Dan | |
14 | * | |
fe8c2806 WD |
15 | */ |
16 | #ifndef __CPM_8XX__ | |
17 | #define __CPM_8XX__ | |
18 | ||
fe8c2806 WD |
19 | #include <asm/8xx_immap.h> |
20 | ||
21 | /* CPM Command register. | |
22 | */ | |
7c7a23bd WD |
23 | #define CPM_CR_RST ((ushort)0x8000) |
24 | #define CPM_CR_OPCODE ((ushort)0x0f00) | |
25 | #define CPM_CR_CHAN ((ushort)0x00f0) | |
26 | #define CPM_CR_FLG ((ushort)0x0001) | |
fe8c2806 WD |
27 | |
28 | /* Some commands (there are more...later) | |
29 | */ | |
30 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | |
31 | #define CPM_CR_INIT_RX ((ushort)0x0001) | |
32 | #define CPM_CR_INIT_TX ((ushort)0x0002) | |
33 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | |
34 | #define CPM_CR_STOP_TX ((ushort)0x0004) | |
35 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | |
36 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | |
37 | ||
38 | /* Channel numbers. | |
39 | */ | |
7c7a23bd WD |
40 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) |
41 | #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ | |
42 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) | |
43 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ | |
44 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) | |
45 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ | |
46 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) | |
47 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ | |
fe8c2806 WD |
48 | |
49 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) | |
50 | ||
51 | /* | |
52 | * DPRAM defines and allocation functions | |
53 | */ | |
54 | ||
55 | /* The dual ported RAM is multi-functional. Some areas can be (and are | |
56 | * being) used for microcode. There is an area that can only be used | |
57 | * as data ram for buffer descriptors, which is all we use right now. | |
58 | * Currently the first 512 and last 256 bytes are used for microcode. | |
59 | */ | |
6d0f6bcf | 60 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
fe8c2806 WD |
61 | |
62 | #define CPM_DATAONLY_BASE ((uint)0x0800) | |
63 | #define CPM_DATAONLY_SIZE ((uint)0x0700) | |
64 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | |
65 | ||
66 | #else | |
67 | ||
68 | #define CPM_SERIAL_BASE 0x0800 | |
69 | #define CPM_I2C_BASE 0x0820 | |
70 | #define CPM_SPI_BASE 0x0840 | |
71 | #define CPM_FEC_BASE 0x0860 | |
79536a6e | 72 | #define CPM_SERIAL2_BASE 0x08E0 |
fe8c2806 WD |
73 | #define CPM_SCC_BASE 0x0900 |
74 | #define CPM_POST_BASE 0x0980 | |
281e00a3 | 75 | #define CPM_WLKBD_BASE 0x0a00 |
fe8c2806 WD |
76 | |
77 | #endif | |
78 | ||
6d0f6bcf | 79 | #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR |
fe8c2806 | 80 | #define CPM_POST_WORD_ADDR 0x07FC |
ea909b76 | 81 | #else |
6d0f6bcf | 82 | #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR |
ea909b76 | 83 | #endif |
fe8c2806 | 84 | |
6d0f6bcf | 85 | #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR |
bdccc4fe WD |
86 | #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) |
87 | #else | |
6d0f6bcf | 88 | #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR |
bdccc4fe WD |
89 | #endif |
90 | ||
fe8c2806 WD |
91 | #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ |
92 | ||
93 | /* Export the base address of the communication processor registers | |
94 | * and dual port ram. | |
95 | */ | |
96 | extern cpm8xx_t *cpmp; /* Pointer to comm processor */ | |
97 | ||
98 | /* Buffer descriptors used by many of the CPM protocols. | |
99 | */ | |
100 | typedef struct cpm_buf_desc { | |
101 | ushort cbd_sc; /* Status and Control */ | |
102 | ushort cbd_datlen; /* Data length in buffer */ | |
103 | uint cbd_bufaddr; /* Buffer address in host memory */ | |
104 | } cbd_t; | |
105 | ||
16263087 | 106 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ |
fe8c2806 WD |
107 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ |
108 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | |
109 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | |
110 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | |
111 | #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ | |
112 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | |
113 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | |
114 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | |
115 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | |
116 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | |
117 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | |
118 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | |
119 | #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ | |
120 | ||
121 | /* Parameter RAM offsets. | |
122 | */ | |
123 | #define PROFF_SCC1 ((uint)0x0000) | |
124 | #define PROFF_IIC ((uint)0x0080) | |
a166fbca | 125 | #define PROFF_REVNUM ((uint)0x00b0) |
fe8c2806 WD |
126 | #define PROFF_SCC2 ((uint)0x0100) |
127 | #define PROFF_SPI ((uint)0x0180) | |
128 | #define PROFF_SCC3 ((uint)0x0200) | |
129 | #define PROFF_SMC1 ((uint)0x0280) | |
130 | #define PROFF_SCC4 ((uint)0x0300) | |
131 | #define PROFF_SMC2 ((uint)0x0380) | |
132 | ||
133 | /* Define enough so I can at least use the serial port as a UART. | |
fe8c2806 WD |
134 | */ |
135 | typedef struct smc_uart { | |
136 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | |
137 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | |
138 | u_char smc_rfcr; /* Rx function code */ | |
139 | u_char smc_tfcr; /* Tx function code */ | |
140 | ushort smc_mrblr; /* Max receive buffer length */ | |
141 | uint smc_rstate; /* Internal */ | |
142 | uint smc_idp; /* Internal */ | |
143 | ushort smc_rbptr; /* Internal */ | |
144 | ushort smc_ibc; /* Internal */ | |
145 | uint smc_rxtmp; /* Internal */ | |
146 | uint smc_tstate; /* Internal */ | |
147 | uint smc_tdp; /* Internal */ | |
148 | ushort smc_tbptr; /* Internal */ | |
149 | ushort smc_tbc; /* Internal */ | |
150 | uint smc_txtmp; /* Internal */ | |
151 | ushort smc_maxidl; /* Maximum idle characters */ | |
152 | ushort smc_tmpidl; /* Temporary idle counter */ | |
153 | ushort smc_brklen; /* Last received break length */ | |
154 | ushort smc_brkec; /* rcv'd break condition counter */ | |
155 | ushort smc_brkcr; /* xmt break count register */ | |
156 | ushort smc_rmask; /* Temporary bit mask */ | |
b423d055 HS |
157 | u_char res1[8]; |
158 | ushort smc_rpbase; /* Relocation pointer */ | |
fe8c2806 WD |
159 | } smc_uart_t; |
160 | ||
161 | /* Function code bits. | |
162 | */ | |
163 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ | |
164 | ||
165 | /* SMC uart mode register. | |
166 | */ | |
167 | #define SMCMR_REN ((ushort)0x0001) | |
168 | #define SMCMR_TEN ((ushort)0x0002) | |
169 | #define SMCMR_DM ((ushort)0x000c) | |
170 | #define SMCMR_SM_GCI ((ushort)0x0000) | |
171 | #define SMCMR_SM_UART ((ushort)0x0020) | |
172 | #define SMCMR_SM_TRANS ((ushort)0x0030) | |
173 | #define SMCMR_SM_MASK ((ushort)0x0030) | |
174 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | |
175 | #define SMCMR_REVD SMCMR_PM_EVEN | |
176 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | |
177 | #define SMCMR_BS SMCMR_PEN | |
178 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | |
179 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | |
180 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | |
181 | ||
182 | /* SMC2 as Centronics parallel printer. It is half duplex, in that | |
183 | * it can only receive or transmit. The parameter ram values for | |
184 | * each direction are either unique or properly overlap, so we can | |
185 | * include them in one structure. | |
186 | */ | |
187 | typedef struct smc_centronics { | |
188 | ushort scent_rbase; | |
189 | ushort scent_tbase; | |
190 | u_char scent_cfcr; | |
191 | u_char scent_smask; | |
192 | ushort scent_mrblr; | |
193 | uint scent_rstate; | |
194 | uint scent_r_ptr; | |
195 | ushort scent_rbptr; | |
196 | ushort scent_r_cnt; | |
197 | uint scent_rtemp; | |
198 | uint scent_tstate; | |
199 | uint scent_t_ptr; | |
200 | ushort scent_tbptr; | |
201 | ushort scent_t_cnt; | |
202 | uint scent_ttemp; | |
203 | ushort scent_max_sl; | |
204 | ushort scent_sl_cnt; | |
205 | ushort scent_character1; | |
206 | ushort scent_character2; | |
207 | ushort scent_character3; | |
208 | ushort scent_character4; | |
209 | ushort scent_character5; | |
210 | ushort scent_character6; | |
211 | ushort scent_character7; | |
212 | ushort scent_character8; | |
213 | ushort scent_rccm; | |
214 | ushort scent_rccr; | |
215 | } smc_cent_t; | |
216 | ||
217 | /* Centronics Status Mask Register. | |
218 | */ | |
219 | #define SMC_CENT_F ((u_char)0x08) | |
220 | #define SMC_CENT_PE ((u_char)0x04) | |
221 | #define SMC_CENT_S ((u_char)0x02) | |
222 | ||
223 | /* SMC Event and Mask register. | |
224 | */ | |
225 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | |
226 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | |
227 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ | |
228 | #define SMCM_BSY ((unsigned char)0x04) | |
229 | #define SMCM_TX ((unsigned char)0x02) | |
230 | #define SMCM_RX ((unsigned char)0x01) | |
231 | ||
232 | /* Baud rate generators. | |
233 | */ | |
234 | #define CPM_BRG_RST ((uint)0x00020000) | |
235 | #define CPM_BRG_EN ((uint)0x00010000) | |
236 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | |
237 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) | |
238 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) | |
239 | #define CPM_BRG_ATB ((uint)0x00002000) | |
240 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | |
241 | #define CPM_BRG_DIV16 ((uint)0x00000001) | |
242 | ||
243 | /* SI Clock Route Register | |
244 | */ | |
245 | #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) | |
246 | #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) | |
247 | #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) | |
248 | #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) | |
249 | #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) | |
250 | #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) | |
251 | #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) | |
252 | #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) | |
253 | ||
254 | /* SCCs. | |
255 | */ | |
256 | #define SCC_GSMRH_IRP ((uint)0x00040000) | |
257 | #define SCC_GSMRH_GDE ((uint)0x00010000) | |
258 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | |
259 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | |
260 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | |
261 | #define SCC_GSMRH_REVD ((uint)0x00002000) | |
262 | #define SCC_GSMRH_TRX ((uint)0x00001000) | |
263 | #define SCC_GSMRH_TTX ((uint)0x00000800) | |
264 | #define SCC_GSMRH_CDP ((uint)0x00000400) | |
265 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | |
266 | #define SCC_GSMRH_CDS ((uint)0x00000100) | |
267 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | |
268 | #define SCC_GSMRH_TFL ((uint)0x00000040) | |
269 | #define SCC_GSMRH_RFW ((uint)0x00000020) | |
270 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | |
271 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | |
272 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | |
273 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | |
274 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | |
275 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | |
276 | ||
277 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | |
278 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | |
279 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | |
280 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | |
281 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | |
282 | #define SCC_GSMRL_TCI ((uint)0x10000000) | |
283 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | |
284 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | |
285 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | |
286 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | |
287 | #define SCC_GSMRL_RINV ((uint)0x02000000) | |
288 | #define SCC_GSMRL_TINV ((uint)0x01000000) | |
289 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | |
290 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | |
291 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | |
292 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | |
293 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | |
294 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | |
295 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | |
296 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | |
297 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | |
298 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | |
299 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | |
300 | #define SCC_GSMRL_TEND ((uint)0x00040000) | |
301 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | |
302 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | |
303 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | |
304 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | |
305 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | |
306 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | |
307 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | |
308 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | |
309 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | |
310 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | |
311 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | |
312 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | |
313 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | |
314 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | |
315 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | |
316 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | |
317 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | |
318 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | |
319 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | |
320 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | |
321 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | |
322 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | |
323 | #define SCC_GSMRL_ENR ((uint)0x00000020) | |
324 | #define SCC_GSMRL_ENT ((uint)0x00000010) | |
325 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | |
326 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | |
327 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | |
328 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | |
329 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | |
330 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | |
331 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | |
332 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | |
333 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | |
334 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | |
335 | ||
336 | #define SCC_TODR_TOD ((ushort)0x8000) | |
337 | ||
338 | /* SCC Event and Mask register. | |
339 | */ | |
340 | #define SCCM_TXE ((unsigned char)0x10) | |
341 | #define SCCM_BSY ((unsigned char)0x04) | |
342 | #define SCCM_TX ((unsigned char)0x02) | |
343 | #define SCCM_RX ((unsigned char)0x01) | |
344 | ||
345 | typedef struct scc_param { | |
346 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | |
347 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | |
348 | u_char scc_rfcr; /* Rx function code */ | |
349 | u_char scc_tfcr; /* Tx function code */ | |
350 | ushort scc_mrblr; /* Max receive buffer length */ | |
351 | uint scc_rstate; /* Internal */ | |
352 | uint scc_idp; /* Internal */ | |
353 | ushort scc_rbptr; /* Internal */ | |
354 | ushort scc_ibc; /* Internal */ | |
355 | uint scc_rxtmp; /* Internal */ | |
356 | uint scc_tstate; /* Internal */ | |
357 | uint scc_tdp; /* Internal */ | |
358 | ushort scc_tbptr; /* Internal */ | |
359 | ushort scc_tbc; /* Internal */ | |
360 | uint scc_txtmp; /* Internal */ | |
361 | uint scc_rcrc; /* Internal */ | |
362 | uint scc_tcrc; /* Internal */ | |
363 | } sccp_t; | |
364 | ||
365 | /* Function code bits. | |
366 | */ | |
367 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ | |
368 | ||
369 | /* CPM Ethernet through SCCx. | |
370 | */ | |
371 | typedef struct scc_enet { | |
372 | sccp_t sen_genscc; | |
373 | uint sen_cpres; /* Preset CRC */ | |
374 | uint sen_cmask; /* Constant mask for CRC */ | |
375 | uint sen_crcec; /* CRC Error counter */ | |
376 | uint sen_alec; /* alignment error counter */ | |
377 | uint sen_disfc; /* discard frame counter */ | |
378 | ushort sen_pads; /* Tx short frame pad character */ | |
379 | ushort sen_retlim; /* Retry limit threshold */ | |
380 | ushort sen_retcnt; /* Retry limit counter */ | |
381 | ushort sen_maxflr; /* maximum frame length register */ | |
382 | ushort sen_minflr; /* minimum frame length register */ | |
383 | ushort sen_maxd1; /* maximum DMA1 length */ | |
384 | ushort sen_maxd2; /* maximum DMA2 length */ | |
385 | ushort sen_maxd; /* Rx max DMA */ | |
386 | ushort sen_dmacnt; /* Rx DMA counter */ | |
387 | ushort sen_maxb; /* Max BD byte count */ | |
388 | ushort sen_gaddr1; /* Group address filter */ | |
389 | ushort sen_gaddr2; | |
390 | ushort sen_gaddr3; | |
391 | ushort sen_gaddr4; | |
392 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | |
393 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | |
394 | uint sen_tbuf0rba; /* Internal */ | |
395 | uint sen_tbuf0crc; /* Internal */ | |
396 | ushort sen_tbuf0bcnt; /* Internal */ | |
397 | ushort sen_paddrh; /* physical address (MSB) */ | |
398 | ushort sen_paddrm; | |
399 | ushort sen_paddrl; /* physical address (LSB) */ | |
400 | ushort sen_pper; /* persistence */ | |
401 | ushort sen_rfbdptr; /* Rx first BD pointer */ | |
402 | ushort sen_tfbdptr; /* Tx first BD pointer */ | |
403 | ushort sen_tlbdptr; /* Tx last BD pointer */ | |
404 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | |
405 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | |
406 | uint sen_tbuf1rba; /* Internal */ | |
407 | uint sen_tbuf1crc; /* Internal */ | |
408 | ushort sen_tbuf1bcnt; /* Internal */ | |
409 | ushort sen_txlen; /* Tx Frame length counter */ | |
410 | ushort sen_iaddr1; /* Individual address filter */ | |
411 | ushort sen_iaddr2; | |
412 | ushort sen_iaddr3; | |
413 | ushort sen_iaddr4; | |
414 | ushort sen_boffcnt; /* Backoff counter */ | |
415 | ||
416 | /* NOTE: Some versions of the manual have the following items | |
417 | * incorrectly documented. Below is the proper order. | |
418 | */ | |
419 | ushort sen_taddrh; /* temp address (MSB) */ | |
420 | ushort sen_taddrm; | |
421 | ushort sen_taddrl; /* temp address (LSB) */ | |
422 | } scc_enet_t; | |
423 | ||
424 | /********************************************************************** | |
425 | * | |
426 | * Board specific configuration settings. | |
427 | * | |
428 | * Please note that we use the presence of a #define SCC_ENET and/or | |
429 | * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. | |
430 | **********************************************************************/ | |
431 | ||
fe8c2806 WD |
432 | /*** BSEIP **********************************************************/ |
433 | ||
434 | #ifdef CONFIG_BSEIP | |
435 | /* This ENET stuff is for the MPC823 with ethernet on SCC2. | |
436 | * This is unique to the BSE ip-Engine board. | |
437 | */ | |
438 | #define PROFF_ENET PROFF_SCC2 | |
439 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
440 | #define SCC_ENET 1 | |
441 | #define PA_ENET_RXD ((ushort)0x0004) | |
442 | #define PA_ENET_TXD ((ushort)0x0008) | |
443 | #define PA_ENET_TCLK ((ushort)0x0100) | |
444 | #define PA_ENET_RCLK ((ushort)0x0200) | |
445 | #define PB_ENET_TENA ((uint)0x00002000) | |
446 | #define PC_ENET_CLSN ((ushort)0x0040) | |
447 | #define PC_ENET_RENA ((ushort)0x0080) | |
448 | ||
449 | /* BSE uses port B and C bits for PHY control also. | |
450 | */ | |
451 | #define PB_BSE_POWERUP ((uint)0x00000004) | |
452 | #define PB_BSE_FDXDIS ((uint)0x00008000) | |
453 | #define PC_BSE_LOOPBACK ((ushort)0x0800) | |
454 | ||
455 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
456 | #define SICR_ENET_CLKRT ((uint)0x00002c00) | |
457 | #endif /* CONFIG_BSEIP */ | |
458 | ||
3bac3513 WD |
459 | /*** ELPT860 *********************************************************/ |
460 | ||
461 | #ifdef CONFIG_ELPT860 | |
462 | /* Bits in parallel I/O port registers that have to be set/cleared | |
463 | * to configure the pins for SCC1 use. | |
464 | */ | |
465 | # define PROFF_ENET PROFF_SCC1 | |
466 | # define CPM_CR_ENET CPM_CR_CH_SCC1 | |
467 | # define SCC_ENET 0 | |
468 | ||
469 | # define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ | |
470 | # define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ | |
471 | # define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
472 | # define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ | |
473 | ||
474 | # define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ | |
475 | # define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ | |
476 | # define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ | |
477 | ||
478 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to | |
479 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
480 | */ | |
481 | # define SICR_ENET_MASK ((uint)0x000000FF) | |
482 | # define SICR_ENET_CLKRT ((uint)0x00000025) | |
483 | #endif /* CONFIG_ELPT860 */ | |
484 | ||
fe8c2806 WD |
485 | /*** ESTEEM 192E **************************************************/ |
486 | #ifdef CONFIG_ESTEEM192E | |
487 | /* ESTEEM192E | |
488 | * This ENET stuff is for the MPC850 with ethernet on SCC2. This | |
489 | * is very similar to the RPX-Lite configuration. | |
490 | * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. | |
491 | */ | |
492 | ||
493 | #define PROFF_ENET PROFF_SCC2 | |
494 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
495 | #define SCC_ENET 1 | |
496 | ||
497 | #define PA_ENET_RXD ((ushort)0x0004) | |
498 | #define PA_ENET_TXD ((ushort)0x0008) | |
499 | #define PA_ENET_TCLK ((ushort)0x0200) | |
500 | #define PA_ENET_RCLK ((ushort)0x0800) | |
501 | #define PB_ENET_TENA ((uint)0x00002000) | |
502 | #define PC_ENET_CLSN ((ushort)0x0040) | |
503 | #define PC_ENET_RENA ((ushort)0x0080) | |
504 | ||
505 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
506 | #define SICR_ENET_CLKRT ((uint)0x00003d00) | |
507 | ||
508 | #define PB_ENET_LOOPBACK ((uint)0x00004000) | |
509 | #define PB_ENET_FDPLEX_DIS ((uint)0x00008000) | |
510 | ||
511 | #endif | |
512 | ||
384ae025 | 513 | /*** FPS850L, FPS860L ************************************************/ |
fe8c2806 | 514 | |
384ae025 | 515 | #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) |
fe8c2806 | 516 | /* Bits in parallel I/O port registers that have to be set/cleared |
384ae025 | 517 | * to configure the pins for SCC2 use. |
fe8c2806 WD |
518 | */ |
519 | #define PROFF_ENET PROFF_SCC2 | |
520 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
521 | #define SCC_ENET 1 | |
522 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
523 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
524 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
525 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
526 | ||
527 | #define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ | |
528 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
529 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
530 | ||
531 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to | |
532 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
533 | */ | |
534 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
535 | #define SICR_ENET_CLKRT ((uint)0x00002600) | |
384ae025 | 536 | #endif /* CONFIG_FPS850L, CONFIG_FPS860L */ |
fe8c2806 | 537 | |
fe8c2806 WD |
538 | /*** HERMES-PRO ******************************************************/ |
539 | ||
540 | /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ | |
541 | ||
542 | #ifdef CONFIG_HERMES | |
543 | ||
544 | #define FEC_ENET /* use FEC for EThernet */ | |
545 | #undef SCC_ENET | |
546 | ||
547 | ||
548 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
549 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
550 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
551 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
552 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
553 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
554 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
555 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
556 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
557 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
558 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
559 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
560 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
561 | ||
562 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
563 | ||
564 | #endif /* CONFIG_HERMES */ | |
565 | ||
fe8c2806 WD |
566 | /*** IP860 **********************************************************/ |
567 | ||
568 | #if defined(CONFIG_IP860) | |
569 | /* Bits in parallel I/O port registers that have to be set/cleared | |
570 | * to configure the pins for SCC1 use. | |
571 | */ | |
572 | #define PROFF_ENET PROFF_SCC1 | |
573 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
574 | #define SCC_ENET 0 | |
575 | #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ | |
576 | #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ | |
577 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
578 | #define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ | |
579 | ||
580 | #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ | |
581 | #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ | |
582 | #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ | |
583 | ||
584 | #define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ | |
585 | #define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ | |
586 | ||
587 | /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to | |
588 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
589 | */ | |
590 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
591 | #define SICR_ENET_CLKRT ((uint)0x0000002C) | |
592 | #endif /* CONFIG_IP860 */ | |
593 | ||
594 | /*** IVMS8 **********************************************************/ | |
595 | ||
596 | /* The IVMS8 uses the FEC on a MPC860T for Ethernet */ | |
597 | ||
598 | #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) | |
599 | ||
600 | #define FEC_ENET /* use FEC for EThernet */ | |
601 | #undef SCC_ENET | |
602 | ||
603 | #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ | |
604 | ||
605 | #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ | |
606 | ||
607 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
608 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
609 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
610 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
611 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
612 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
613 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
614 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
615 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
616 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
617 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
618 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
619 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
620 | ||
621 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
622 | ||
623 | #endif /* CONFIG_IVMS8, CONFIG_IVML24 */ | |
624 | ||
0608e04d WD |
625 | /*** KUP4K, KUP4X ****************************************************/ |
626 | /* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ | |
56f94be3 | 627 | |
0608e04d | 628 | #if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) |
56f94be3 WD |
629 | |
630 | #define FEC_ENET /* use FEC for EThernet */ | |
631 | #undef SCC_ENET | |
632 | ||
633 | #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ | |
634 | ||
635 | #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ | |
636 | ||
637 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
638 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
639 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
640 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
641 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
642 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
643 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
644 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
645 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
646 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
647 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
648 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
649 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
650 | ||
651 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
652 | ||
653 | #endif /* CONFIG_KUP4K */ | |
654 | ||
fe8c2806 WD |
655 | /*** LWMON **********************************************************/ |
656 | ||
281e00a3 | 657 | #if defined(CONFIG_LWMON) |
fe8c2806 WD |
658 | /* Bits in parallel I/O port registers that have to be set/cleared |
659 | * to configure the pins for SCC2 use. | |
660 | */ | |
661 | #define PROFF_ENET PROFF_SCC2 | |
662 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
663 | #define SCC_ENET 1 | |
664 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
665 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
666 | #define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ | |
667 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
668 | ||
669 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
670 | ||
671 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
672 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
673 | ||
674 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to | |
675 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
676 | */ | |
677 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
678 | #define SICR_ENET_CLKRT ((uint)0x00003E00) | |
679 | #endif /* CONFIG_LWMON */ | |
680 | ||
d044954f | 681 | /*** KM8XX *********************************************************/ |
381e4e63 | 682 | |
d044954f | 683 | /* The KM8XX Service Module uses SCC3 for Ethernet */ |
381e4e63 | 684 | |
d044954f | 685 | #ifdef CONFIG_KM8XX |
381e4e63 HS |
686 | #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ |
687 | #define CPM_CR_ENET CPM_CR_CH_SCC3 | |
688 | #define SCC_ENET 2 | |
689 | #define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ | |
690 | #define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ | |
691 | #define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ | |
692 | #define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ | |
693 | ||
694 | #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ | |
695 | ||
696 | #define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ | |
697 | #define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ | |
698 | ||
699 | /* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to | |
700 | * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. | |
701 | */ | |
702 | #define SICR_ENET_MASK ((uint)0x00FF0000) | |
703 | #define SICR_ENET_CLKRT ((uint)0x00250000) | |
d044954f | 704 | #endif /* CONFIG_KM8XX */ |
381e4e63 | 705 | |
608c9146 WD |
706 | /*** NETVIA *******************************************************/ |
707 | ||
708 | #if defined(CONFIG_NETVIA) | |
709 | /* Bits in parallel I/O port registers that have to be set/cleared | |
710 | * to configure the pins for SCC2 use. | |
711 | */ | |
712 | #define PROFF_ENET PROFF_SCC2 | |
713 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
714 | #define SCC_ENET 1 | |
715 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
716 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
717 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
718 | #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ | |
719 | ||
993cad93 WD |
720 | #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 |
721 | # define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ | |
722 | #elif CONFIG_NETVIA_VERSION >= 2 | |
723 | # define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ | |
724 | #endif | |
725 | ||
608c9146 WD |
726 | #define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ |
727 | ||
728 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
729 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
730 | ||
731 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
732 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
733 | */ | |
734 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
735 | #define SICR_ENET_CLKRT ((uint)0x00002f00) | |
736 | ||
737 | #endif /* CONFIG_NETVIA */ | |
738 | ||
fe8c2806 WD |
739 | /*** SM850 *********************************************************/ |
740 | ||
741 | /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ | |
742 | ||
743 | #ifdef CONFIG_SM850 | |
744 | #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ | |
745 | #define CPM_CR_ENET CPM_CR_CH_SCC3 | |
746 | #define SCC_ENET 2 | |
747 | #define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ | |
748 | #define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ | |
749 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
750 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
751 | ||
752 | #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ | |
753 | #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ | |
754 | ||
755 | #define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ | |
756 | #define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ | |
757 | ||
758 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
759 | * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. | |
760 | */ | |
761 | #define SICR_ENET_MASK ((uint)0x00FF0000) | |
762 | #define SICR_ENET_CLKRT ((uint)0x00260000) | |
763 | #endif /* CONFIG_SM850 */ | |
764 | ||
765 | /*** SPD823TS ******************************************************/ | |
766 | ||
767 | #ifdef CONFIG_SPD823TS | |
768 | /* Bits in parallel I/O port registers that have to be set/cleared | |
769 | * to configure the pins for SCC2 use. | |
770 | */ | |
771 | #define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ | |
772 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
773 | #define SCC_ENET 1 | |
774 | #define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ | |
775 | #define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ | |
776 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ | |
777 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
778 | #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ | |
779 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
780 | ||
781 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
782 | ||
783 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
784 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
785 | #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ | |
786 | ||
787 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to | |
788 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
789 | */ | |
790 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
791 | #define SICR_ENET_CLKRT ((uint)0x00002E00) | |
792 | #endif /* CONFIG_SPD823TS */ | |
793 | ||
1b0757ec | 794 | /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ |
fe8c2806 WD |
795 | |
796 | #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ | |
c750b9c0 | 797 | defined(CONFIG_R360MPI) || \ |
1b0757ec WD |
798 | defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ |
799 | defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ | |
800 | defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ | |
801 | defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2) | |
090eb735 | 802 | |
fe8c2806 WD |
803 | /* Bits in parallel I/O port registers that have to be set/cleared |
804 | * to configure the pins for SCC2 use. | |
805 | */ | |
806 | #define PROFF_ENET PROFF_SCC2 | |
807 | #define CPM_CR_ENET CPM_CR_CH_SCC2 | |
2b4f778f | 808 | #if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ |
fe8c2806 | 809 | #define SCC_ENET 1 |
2b4f778f | 810 | #endif |
fe8c2806 WD |
811 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ |
812 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ | |
813 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
814 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
815 | ||
816 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ | |
817 | ||
818 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ | |
819 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ | |
820 | #if defined(CONFIG_R360MPI) | |
821 | #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ | |
822 | #endif /* CONFIG_R360MPI */ | |
823 | ||
824 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
825 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. | |
826 | */ | |
827 | #define SICR_ENET_MASK ((uint)0x0000ff00) | |
828 | #define SICR_ENET_CLKRT ((uint)0x00002600) | |
090eb735 MK |
829 | |
830 | # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ | |
831 | #define FEC_ENET | |
832 | # endif /* CONFIG_FEC_ENET */ | |
833 | ||
71f95118 | 834 | #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ |
fe8c2806 | 835 | |
d4ca31c4 | 836 | /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ |
fe8c2806 | 837 | |
71f95118 WD |
838 | #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ |
839 | defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ | |
d4ca31c4 WD |
840 | defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ |
841 | defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) | |
fe8c2806 WD |
842 | |
843 | # ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ | |
844 | ||
845 | /* Bits in parallel I/O port registers that have to be set/cleared | |
846 | * to configure the pins for SCC1 use. | |
847 | */ | |
848 | #define PROFF_ENET PROFF_SCC1 | |
849 | #define CPM_CR_ENET CPM_CR_CH_SCC1 | |
850 | #define SCC_ENET 0 | |
851 | #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ | |
852 | #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ | |
853 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ | |
854 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ | |
855 | ||
856 | #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ | |
857 | #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ | |
858 | #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ | |
859 | ||
860 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to | |
861 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | |
862 | */ | |
863 | #define SICR_ENET_MASK ((uint)0x000000ff) | |
864 | #define SICR_ENET_CLKRT ((uint)0x00000026) | |
865 | ||
866 | # endif /* CONFIG_SCC1_ENET */ | |
867 | ||
868 | # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ | |
869 | ||
870 | #define FEC_ENET | |
871 | ||
872 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ | |
873 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ | |
874 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ | |
875 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ | |
876 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ | |
877 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ | |
878 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ | |
879 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ | |
880 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ | |
881 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ | |
882 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ | |
883 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ | |
884 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ | |
885 | ||
886 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ | |
887 | ||
888 | # endif /* CONFIG_FEC_ENET */ | |
71f95118 | 889 | #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ |
fe8c2806 | 890 | |
fe8c2806 WD |
891 | /*********************************************************************/ |
892 | ||
893 | /* SCC Event register as used by Ethernet. | |
894 | */ | |
895 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | |
896 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | |
897 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | |
898 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | |
899 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | |
900 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | |
901 | ||
902 | /* SCC Mode Register (PSMR) as used by Ethernet. | |
903 | */ | |
904 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | |
905 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | |
906 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | |
907 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | |
908 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | |
909 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | |
910 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | |
911 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | |
912 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | |
913 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | |
914 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | |
915 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | |
916 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | |
917 | ||
918 | /* Buffer descriptor control/status used by Ethernet receive. | |
919 | */ | |
920 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | |
921 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | |
922 | #define BD_ENET_RX_INTR ((ushort)0x1000) | |
923 | #define BD_ENET_RX_LAST ((ushort)0x0800) | |
924 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | |
925 | #define BD_ENET_RX_MISS ((ushort)0x0100) | |
926 | #define BD_ENET_RX_LG ((ushort)0x0020) | |
927 | #define BD_ENET_RX_NO ((ushort)0x0010) | |
928 | #define BD_ENET_RX_SH ((ushort)0x0008) | |
929 | #define BD_ENET_RX_CR ((ushort)0x0004) | |
930 | #define BD_ENET_RX_OV ((ushort)0x0002) | |
931 | #define BD_ENET_RX_CL ((ushort)0x0001) | |
932 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | |
933 | ||
934 | /* Buffer descriptor control/status used by Ethernet transmit. | |
935 | */ | |
936 | #define BD_ENET_TX_READY ((ushort)0x8000) | |
937 | #define BD_ENET_TX_PAD ((ushort)0x4000) | |
938 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | |
939 | #define BD_ENET_TX_INTR ((ushort)0x1000) | |
940 | #define BD_ENET_TX_LAST ((ushort)0x0800) | |
941 | #define BD_ENET_TX_TC ((ushort)0x0400) | |
942 | #define BD_ENET_TX_DEF ((ushort)0x0200) | |
943 | #define BD_ENET_TX_HB ((ushort)0x0100) | |
944 | #define BD_ENET_TX_LC ((ushort)0x0080) | |
945 | #define BD_ENET_TX_RL ((ushort)0x0040) | |
946 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | |
947 | #define BD_ENET_TX_UN ((ushort)0x0002) | |
948 | #define BD_ENET_TX_CSL ((ushort)0x0001) | |
949 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | |
950 | ||
951 | /* SCC as UART | |
952 | */ | |
953 | typedef struct scc_uart { | |
954 | sccp_t scc_genscc; | |
955 | uint scc_res1; /* Reserved */ | |
956 | uint scc_res2; /* Reserved */ | |
957 | ushort scc_maxidl; /* Maximum idle chars */ | |
958 | ushort scc_idlc; /* temp idle counter */ | |
959 | ushort scc_brkcr; /* Break count register */ | |
960 | ushort scc_parec; /* receive parity error counter */ | |
961 | ushort scc_frmec; /* receive framing error counter */ | |
962 | ushort scc_nosec; /* receive noise counter */ | |
963 | ushort scc_brkec; /* receive break condition counter */ | |
964 | ushort scc_brkln; /* last received break length */ | |
965 | ushort scc_uaddr1; /* UART address character 1 */ | |
966 | ushort scc_uaddr2; /* UART address character 2 */ | |
967 | ushort scc_rtemp; /* Temp storage */ | |
968 | ushort scc_toseq; /* Transmit out of sequence char */ | |
969 | ushort scc_char1; /* control character 1 */ | |
970 | ushort scc_char2; /* control character 2 */ | |
971 | ushort scc_char3; /* control character 3 */ | |
972 | ushort scc_char4; /* control character 4 */ | |
973 | ushort scc_char5; /* control character 5 */ | |
974 | ushort scc_char6; /* control character 6 */ | |
975 | ushort scc_char7; /* control character 7 */ | |
976 | ushort scc_char8; /* control character 8 */ | |
977 | ushort scc_rccm; /* receive control character mask */ | |
978 | ushort scc_rccr; /* receive control character register */ | |
979 | ushort scc_rlbc; /* receive last break character */ | |
980 | } scc_uart_t; | |
981 | ||
982 | /* SCC Event and Mask registers when it is used as a UART. | |
983 | */ | |
984 | #define UART_SCCM_GLR ((ushort)0x1000) | |
985 | #define UART_SCCM_GLT ((ushort)0x0800) | |
986 | #define UART_SCCM_AB ((ushort)0x0200) | |
987 | #define UART_SCCM_IDL ((ushort)0x0100) | |
988 | #define UART_SCCM_GRA ((ushort)0x0080) | |
989 | #define UART_SCCM_BRKE ((ushort)0x0040) | |
990 | #define UART_SCCM_BRKS ((ushort)0x0020) | |
991 | #define UART_SCCM_CCR ((ushort)0x0008) | |
992 | #define UART_SCCM_BSY ((ushort)0x0004) | |
993 | #define UART_SCCM_TX ((ushort)0x0002) | |
994 | #define UART_SCCM_RX ((ushort)0x0001) | |
995 | ||
996 | /* The SCC PSMR when used as a UART. | |
997 | */ | |
998 | #define SCU_PSMR_FLC ((ushort)0x8000) | |
999 | #define SCU_PSMR_SL ((ushort)0x4000) | |
1000 | #define SCU_PSMR_CL ((ushort)0x3000) | |
1001 | #define SCU_PSMR_UM ((ushort)0x0c00) | |
1002 | #define SCU_PSMR_FRZ ((ushort)0x0200) | |
1003 | #define SCU_PSMR_RZS ((ushort)0x0100) | |
1004 | #define SCU_PSMR_SYN ((ushort)0x0080) | |
1005 | #define SCU_PSMR_DRT ((ushort)0x0040) | |
1006 | #define SCU_PSMR_PEN ((ushort)0x0010) | |
1007 | #define SCU_PSMR_RPM ((ushort)0x000c) | |
1008 | #define SCU_PSMR_REVP ((ushort)0x0008) | |
1009 | #define SCU_PSMR_TPM ((ushort)0x0003) | |
1010 | #define SCU_PSMR_TEVP ((ushort)0x0003) | |
1011 | ||
1012 | /* CPM Transparent mode SCC. | |
1013 | */ | |
1014 | typedef struct scc_trans { | |
1015 | sccp_t st_genscc; | |
1016 | uint st_cpres; /* Preset CRC */ | |
1017 | uint st_cmask; /* Constant mask for CRC */ | |
1018 | } scc_trans_t; | |
1019 | ||
1020 | #define BD_SCC_TX_LAST ((ushort)0x0800) | |
1021 | ||
1022 | /* IIC parameter RAM. | |
1023 | */ | |
1024 | typedef struct iic { | |
1025 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | |
1026 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | |
1027 | u_char iic_rfcr; /* Rx function code */ | |
1028 | u_char iic_tfcr; /* Tx function code */ | |
1029 | ushort iic_mrblr; /* Max receive buffer length */ | |
1030 | uint iic_rstate; /* Internal */ | |
1031 | uint iic_rdp; /* Internal */ | |
1032 | ushort iic_rbptr; /* Internal */ | |
1033 | ushort iic_rbc; /* Internal */ | |
1034 | uint iic_rxtmp; /* Internal */ | |
1035 | uint iic_tstate; /* Internal */ | |
1036 | uint iic_tdp; /* Internal */ | |
1037 | ushort iic_tbptr; /* Internal */ | |
1038 | ushort iic_tbc; /* Internal */ | |
1039 | uint iic_txtmp; /* Internal */ | |
1040 | uint iic_res; /* reserved */ | |
1041 | ushort iic_rpbase; /* Relocation pointer */ | |
1042 | ushort iic_res2; /* reserved */ | |
1043 | } iic_t; | |
1044 | ||
1045 | /* SPI parameter RAM. | |
1046 | */ | |
1047 | typedef struct spi { | |
1048 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | |
1049 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | |
1050 | u_char spi_rfcr; /* Rx function code */ | |
1051 | u_char spi_tfcr; /* Tx function code */ | |
1052 | ushort spi_mrblr; /* Max receive buffer length */ | |
1053 | uint spi_rstate; /* Internal */ | |
1054 | uint spi_rdp; /* Internal */ | |
1055 | ushort spi_rbptr; /* Internal */ | |
1056 | ushort spi_rbc; /* Internal */ | |
1057 | uint spi_rxtmp; /* Internal */ | |
1058 | uint spi_tstate; /* Internal */ | |
1059 | uint spi_tdp; /* Internal */ | |
1060 | ushort spi_tbptr; /* Internal */ | |
1061 | ushort spi_tbc; /* Internal */ | |
1062 | uint spi_txtmp; /* Internal */ | |
1063 | uint spi_res; | |
1064 | ushort spi_rpbase; /* Relocation pointer */ | |
1065 | ushort spi_res2; | |
1066 | } spi_t; | |
1067 | ||
1068 | /* SPI Mode register. | |
1069 | */ | |
1070 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | |
1071 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | |
1072 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | |
1073 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | |
1074 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | |
1075 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | |
1076 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | |
1077 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | |
1078 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | |
1079 | ||
1080 | #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) | |
1081 | #define SPMODE_PM(x) ((x) &0xF) | |
1082 | ||
1083 | /* HDLC parameter RAM. | |
1084 | */ | |
1085 | ||
1086 | typedef struct hdlc_pram_s { | |
1087 | /* | |
1088 | * SCC parameter RAM | |
1089 | */ | |
1090 | ushort rbase; /* Rx Buffer descriptor base address */ | |
1091 | ushort tbase; /* Tx Buffer descriptor base address */ | |
1092 | uchar rfcr; /* Rx function code */ | |
1093 | uchar tfcr; /* Tx function code */ | |
1094 | ushort mrblr; /* Rx buffer length */ | |
1095 | ulong rstate; /* Rx internal state */ | |
1096 | ulong rptr; /* Rx internal data pointer */ | |
1097 | ushort rbptr; /* rb BD Pointer */ | |
1098 | ushort rcount; /* Rx internal byte count */ | |
1099 | ulong rtemp; /* Rx temp */ | |
1100 | ulong tstate; /* Tx internal state */ | |
1101 | ulong tptr; /* Tx internal data pointer */ | |
1102 | ushort tbptr; /* Tx BD pointer */ | |
1103 | ushort tcount; /* Tx byte count */ | |
1104 | ulong ttemp; /* Tx temp */ | |
1105 | ulong rcrc; /* temp receive CRC */ | |
1106 | ulong tcrc; /* temp transmit CRC */ | |
1107 | /* | |
1108 | * HDLC specific parameter RAM | |
1109 | */ | |
1110 | uchar res[4]; /* reserved */ | |
1111 | ulong c_mask; /* CRC constant */ | |
1112 | ulong c_pres; /* CRC preset */ | |
1113 | ushort disfc; /* discarded frame counter */ | |
1114 | ushort crcec; /* CRC error counter */ | |
1115 | ushort abtsc; /* abort sequence counter */ | |
1116 | ushort nmarc; /* nonmatching address rx cnt */ | |
1117 | ushort retrc; /* frame retransmission cnt */ | |
1118 | ushort mflr; /* maximum frame length reg */ | |
1119 | ushort max_cnt; /* maximum length counter */ | |
1120 | ushort rfthr; /* received frames threshold */ | |
1121 | ushort rfcnt; /* received frames count */ | |
1122 | ushort hmask; /* user defined frm addr mask */ | |
1123 | ushort haddr1; /* user defined frm address 1 */ | |
1124 | ushort haddr2; /* user defined frm address 2 */ | |
1125 | ushort haddr3; /* user defined frm address 3 */ | |
1126 | ushort haddr4; /* user defined frm address 4 */ | |
1127 | ushort tmp; /* temp */ | |
1128 | ushort tmp_mb; /* temp */ | |
1129 | } hdlc_pram_t; | |
1130 | ||
1131 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM | |
1132 | * channels or devices. All of these are presented to the PPC core | |
1133 | * as a single interrupt. The CPM interrupt handler dispatches its | |
1134 | * own handlers, in a similar fashion to the PPC core handler. We | |
1135 | * use the table as defined in the manuals (i.e. no special high | |
1136 | * priority and SCC1 == SCCa, etc...). | |
1137 | */ | |
1138 | #define CPMVEC_NR 32 | |
7c7a23bd WD |
1139 | #define CPMVEC_OFFSET 0x00010000 |
1140 | #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) | |
1141 | #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) | |
1142 | #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) | |
1143 | #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) | |
1144 | #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) | |
1145 | #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) | |
1146 | #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) | |
1147 | #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) | |
1148 | #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) | |
1149 | #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) | |
1150 | #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) | |
1151 | #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) | |
1152 | #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) | |
1153 | #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) | |
1154 | #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) | |
1155 | #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) | |
1156 | #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) | |
1157 | #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) | |
1158 | #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) | |
1159 | #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) | |
1160 | #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) | |
1161 | #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) | |
1162 | #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) | |
1163 | #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) | |
1164 | #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) | |
1165 | #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) | |
1166 | #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) | |
1167 | #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) | |
1168 | #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) | |
fe8c2806 WD |
1169 | |
1170 | extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); | |
1171 | ||
1172 | /* CPM interrupt configuration vector. | |
1173 | */ | |
1174 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | |
1175 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | |
1176 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | |
1177 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | |
1178 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ | |
1179 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ | |
1180 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | |
1181 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | |
1182 | #endif /* __CPM_8XX__ */ |