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powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7
[people/ms/u-boot.git] / include / commproc.h
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fe8c2806
WD		 1/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
8cba090c 5 * (C) Copyright 2000-2006
d4ca31c4
WD		 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
fe8c2806
WD		 8 * This file contains structures and information for the communication
9 * processor channels. Some CPM control and status is available
10 * throught the MPC8xx internal memory map. See immap.h for details.
11 * This file only contains what I need for the moment, not the total
12 * CPM capabilities. I (or someone else) will add definitions as they
13 * are needed. -- Dan
14 *
15 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
16 * bytes of the DP RAM and relocates the I2C parameter area to the
17 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
18 * or other use.
19 */
20#ifndef __CPM_8XX__
21#define __CPM_8XX__
22
23#include <linux/config.h>
24#include <asm/8xx_immap.h>
25
26/* CPM Command register.
27*/
7c7a23bd
WD		 28#define CPM_CR_RST ((ushort)0x8000)
29#define CPM_CR_OPCODE ((ushort)0x0f00)
30#define CPM_CR_CHAN ((ushort)0x00f0)
31#define CPM_CR_FLG ((ushort)0x0001)
fe8c2806
WD		 32
33/* Some commands (there are more...later)
34*/
35#define CPM_CR_INIT_TRX ((ushort)0x0000)
36#define CPM_CR_INIT_RX ((ushort)0x0001)
37#define CPM_CR_INIT_TX ((ushort)0x0002)
38#define CPM_CR_HUNT_MODE ((ushort)0x0003)
39#define CPM_CR_STOP_TX ((ushort)0x0004)
40#define CPM_CR_RESTART_TX ((ushort)0x0006)
41#define CPM_CR_SET_GADDR ((ushort)0x0008)
42
43/* Channel numbers.
44*/
7c7a23bd
WD		 45#define CPM_CR_CH_SCC1 ((ushort)0x0000)
46#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
47#define CPM_CR_CH_SCC2 ((ushort)0x0004)
48#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
49#define CPM_CR_CH_SCC3 ((ushort)0x0008)
50#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
51#define CPM_CR_CH_SCC4 ((ushort)0x000c)
52#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
fe8c2806
WD		 53
54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
55
56/*
57 * DPRAM defines and allocation functions
58 */
59
60/* The dual ported RAM is multi-functional. Some areas can be (and are
61 * being) used for microcode. There is an area that can only be used
62 * as data ram for buffer descriptors, which is all we use right now.
63 * Currently the first 512 and last 256 bytes are used for microcode.
64 */
6d0f6bcf 65#ifdef CONFIG_SYS_ALLOC_DPRAM
fe8c2806
WD		 66
67#define CPM_DATAONLY_BASE ((uint)0x0800)
68#define CPM_DATAONLY_SIZE ((uint)0x0700)
69#define CPM_DP_NOSPACE ((uint)0x7fffffff)
70
71#else
72
73#define CPM_SERIAL_BASE 0x0800
74#define CPM_I2C_BASE 0x0820
75#define CPM_SPI_BASE 0x0840
76#define CPM_FEC_BASE 0x0860
79536a6e 77#define CPM_SERIAL2_BASE 0x08E0
fe8c2806
WD		 78#define CPM_SCC_BASE 0x0900
79#define CPM_POST_BASE 0x0980
281e00a3 80#define CPM_WLKBD_BASE 0x0a00
fe8c2806
WD		 81
82#endif
83
6d0f6bcf 84#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
fe8c2806 85#define CPM_POST_WORD_ADDR 0x07FC
ea909b76 86#else
6d0f6bcf 87#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
ea909b76 88#endif
fe8c2806 89
6d0f6bcf 90#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
bdccc4fe
WD		 91#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
92#else
6d0f6bcf 93#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
bdccc4fe
WD		 94#endif
95
fe8c2806
WD		 96#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
97
98/* Export the base address of the communication processor registers
99 * and dual port ram.
100 */
101extern cpm8xx_t *cpmp; /* Pointer to comm processor */
102
103/* Buffer descriptors used by many of the CPM protocols.
104*/
105typedef struct cpm_buf_desc {
106 ushort cbd_sc; /* Status and Control */
107 ushort cbd_datlen; /* Data length in buffer */
108 uint cbd_bufaddr; /* Buffer address in host memory */
109} cbd_t;
110
16263087 111#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
fe8c2806
WD		 112#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
113#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
114#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
115#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
116#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
117#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
118#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
119#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
120#define BD_SC_BR ((ushort)0x0020) /* Break received */
121#define BD_SC_FR ((ushort)0x0010) /* Framing error */
122#define BD_SC_PR ((ushort)0x0008) /* Parity error */
123#define BD_SC_OV ((ushort)0x0002) /* Overrun */
124#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
125
126/* Parameter RAM offsets.
127*/
128#define PROFF_SCC1 ((uint)0x0000)
129#define PROFF_IIC ((uint)0x0080)
a166fbca 130#define PROFF_REVNUM ((uint)0x00b0)
fe8c2806
WD		 131#define PROFF_SCC2 ((uint)0x0100)
132#define PROFF_SPI ((uint)0x0180)
133#define PROFF_SCC3 ((uint)0x0200)
134#define PROFF_SMC1 ((uint)0x0280)
135#define PROFF_SCC4 ((uint)0x0300)
136#define PROFF_SMC2 ((uint)0x0380)
137
138/* Define enough so I can at least use the serial port as a UART.
139 * The MBX uses SMC1 as the host serial port.
140 */
141typedef struct smc_uart {
142 ushort smc_rbase; /* Rx Buffer descriptor base address */
143 ushort smc_tbase; /* Tx Buffer descriptor base address */
144 u_char smc_rfcr; /* Rx function code */
145 u_char smc_tfcr; /* Tx function code */
146 ushort smc_mrblr; /* Max receive buffer length */
147 uint smc_rstate; /* Internal */
148 uint smc_idp; /* Internal */
149 ushort smc_rbptr; /* Internal */
150 ushort smc_ibc; /* Internal */
151 uint smc_rxtmp; /* Internal */
152 uint smc_tstate; /* Internal */
153 uint smc_tdp; /* Internal */
154 ushort smc_tbptr; /* Internal */
155 ushort smc_tbc; /* Internal */
156 uint smc_txtmp; /* Internal */
157 ushort smc_maxidl; /* Maximum idle characters */
158 ushort smc_tmpidl; /* Temporary idle counter */
159 ushort smc_brklen; /* Last received break length */
160 ushort smc_brkec; /* rcv'd break condition counter */
161 ushort smc_brkcr; /* xmt break count register */
162 ushort smc_rmask; /* Temporary bit mask */
b423d055
HS		 163 u_char res1[8];
164 ushort smc_rpbase; /* Relocation pointer */
fe8c2806
WD		 165} smc_uart_t;
166
167/* Function code bits.
168*/
169#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
170
171/* SMC uart mode register.
172*/
173#define SMCMR_REN ((ushort)0x0001)
174#define SMCMR_TEN ((ushort)0x0002)
175#define SMCMR_DM ((ushort)0x000c)
176#define SMCMR_SM_GCI ((ushort)0x0000)
177#define SMCMR_SM_UART ((ushort)0x0020)
178#define SMCMR_SM_TRANS ((ushort)0x0030)
179#define SMCMR_SM_MASK ((ushort)0x0030)
180#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
181#define SMCMR_REVD SMCMR_PM_EVEN
182#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
183#define SMCMR_BS SMCMR_PEN
184#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
185#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
186#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
187
188/* SMC2 as Centronics parallel printer. It is half duplex, in that
189 * it can only receive or transmit. The parameter ram values for
190 * each direction are either unique or properly overlap, so we can
191 * include them in one structure.
192 */
193typedef struct smc_centronics {
194 ushort scent_rbase;
195 ushort scent_tbase;
196 u_char scent_cfcr;
197 u_char scent_smask;
198 ushort scent_mrblr;
199 uint scent_rstate;
200 uint scent_r_ptr;
201 ushort scent_rbptr;
202 ushort scent_r_cnt;
203 uint scent_rtemp;
204 uint scent_tstate;
205 uint scent_t_ptr;
206 ushort scent_tbptr;
207 ushort scent_t_cnt;
208 uint scent_ttemp;
209 ushort scent_max_sl;
210 ushort scent_sl_cnt;
211 ushort scent_character1;
212 ushort scent_character2;
213 ushort scent_character3;
214 ushort scent_character4;
215 ushort scent_character5;
216 ushort scent_character6;
217 ushort scent_character7;
218 ushort scent_character8;
219 ushort scent_rccm;
220 ushort scent_rccr;
221} smc_cent_t;
222
223/* Centronics Status Mask Register.
224*/
225#define SMC_CENT_F ((u_char)0x08)
226#define SMC_CENT_PE ((u_char)0x04)
227#define SMC_CENT_S ((u_char)0x02)
228
229/* SMC Event and Mask register.
230*/
231#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
232#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
233#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
234#define SMCM_BSY ((unsigned char)0x04)
235#define SMCM_TX ((unsigned char)0x02)
236#define SMCM_RX ((unsigned char)0x01)
237
238/* Baud rate generators.
239*/
240#define CPM_BRG_RST ((uint)0x00020000)
241#define CPM_BRG_EN ((uint)0x00010000)
242#define CPM_BRG_EXTC_INT ((uint)0x00000000)
243#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
244#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
245#define CPM_BRG_ATB ((uint)0x00002000)
246#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
247#define CPM_BRG_DIV16 ((uint)0x00000001)
248
249/* SI Clock Route Register
250*/
251#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
252#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
253#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
254#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
255#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
256#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
257#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
258#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
259
260/* SCCs.
261*/
262#define SCC_GSMRH_IRP ((uint)0x00040000)
263#define SCC_GSMRH_GDE ((uint)0x00010000)
264#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
265#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
266#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
267#define SCC_GSMRH_REVD ((uint)0x00002000)
268#define SCC_GSMRH_TRX ((uint)0x00001000)
269#define SCC_GSMRH_TTX ((uint)0x00000800)
270#define SCC_GSMRH_CDP ((uint)0x00000400)
271#define SCC_GSMRH_CTSP ((uint)0x00000200)
272#define SCC_GSMRH_CDS ((uint)0x00000100)
273#define SCC_GSMRH_CTSS ((uint)0x00000080)
274#define SCC_GSMRH_TFL ((uint)0x00000040)
275#define SCC_GSMRH_RFW ((uint)0x00000020)
276#define SCC_GSMRH_TXSY ((uint)0x00000010)
277#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
278#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
279#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
280#define SCC_GSMRH_RTSM ((uint)0x00000002)
281#define SCC_GSMRH_RSYN ((uint)0x00000001)
282
283#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
284#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
285#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
286#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
287#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
288#define SCC_GSMRL_TCI ((uint)0x10000000)
289#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
290#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
291#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
292#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
293#define SCC_GSMRL_RINV ((uint)0x02000000)
294#define SCC_GSMRL_TINV ((uint)0x01000000)
295#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
296#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
297#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
298#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
299#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
300#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
301#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
302#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
303#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
304#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
305#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
306#define SCC_GSMRL_TEND ((uint)0x00040000)
307#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
308#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
309#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
310#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
311#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
312#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
313#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
314#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
315#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
316#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
317#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
318#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
319#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
320#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
321#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
322#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
323#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
324#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
325#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
326#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
327#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
328#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
329#define SCC_GSMRL_ENR ((uint)0x00000020)
330#define SCC_GSMRL_ENT ((uint)0x00000010)
331#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
332#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
333#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
334#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
335#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
336#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
337#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
338#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
339#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
340#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
341
342#define SCC_TODR_TOD ((ushort)0x8000)
343
344/* SCC Event and Mask register.
345*/
346#define SCCM_TXE ((unsigned char)0x10)
347#define SCCM_BSY ((unsigned char)0x04)
348#define SCCM_TX ((unsigned char)0x02)
349#define SCCM_RX ((unsigned char)0x01)
350
351typedef struct scc_param {
352 ushort scc_rbase; /* Rx Buffer descriptor base address */
353 ushort scc_tbase; /* Tx Buffer descriptor base address */
354 u_char scc_rfcr; /* Rx function code */
355 u_char scc_tfcr; /* Tx function code */
356 ushort scc_mrblr; /* Max receive buffer length */
357 uint scc_rstate; /* Internal */
358 uint scc_idp; /* Internal */
359 ushort scc_rbptr; /* Internal */
360 ushort scc_ibc; /* Internal */
361 uint scc_rxtmp; /* Internal */
362 uint scc_tstate; /* Internal */
363 uint scc_tdp; /* Internal */
364 ushort scc_tbptr; /* Internal */
365 ushort scc_tbc; /* Internal */
366 uint scc_txtmp; /* Internal */
367 uint scc_rcrc; /* Internal */
368 uint scc_tcrc; /* Internal */
369} sccp_t;
370
371/* Function code bits.
372*/
373#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
374
375/* CPM Ethernet through SCCx.
376 */
377typedef struct scc_enet {
378 sccp_t sen_genscc;
379 uint sen_cpres; /* Preset CRC */
380 uint sen_cmask; /* Constant mask for CRC */
381 uint sen_crcec; /* CRC Error counter */
382 uint sen_alec; /* alignment error counter */
383 uint sen_disfc; /* discard frame counter */
384 ushort sen_pads; /* Tx short frame pad character */
385 ushort sen_retlim; /* Retry limit threshold */
386 ushort sen_retcnt; /* Retry limit counter */
387 ushort sen_maxflr; /* maximum frame length register */
388 ushort sen_minflr; /* minimum frame length register */
389 ushort sen_maxd1; /* maximum DMA1 length */
390 ushort sen_maxd2; /* maximum DMA2 length */
391 ushort sen_maxd; /* Rx max DMA */
392 ushort sen_dmacnt; /* Rx DMA counter */
393 ushort sen_maxb; /* Max BD byte count */
394 ushort sen_gaddr1; /* Group address filter */
395 ushort sen_gaddr2;
396 ushort sen_gaddr3;
397 ushort sen_gaddr4;
398 uint sen_tbuf0data0; /* Save area 0 - current frame */
399 uint sen_tbuf0data1; /* Save area 1 - current frame */
400 uint sen_tbuf0rba; /* Internal */
401 uint sen_tbuf0crc; /* Internal */
402 ushort sen_tbuf0bcnt; /* Internal */
403 ushort sen_paddrh; /* physical address (MSB) */
404 ushort sen_paddrm;
405 ushort sen_paddrl; /* physical address (LSB) */
406 ushort sen_pper; /* persistence */
407 ushort sen_rfbdptr; /* Rx first BD pointer */
408 ushort sen_tfbdptr; /* Tx first BD pointer */
409 ushort sen_tlbdptr; /* Tx last BD pointer */
410 uint sen_tbuf1data0; /* Save area 0 - current frame */
411 uint sen_tbuf1data1; /* Save area 1 - current frame */
412 uint sen_tbuf1rba; /* Internal */
413 uint sen_tbuf1crc; /* Internal */
414 ushort sen_tbuf1bcnt; /* Internal */
415 ushort sen_txlen; /* Tx Frame length counter */
416 ushort sen_iaddr1; /* Individual address filter */
417 ushort sen_iaddr2;
418 ushort sen_iaddr3;
419 ushort sen_iaddr4;
420 ushort sen_boffcnt; /* Backoff counter */
421
422 /* NOTE: Some versions of the manual have the following items
423 * incorrectly documented. Below is the proper order.
424 */
425 ushort sen_taddrh; /* temp address (MSB) */
426 ushort sen_taddrm;
427 ushort sen_taddrl; /* temp address (LSB) */
428} scc_enet_t;
429
430/**********************************************************************
431 *
432 * Board specific configuration settings.
433 *
434 * Please note that we use the presence of a #define SCC_ENET and/or
435 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
436 **********************************************************************/
437
438
439/*** ADS *************************************************************/
440
441#if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
442/* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
443 */
444
445#define PROFF_ENET PROFF_SCC1
446#define CPM_CR_ENET CPM_CR_CH_SCC1
447#define SCC_ENET 0
448
449#define PA_ENET_RXD ((ushort)0x0001)
450#define PA_ENET_TXD ((ushort)0x0002)
451#define PA_ENET_TCLK ((ushort)0x0100)
452#define PA_ENET_RCLK ((ushort)0x0200)
453
454#define PB_ENET_TENA ((uint)0x00001000)
455
456#define PC_ENET_CLSN ((ushort)0x0010)
457#define PC_ENET_RENA ((ushort)0x0020)
458
459#define SICR_ENET_MASK ((uint)0x000000ff)
460#define SICR_ENET_CLKRT ((uint)0x0000002c)
461
462/* 68160 PHY control */
463
464#define PC_ENET_ETHLOOP ((ushort)0x0800)
465#define PC_ENET_TPFLDL ((ushort)0x0400)
466#define PC_ENET_TPSQEL ((ushort)0x0200)
467
468#endif /* MPC860ADS */
469
fe8c2806
WD		 470/*** BSEIP **********************************************************/
471
472#ifdef CONFIG_BSEIP
473/* This ENET stuff is for the MPC823 with ethernet on SCC2.
474 * This is unique to the BSE ip-Engine board.
475 */
476#define PROFF_ENET PROFF_SCC2
477#define CPM_CR_ENET CPM_CR_CH_SCC2
478#define SCC_ENET 1
479#define PA_ENET_RXD ((ushort)0x0004)
480#define PA_ENET_TXD ((ushort)0x0008)
481#define PA_ENET_TCLK ((ushort)0x0100)
482#define PA_ENET_RCLK ((ushort)0x0200)
483#define PB_ENET_TENA ((uint)0x00002000)
484#define PC_ENET_CLSN ((ushort)0x0040)
485#define PC_ENET_RENA ((ushort)0x0080)
486
487/* BSE uses port B and C bits for PHY control also.
488*/
489#define PB_BSE_POWERUP ((uint)0x00000004)
490#define PB_BSE_FDXDIS ((uint)0x00008000)
491#define PC_BSE_LOOPBACK ((ushort)0x0800)
492
493#define SICR_ENET_MASK ((uint)0x0000ff00)
494#define SICR_ENET_CLKRT ((uint)0x00002c00)
495#endif /* CONFIG_BSEIP */
496
497/*** BSEIP **********************************************************/
498
499#ifdef CONFIG_FLAGADM
500/* Enet configuration for the FLAGADM */
501/* Enet on SCC2 */
502
503#define PROFF_ENET PROFF_SCC2
504#define CPM_CR_ENET CPM_CR_CH_SCC2
505#define SCC_ENET 1
7c7a23bd
WD		 506#define PA_ENET_RXD ((ushort)0x0004)
507#define PA_ENET_TXD ((ushort)0x0008)
fe8c2806
WD		 508#define PA_ENET_TCLK ((ushort)0x0100)
509#define PA_ENET_RCLK ((ushort)0x0400)
510#define PB_ENET_TENA ((uint)0x00002000)
511#define PC_ENET_CLSN ((ushort)0x0040)
512#define PC_ENET_RENA ((ushort)0x0080)
513
514#define SICR_ENET_MASK ((uint)0x0000ff00)
515#define SICR_ENET_CLKRT ((uint)0x00003400)
516#endif /* CONFIG_FLAGADM */
517
3bac3513
WD		 518/*** ELPT860 *********************************************************/
519
520#ifdef CONFIG_ELPT860
521/* Bits in parallel I/O port registers that have to be set/cleared
522 * to configure the pins for SCC1 use.
523 */
524# define PROFF_ENET PROFF_SCC1
525# define CPM_CR_ENET CPM_CR_CH_SCC1
526# define SCC_ENET 0
527
528# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
529# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
530# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
531# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
532
533# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
534# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
535# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
536
537/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
538 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
539 */
540# define SICR_ENET_MASK ((uint)0x000000FF)
541# define SICR_ENET_CLKRT ((uint)0x00000025)
542#endif /* CONFIG_ELPT860 */
543
fe8c2806
WD		 544/*** ESTEEM 192E **************************************************/
545#ifdef CONFIG_ESTEEM192E
546/* ESTEEM192E
547 * This ENET stuff is for the MPC850 with ethernet on SCC2. This
548 * is very similar to the RPX-Lite configuration.
549 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
550 */
551
552#define PROFF_ENET PROFF_SCC2
553#define CPM_CR_ENET CPM_CR_CH_SCC2
554#define SCC_ENET 1
555
556#define PA_ENET_RXD ((ushort)0x0004)
557#define PA_ENET_TXD ((ushort)0x0008)
558#define PA_ENET_TCLK ((ushort)0x0200)
559#define PA_ENET_RCLK ((ushort)0x0800)
560#define PB_ENET_TENA ((uint)0x00002000)
561#define PC_ENET_CLSN ((ushort)0x0040)
562#define PC_ENET_RENA ((ushort)0x0080)
563
564#define SICR_ENET_MASK ((uint)0x0000ff00)
565#define SICR_ENET_CLKRT ((uint)0x00003d00)
566
567#define PB_ENET_LOOPBACK ((uint)0x00004000)
568#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
569
570#endif
571
572/*** FADS823 ********************************************************/
573
574#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
575/* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
576 */
577#ifdef CONFIG_SCC2_ENET
578#define PROFF_ENET PROFF_SCC2
579#define CPM_CR_ENET CPM_CR_CH_SCC2
580#define SCC_ENET 1
581#define CPMVEC_ENET CPMVEC_SCC2
582#endif
583
584#ifdef CONFIG_SCC1_ENET
585#define PROFF_ENET PROFF_SCC1
586#define CPM_CR_ENET CPM_CR_CH_SCC1
587#define SCC_ENET 0
588#define CPMVEC_ENET CPMVEC_SCC1
589#endif
590
591#define PA_ENET_RXD ((ushort)0x0004)
592#define PA_ENET_TXD ((ushort)0x0008)
593#define PA_ENET_TCLK ((ushort)0x0400)
594#define PA_ENET_RCLK ((ushort)0x0200)
595
596#define PB_ENET_TENA ((uint)0x00002000)
597
598#define PC_ENET_CLSN ((ushort)0x0040)
599#define PC_ENET_RENA ((ushort)0x0080)
600
601#define SICR_ENET_MASK ((uint)0x0000ff00)
602#define SICR_ENET_CLKRT ((uint)0x00002e00)
603
604#endif /* CONFIG_FADS823FADS */
605
606/*** FADS850SAR ********************************************************/
607
608#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
609/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
610 * this may be unique to the FADS850SAR configuration.
611 * Note TENA is on Port B.
612 */
613#define PROFF_ENET PROFF_SCC2
614#define CPM_CR_ENET CPM_CR_CH_SCC2
615#define SCC_ENET 1
616#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
617#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
618#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
619#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
620#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
621#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
622#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
623
624#define SICR_ENET_MASK ((uint)0x0000ff00)
625#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
626#endif /* CONFIG_FADS850SAR */
627
628/*** FADS860T********************************************************/
629
180d3f74
WD		 630#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
631/*
632 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
fe8c2806 633 */
fe8c2806 634#ifdef CONFIG_SCC1_ENET
180d3f74 635
fe8c2806 636#define SCC_ENET 0
180d3f74 637
fe8c2806
WD		 638#define PROFF_ENET PROFF_SCC1
639#define CPM_CR_ENET CPM_CR_CH_SCC1
640
641#define PA_ENET_RXD ((ushort)0x0001)
642#define PA_ENET_TXD ((ushort)0x0002)
643#define PA_ENET_TCLK ((ushort)0x0100)
644#define PA_ENET_RCLK ((ushort)0x0200)
645
646#define PB_ENET_TENA ((uint)0x00001000)
647
648#define PC_ENET_CLSN ((ushort)0x0010)
649#define PC_ENET_RENA ((ushort)0x0020)
650
651#define SICR_ENET_MASK ((uint)0x000000ff)
652#define SICR_ENET_CLKRT ((uint)0x0000002c)
653
180d3f74
WD		 654#endif /* CONFIG_SCC1_ETHERNET */
655
656/*
1114257c
WD		 657 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
658 * with ethernet on FEC.
fe8c2806
WD		 659 */
660
661#ifdef CONFIG_FEC_ENET
180d3f74
WD		 662#define FEC_ENET /* Use FEC for Ethernet */
663#endif /* CONFIG_FEC_ENET */
fe8c2806 664
180d3f74 665#endif /* CONFIG_FADS && CONFIG_MPC86x */
fe8c2806 666
384ae025 667/*** FPS850L, FPS860L ************************************************/
fe8c2806 668
384ae025 669#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
fe8c2806 670/* Bits in parallel I/O port registers that have to be set/cleared
384ae025 671 * to configure the pins for SCC2 use.
fe8c2806
WD		 672 */
673#define PROFF_ENET PROFF_SCC2
674#define CPM_CR_ENET CPM_CR_CH_SCC2
675#define SCC_ENET 1
676#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
677#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
678#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
679#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
680
681#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
682#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
683#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
684
685/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
686 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
687 */
688#define SICR_ENET_MASK ((uint)0x0000ff00)
689#define SICR_ENET_CLKRT ((uint)0x00002600)
384ae025 690#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
fe8c2806
WD		 691
692/*** GEN860T **********************************************************/
693#if defined(CONFIG_GEN860T)
694#undef SCC_ENET
695#define FEC_ENET
696
53677ef1
WD		 697#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
698#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
699#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
700#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
701#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
702#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
703#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
704#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
705#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
706#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
707#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
708#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
709#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
fe8c2806
WD		 710#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
711#endif /* CONFIG_GEN860T */
712
713/*** GENIETV ********************************************************/
714
715#if defined(CONFIG_GENIETV)
716/* Ethernet is only on SCC2 */
717
718#define CONFIG_SCC2_ENET
719#define PROFF_ENET PROFF_SCC2
720#define CPM_CR_ENET CPM_CR_CH_SCC2
721#define SCC_ENET 1
722#define CPMVEC_ENET CPMVEC_SCC2
723
724#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
725#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
726#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
727#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
728
729#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
730
731#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
732#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
733
734#define SICR_ENET_MASK ((uint)0x0000ff00)
735#define SICR_ENET_CLKRT ((uint)0x00002e00)
736
737#endif /* CONFIG_GENIETV */
738
fe8c2806
WD		 739/*** HERMES-PRO ******************************************************/
740
741/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
742
743#ifdef CONFIG_HERMES
744
745#define FEC_ENET /* use FEC for EThernet */
746#undef SCC_ENET
747
748
749#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
750#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
751#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
752#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
753#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
754#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
755#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
756#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
757#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
758#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
759#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
760#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
761#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
762
763#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
764
765#endif /* CONFIG_HERMES */
766
fe8c2806
WD		 767/*** ICU862 **********************************************************/
768
769#if defined(CONFIG_ICU862)
770
771#ifdef CONFIG_FEC_ENET
772#define FEC_ENET /* use FEC for EThernet */
773#endif /* CONFIG_FEC_ETHERNET */
774
775#endif /* CONFIG_ICU862 */
776
777/*** IP860 **********************************************************/
778
779#if defined(CONFIG_IP860)
780/* Bits in parallel I/O port registers that have to be set/cleared
781 * to configure the pins for SCC1 use.
782 */
783#define PROFF_ENET PROFF_SCC1
784#define CPM_CR_ENET CPM_CR_CH_SCC1
785#define SCC_ENET 0
786#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
787#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
788#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
789#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
790
791#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
792#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
793#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
794
795#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
796#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
797
798/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
799 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
800 */
801#define SICR_ENET_MASK ((uint)0x000000ff)
802#define SICR_ENET_CLKRT ((uint)0x0000002C)
803#endif /* CONFIG_IP860 */
804
805/*** IVMS8 **********************************************************/
806
807/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
808
809#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
810
811#define FEC_ENET /* use FEC for EThernet */
812#undef SCC_ENET
813
814#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
815
816#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
817
818#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
819#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
820#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
821#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
822#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
823#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
824#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
825#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
826#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
827#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
828#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
829#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
830#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
831
832#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
833
834#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
835
0608e04d
WD		 836/*** KUP4K, KUP4X ****************************************************/
837/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
56f94be3 838
0608e04d 839#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
56f94be3
WD		 840
841#define FEC_ENET /* use FEC for EThernet */
842#undef SCC_ENET
843
844#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
845
846#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
847
848#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
849#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
850#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
851#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
852#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
853#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
854#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
855#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
856#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
857#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
858#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
859#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
860#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
861
862#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
863
864#endif /* CONFIG_KUP4K */
865
fe8c2806
WD		 866/*** LWMON **********************************************************/
867
281e00a3 868#if defined(CONFIG_LWMON)
fe8c2806
WD		 869/* Bits in parallel I/O port registers that have to be set/cleared
870 * to configure the pins for SCC2 use.
871 */
872#define PROFF_ENET PROFF_SCC2
873#define CPM_CR_ENET CPM_CR_CH_SCC2
874#define SCC_ENET 1
875#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
876#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
877#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
878#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
879
880#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
881
882#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
883#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
884
885/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
886 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
887 */
888#define SICR_ENET_MASK ((uint)0x0000ff00)
889#define SICR_ENET_CLKRT ((uint)0x00003E00)
890#endif /* CONFIG_LWMON */
891
892/*** NX823 ***********************************************/
893
894#if defined(CONFIG_NX823)
895/* Bits in parallel I/O port registers that have to be set/cleared
896 * to configure the pins for SCC1 use.
897 */
898#define PROFF_ENET PROFF_SCC2
899#define CPM_CR_ENET CPM_CR_CH_SCC2
900#define SCC_ENET 1
7c7a23bd
WD		 901#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
902#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
903#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
904#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
fe8c2806 905
7c7a23bd 906#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
fe8c2806 907
7c7a23bd
WD		 908#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
909#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
fe8c2806
WD		 910
911/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
912 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
913 */
7c7a23bd
WD		 914#define SICR_ENET_MASK ((uint)0x0000ff00)
915#define SICR_ENET_CLKRT ((uint)0x00002f00)
fe8c2806
WD		 916
917#endif /* CONFIG_NX823 */
918
919/*** MBX ************************************************************/
920
921#ifdef CONFIG_MBX
922/* Bits in parallel I/O port registers that have to be set/cleared
923 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
924 * to the MBX860 board. Any two of the four available clocks could be
925 * used, and the MPC860 cookbook manual has an example using different
926 * clock pins.
927 */
928#define PROFF_ENET PROFF_SCC1
929#define CPM_CR_ENET CPM_CR_CH_SCC1
930#define SCC_ENET 0
931#define PA_ENET_RXD ((ushort)0x0001)
932#define PA_ENET_TXD ((ushort)0x0002)
933#define PA_ENET_TCLK ((ushort)0x0200)
934#define PA_ENET_RCLK ((ushort)0x0800)
935#define PC_ENET_TENA ((ushort)0x0001)
936#define PC_ENET_CLSN ((ushort)0x0010)
937#define PC_ENET_RENA ((ushort)0x0020)
938
939/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
940 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
941 */
942#define SICR_ENET_MASK ((uint)0x000000ff)
943#define SICR_ENET_CLKRT ((uint)0x0000003d)
944#endif /* CONFIG_MBX */
945
d044954f 946/*** KM8XX *********************************************************/
381e4e63 947
d044954f 948/* The KM8XX Service Module uses SCC3 for Ethernet */
381e4e63 949
d044954f 950#ifdef CONFIG_KM8XX
381e4e63
HS		 951#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
952#define CPM_CR_ENET CPM_CR_CH_SCC3
953#define SCC_ENET 2
954#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
955#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
956#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
957#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
958
959#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
960
961#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
962#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
963
964/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
965 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
966 */
967#define SICR_ENET_MASK ((uint)0x00FF0000)
968#define SICR_ENET_CLKRT ((uint)0x00250000)
d044954f 969#endif /* CONFIG_KM8XX */
381e4e63
HS		 970
971
fe8c2806
WD		 972/*** MHPC ********************************************************/
973
974#if defined(CONFIG_MHPC)
975/* This ENET stuff is for the MHPC with ethernet on SCC2.
976 * Note TENA is on Port B.
977 */
978#define PROFF_ENET PROFF_SCC2
979#define CPM_CR_ENET CPM_CR_CH_SCC2
980#define SCC_ENET 1
981#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
982#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
983#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
984#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
985#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
986#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
987#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
988
989#define SICR_ENET_MASK ((uint)0x0000ff00)
990#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
991#endif /* CONFIG_MHPC */
992
608c9146
WD		 993/*** NETVIA *******************************************************/
994
dc7c9a1a
WD		 995/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
996#if ( defined CONFIG_SVM_SC8xx )
997# ifndef CONFIG_FEC_ENET
998
999#define PROFF_ENET PROFF_SCC2
1000#define CPM_CR_ENET CPM_CR_CH_SCC2
1001#define SCC_ENET 1
1002
1003 /* Bits in parallel I/O port registers that have to be set/cleared
1004 * * * * to configure the pins for SCC2 use.
1005 * * * */
1006#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1007#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1008#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
1009#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1010
1011#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1012
1013#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1014#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1015/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1016 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1017 * * * */
1018#define SICR_ENET_MASK ((uint)0x0000ff00)
1019#define SICR_ENET_CLKRT ((uint)0x00003700)
1020
1021# else /* Use FEC for Fast Ethernet */
1022
1023#undef SCC_ENET
1024#define FEC_ENET
1025
1026#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1027#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1028#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1029#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1030#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1031#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1032#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1033#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1034#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1035#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1036#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1037#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1038#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1039
1040#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1041
1042# endif /* CONFIG_FEC_ENET */
1043#endif /* CONFIG_SVM_SC8xx */
8bde7f77
WD		 1044
1045
608c9146
WD		 1046#if defined(CONFIG_NETVIA)
1047/* Bits in parallel I/O port registers that have to be set/cleared
1048 * to configure the pins for SCC2 use.
1049 */
1050#define PROFF_ENET PROFF_SCC2
1051#define CPM_CR_ENET CPM_CR_CH_SCC2
1052#define SCC_ENET 1
1053#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1054#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1055#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1056#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1057
993cad93
WD		 1058#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
1059# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
1060#elif CONFIG_NETVIA_VERSION >= 2
1061# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
1062#endif
1063
608c9146
WD		 1064#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
1065
1066#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1067#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1068
1069/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1070 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1071 */
1072#define SICR_ENET_MASK ((uint)0x0000ff00)
1073#define SICR_ENET_CLKRT ((uint)0x00002f00)
1074
1075#endif /* CONFIG_NETVIA */
1076
3bbc899f
WD		 1077/*** QS850/QS823 ***************************************************/
1078
1079#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
1080#undef FEC_ENET /* Don't use FEC for EThernet */
1081
1082#define PROFF_ENET PROFF_SCC2
1083#define CPM_CR_ENET CPM_CR_CH_SCC2
1084#define SCC_ENET 1
1085
1086#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
1087#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
1088#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
1089#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
1090#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
1091#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
1092#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
1093#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
1094#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
1095#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
1096
1097/* SCC2 TXCLK from CLK2
1098 * SCC2 RXCLK from CLK4
1099 * SCC2 Connected to NMSI */
1100#define SICR_ENET_MASK ((uint)0x00007F00)
1101#define SICR_ENET_CLKRT ((uint)0x00003D00)
1102
1103#endif /* CONFIG_QS850/QS823 */
1104
1105/*** QS860T ***************************************************/
1106
1107#ifdef CONFIG_QS860T
1108#ifdef CONFIG_FEC_ENET
1109#define FEC_ENET /* use FEC for EThernet */
1110#endif /* CONFIG_FEC_ETHERNET */
1111
1112/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
1113#define PROFF_ENET PROFF_SCC1
1114#define CPM_CR_ENET CPM_CR_CH_SCC1
1115#define SCC_ENET 0
1116
1117#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
1118#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
1119#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
1120#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
1121#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
1122#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
1123#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
1124
1125#define SICR_ENET_MASK ((uint)0x000000ff)
1126/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
1127#define SICR_ENET_CLKRT ((uint)0x0000003D)
1128
1129#endif /* CONFIG_QS860T */
1130
fe8c2806
WD		 1131/*** RPXCLASSIC *****************************************************/
1132
1133#ifdef CONFIG_RPXCLASSIC
1134
1135#ifdef CONFIG_FEC_ENET
1136
1137# define FEC_ENET /* use FEC for EThernet */
1138# undef SCC_ENET
1139
1140#else /* ! CONFIG_FEC_ENET */
1141
1142/* Bits in parallel I/O port registers that have to be set/cleared
1143 * to configure the pins for SCC1 use.
1144 */
1145#define PROFF_ENET PROFF_SCC1
1146#define CPM_CR_ENET CPM_CR_CH_SCC1
1147#define SCC_ENET 0
1148#define PA_ENET_RXD ((ushort)0x0001)
1149#define PA_ENET_TXD ((ushort)0x0002)
1150#define PA_ENET_TCLK ((ushort)0x0200)
1151#define PA_ENET_RCLK ((ushort)0x0800)
1152#define PB_ENET_TENA ((uint)0x00001000)
1153#define PC_ENET_CLSN ((ushort)0x0010)
1154#define PC_ENET_RENA ((ushort)0x0020)
1155
1156/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1157 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1158 */
1159#define SICR_ENET_MASK ((uint)0x000000ff)
1160#define SICR_ENET_CLKRT ((uint)0x0000003d)
1161
1162#endif /* CONFIG_FEC_ENET */
1163
1164#endif /* CONFIG_RPXCLASSIC */
1165
1166/*** RPXLITE ********************************************************/
1167
1168#ifdef CONFIG_RPXLITE
1169/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
1170 * this may be unique to the RPX-Lite configuration.
1171 * Note TENA is on Port B.
1172 */
1173#define PROFF_ENET PROFF_SCC2
1174#define CPM_CR_ENET CPM_CR_CH_SCC2
1175#define SCC_ENET 1
1176#define PA_ENET_RXD ((ushort)0x0004)
1177#define PA_ENET_TXD ((ushort)0x0008)
1178#define PA_ENET_TCLK ((ushort)0x0200)
1179#define PA_ENET_RCLK ((ushort)0x0800)
73a8b27c
WD		 1180#if defined(CONFIG_RMU)
1181#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
1182#else
fe8c2806 1183#define PB_ENET_TENA ((uint)0x00002000)
73a8b27c 1184#endif
fe8c2806
WD		 1185#define PC_ENET_CLSN ((ushort)0x0040)
1186#define PC_ENET_RENA ((ushort)0x0080)
1187
1188#define SICR_ENET_MASK ((uint)0x0000ff00)
1189#define SICR_ENET_CLKRT ((uint)0x00003d00)
1190#endif /* CONFIG_RPXLITE */
1191
1192/*** SM850 *********************************************************/
1193
1194/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1195
1196#ifdef CONFIG_SM850
1197#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
1198#define CPM_CR_ENET CPM_CR_CH_SCC3
1199#define SCC_ENET 2
1200#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
1201#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
1202#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1203#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1204
1205#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1206#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
1207
1208#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
1209#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
1210
1211/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1212 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1213 */
1214#define SICR_ENET_MASK ((uint)0x00FF0000)
1215#define SICR_ENET_CLKRT ((uint)0x00260000)
1216#endif /* CONFIG_SM850 */
1217
1218/*** SPD823TS ******************************************************/
1219
1220#ifdef CONFIG_SPD823TS
1221/* Bits in parallel I/O port registers that have to be set/cleared
1222 * to configure the pins for SCC2 use.
1223 */
1224#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
1225#define CPM_CR_ENET CPM_CR_CH_SCC2
1226#define SCC_ENET 1
1227#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
1228#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
1229#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1230#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1231#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1232#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1233
1234#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1235
1236#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1237#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1238#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
1239
1240/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1241 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1242 */
1243#define SICR_ENET_MASK ((uint)0x0000ff00)
1244#define SICR_ENET_CLKRT ((uint)0x00002E00)
1245#endif /* CONFIG_SPD823TS */
1246
1247/*** SXNI855T ******************************************************/
1248
1249#if defined(CONFIG_SXNI855T)
1250
1251#ifdef CONFIG_FEC_ENET
1252#define FEC_ENET /* use FEC for Ethernet */
1253#endif /* CONFIG_FEC_ETHERNET */
1254
1255#endif /* CONFIG_SXNI855T */
1256
1b0757ec 1257/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
fe8c2806
WD		 1258
1259#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
71f95118 1260 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
1b0757ec
WD		 1261 defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
1262 defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
1263 defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
1264 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
090eb735 1265
fe8c2806
WD		 1266/* Bits in parallel I/O port registers that have to be set/cleared
1267 * to configure the pins for SCC2 use.
1268 */
1269#define PROFF_ENET PROFF_SCC2
1270#define CPM_CR_ENET CPM_CR_CH_SCC2
2b4f778f 1271#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
fe8c2806 1272#define SCC_ENET 1
2b4f778f 1273#endif
fe8c2806
WD		 1274#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1275#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1276#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1277#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1278
1279#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1280
1281#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1282#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1283#if defined(CONFIG_R360MPI)
1284#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1285#endif /* CONFIG_R360MPI */
1286
1287/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1288 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1289 */
1290#define SICR_ENET_MASK ((uint)0x0000ff00)
1291#define SICR_ENET_CLKRT ((uint)0x00002600)
090eb735
MK		 1292
1293# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1294#define FEC_ENET
1295# endif /* CONFIG_FEC_ENET */
1296
71f95118 1297#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
fe8c2806 1298
d4ca31c4 1299/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
fe8c2806 1300
71f95118
WD		 1301#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
1302 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
d4ca31c4
WD		 1303 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
1304 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
fe8c2806
WD		 1305
1306# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
1307
1308/* Bits in parallel I/O port registers that have to be set/cleared
1309 * to configure the pins for SCC1 use.
1310 */
1311#define PROFF_ENET PROFF_SCC1
1312#define CPM_CR_ENET CPM_CR_CH_SCC1
1313#define SCC_ENET 0
1314#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
1315#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
1316#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1317#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1318
1319#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
1320#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
1321#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
1322
1323/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1324 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1325 */
1326#define SICR_ENET_MASK ((uint)0x000000ff)
1327#define SICR_ENET_CLKRT ((uint)0x00000026)
1328
1329# endif /* CONFIG_SCC1_ENET */
1330
1331# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1332
1333#define FEC_ENET
1334
1335#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1336#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1337#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1338#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1339#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1340#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1341#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1342#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1343#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1344#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1345#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1346#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1347#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1348
1349#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1350
1351# endif /* CONFIG_FEC_ENET */
71f95118 1352#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
fe8c2806 1353
608c9146
WD		 1354/*** V37 **********************************************************/
1355
1356#ifdef CONFIG_V37
1357/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
1358 * this may be unique to the Marel V37 configuration.
1359 * Note TENA is on Port B.
fe8c2806
WD		 1360 */
1361#define PROFF_ENET PROFF_SCC2
1362#define CPM_CR_ENET CPM_CR_CH_SCC2
1363#define SCC_ENET 1
608c9146
WD		 1364#define PA_ENET_RXD ((ushort)0x0004)
1365#define PA_ENET_TXD ((ushort)0x0008)
1366#define PA_ENET_TCLK ((ushort)0x0400)
1367#define PA_ENET_RCLK ((ushort)0x0200)
1368#define PB_ENET_TENA ((uint)0x00002000)
1369#define PC_ENET_CLSN ((ushort)0x0040)
1370#define PC_ENET_RENA ((ushort)0x0080)
fe8c2806 1371
fe8c2806 1372#define SICR_ENET_MASK ((uint)0x0000ff00)
608c9146
WD		 1373#define SICR_ENET_CLKRT ((uint)0x00002e00)
1374#endif /* CONFIG_V37 */
fe8c2806 1375
3bbc899f 1376
fe8c2806
WD		 1377/*********************************************************************/
1378
1379/* SCC Event register as used by Ethernet.
1380*/
1381#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
1382#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
1383#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
1384#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
1385#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
1386#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
1387
1388/* SCC Mode Register (PSMR) as used by Ethernet.
1389*/
1390#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
1391#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
1392#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
1393#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
1394#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
1395#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
1396#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
1397#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
1398#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
1399#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
1400#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
1401#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
1402#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
1403
1404/* Buffer descriptor control/status used by Ethernet receive.
1405*/
1406#define BD_ENET_RX_EMPTY ((ushort)0x8000)
1407#define BD_ENET_RX_WRAP ((ushort)0x2000)
1408#define BD_ENET_RX_INTR ((ushort)0x1000)
1409#define BD_ENET_RX_LAST ((ushort)0x0800)
1410#define BD_ENET_RX_FIRST ((ushort)0x0400)
1411#define BD_ENET_RX_MISS ((ushort)0x0100)
1412#define BD_ENET_RX_LG ((ushort)0x0020)
1413#define BD_ENET_RX_NO ((ushort)0x0010)
1414#define BD_ENET_RX_SH ((ushort)0x0008)
1415#define BD_ENET_RX_CR ((ushort)0x0004)
1416#define BD_ENET_RX_OV ((ushort)0x0002)
1417#define BD_ENET_RX_CL ((ushort)0x0001)
1418#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
1419
1420/* Buffer descriptor control/status used by Ethernet transmit.
1421*/
1422#define BD_ENET_TX_READY ((ushort)0x8000)
1423#define BD_ENET_TX_PAD ((ushort)0x4000)
1424#define BD_ENET_TX_WRAP ((ushort)0x2000)
1425#define BD_ENET_TX_INTR ((ushort)0x1000)
1426#define BD_ENET_TX_LAST ((ushort)0x0800)
1427#define BD_ENET_TX_TC ((ushort)0x0400)
1428#define BD_ENET_TX_DEF ((ushort)0x0200)
1429#define BD_ENET_TX_HB ((ushort)0x0100)
1430#define BD_ENET_TX_LC ((ushort)0x0080)
1431#define BD_ENET_TX_RL ((ushort)0x0040)
1432#define BD_ENET_TX_RCMASK ((ushort)0x003c)
1433#define BD_ENET_TX_UN ((ushort)0x0002)
1434#define BD_ENET_TX_CSL ((ushort)0x0001)
1435#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
1436
1437/* SCC as UART
1438*/
1439typedef struct scc_uart {
1440 sccp_t scc_genscc;
1441 uint scc_res1; /* Reserved */
1442 uint scc_res2; /* Reserved */
1443 ushort scc_maxidl; /* Maximum idle chars */
1444 ushort scc_idlc; /* temp idle counter */
1445 ushort scc_brkcr; /* Break count register */
1446 ushort scc_parec; /* receive parity error counter */
1447 ushort scc_frmec; /* receive framing error counter */
1448 ushort scc_nosec; /* receive noise counter */
1449 ushort scc_brkec; /* receive break condition counter */
1450 ushort scc_brkln; /* last received break length */
1451 ushort scc_uaddr1; /* UART address character 1 */
1452 ushort scc_uaddr2; /* UART address character 2 */
1453 ushort scc_rtemp; /* Temp storage */
1454 ushort scc_toseq; /* Transmit out of sequence char */
1455 ushort scc_char1; /* control character 1 */
1456 ushort scc_char2; /* control character 2 */
1457 ushort scc_char3; /* control character 3 */
1458 ushort scc_char4; /* control character 4 */
1459 ushort scc_char5; /* control character 5 */
1460 ushort scc_char6; /* control character 6 */
1461 ushort scc_char7; /* control character 7 */
1462 ushort scc_char8; /* control character 8 */
1463 ushort scc_rccm; /* receive control character mask */
1464 ushort scc_rccr; /* receive control character register */
1465 ushort scc_rlbc; /* receive last break character */
1466} scc_uart_t;
1467
1468/* SCC Event and Mask registers when it is used as a UART.
1469*/
1470#define UART_SCCM_GLR ((ushort)0x1000)
1471#define UART_SCCM_GLT ((ushort)0x0800)
1472#define UART_SCCM_AB ((ushort)0x0200)
1473#define UART_SCCM_IDL ((ushort)0x0100)
1474#define UART_SCCM_GRA ((ushort)0x0080)
1475#define UART_SCCM_BRKE ((ushort)0x0040)
1476#define UART_SCCM_BRKS ((ushort)0x0020)
1477#define UART_SCCM_CCR ((ushort)0x0008)
1478#define UART_SCCM_BSY ((ushort)0x0004)
1479#define UART_SCCM_TX ((ushort)0x0002)
1480#define UART_SCCM_RX ((ushort)0x0001)
1481
1482/* The SCC PSMR when used as a UART.
1483*/
1484#define SCU_PSMR_FLC ((ushort)0x8000)
1485#define SCU_PSMR_SL ((ushort)0x4000)
1486#define SCU_PSMR_CL ((ushort)0x3000)
1487#define SCU_PSMR_UM ((ushort)0x0c00)
1488#define SCU_PSMR_FRZ ((ushort)0x0200)
1489#define SCU_PSMR_RZS ((ushort)0x0100)
1490#define SCU_PSMR_SYN ((ushort)0x0080)
1491#define SCU_PSMR_DRT ((ushort)0x0040)
1492#define SCU_PSMR_PEN ((ushort)0x0010)
1493#define SCU_PSMR_RPM ((ushort)0x000c)
1494#define SCU_PSMR_REVP ((ushort)0x0008)
1495#define SCU_PSMR_TPM ((ushort)0x0003)
1496#define SCU_PSMR_TEVP ((ushort)0x0003)
1497
1498/* CPM Transparent mode SCC.
1499 */
1500typedef struct scc_trans {
1501 sccp_t st_genscc;
1502 uint st_cpres; /* Preset CRC */
1503 uint st_cmask; /* Constant mask for CRC */
1504} scc_trans_t;
1505
1506#define BD_SCC_TX_LAST ((ushort)0x0800)
1507
1508/* IIC parameter RAM.
1509*/
1510typedef struct iic {
1511 ushort iic_rbase; /* Rx Buffer descriptor base address */
1512 ushort iic_tbase; /* Tx Buffer descriptor base address */
1513 u_char iic_rfcr; /* Rx function code */
1514 u_char iic_tfcr; /* Tx function code */
1515 ushort iic_mrblr; /* Max receive buffer length */
1516 uint iic_rstate; /* Internal */
1517 uint iic_rdp; /* Internal */
1518 ushort iic_rbptr; /* Internal */
1519 ushort iic_rbc; /* Internal */
1520 uint iic_rxtmp; /* Internal */
1521 uint iic_tstate; /* Internal */
1522 uint iic_tdp; /* Internal */
1523 ushort iic_tbptr; /* Internal */
1524 ushort iic_tbc; /* Internal */
1525 uint iic_txtmp; /* Internal */
1526 uint iic_res; /* reserved */
1527 ushort iic_rpbase; /* Relocation pointer */
1528 ushort iic_res2; /* reserved */
1529} iic_t;
1530
1531/* SPI parameter RAM.
1532*/
1533typedef struct spi {
1534 ushort spi_rbase; /* Rx Buffer descriptor base address */
1535 ushort spi_tbase; /* Tx Buffer descriptor base address */
1536 u_char spi_rfcr; /* Rx function code */
1537 u_char spi_tfcr; /* Tx function code */
1538 ushort spi_mrblr; /* Max receive buffer length */
1539 uint spi_rstate; /* Internal */
1540 uint spi_rdp; /* Internal */
1541 ushort spi_rbptr; /* Internal */
1542 ushort spi_rbc; /* Internal */
1543 uint spi_rxtmp; /* Internal */
1544 uint spi_tstate; /* Internal */
1545 uint spi_tdp; /* Internal */
1546 ushort spi_tbptr; /* Internal */
1547 ushort spi_tbc; /* Internal */
1548 uint spi_txtmp; /* Internal */
1549 uint spi_res;
1550 ushort spi_rpbase; /* Relocation pointer */
1551 ushort spi_res2;
1552} spi_t;
1553
1554/* SPI Mode register.
1555*/
1556#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
1557#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
1558#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
1559#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
1560#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
1561#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
1562#define SPMODE_EN ((ushort)0x0100) /* Enable */
1563#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
1564#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
1565
1566#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
1567#define SPMODE_PM(x) ((x) &0xF)
1568
1569/* HDLC parameter RAM.
1570*/
1571
1572typedef struct hdlc_pram_s {
1573 /*
1574 * SCC parameter RAM
1575 */
1576 ushort rbase; /* Rx Buffer descriptor base address */
1577 ushort tbase; /* Tx Buffer descriptor base address */
1578 uchar rfcr; /* Rx function code */
1579 uchar tfcr; /* Tx function code */
1580 ushort mrblr; /* Rx buffer length */
1581 ulong rstate; /* Rx internal state */
1582 ulong rptr; /* Rx internal data pointer */
1583 ushort rbptr; /* rb BD Pointer */
1584 ushort rcount; /* Rx internal byte count */
1585 ulong rtemp; /* Rx temp */
1586 ulong tstate; /* Tx internal state */
1587 ulong tptr; /* Tx internal data pointer */
1588 ushort tbptr; /* Tx BD pointer */
1589 ushort tcount; /* Tx byte count */
1590 ulong ttemp; /* Tx temp */
1591 ulong rcrc; /* temp receive CRC */
1592 ulong tcrc; /* temp transmit CRC */
1593 /*
1594 * HDLC specific parameter RAM
1595 */
1596 uchar res[4]; /* reserved */
1597 ulong c_mask; /* CRC constant */
1598 ulong c_pres; /* CRC preset */
1599 ushort disfc; /* discarded frame counter */
1600 ushort crcec; /* CRC error counter */
1601 ushort abtsc; /* abort sequence counter */
1602 ushort nmarc; /* nonmatching address rx cnt */
1603 ushort retrc; /* frame retransmission cnt */
1604 ushort mflr; /* maximum frame length reg */
1605 ushort max_cnt; /* maximum length counter */
1606 ushort rfthr; /* received frames threshold */
1607 ushort rfcnt; /* received frames count */
1608 ushort hmask; /* user defined frm addr mask */
1609 ushort haddr1; /* user defined frm address 1 */
1610 ushort haddr2; /* user defined frm address 2 */
1611 ushort haddr3; /* user defined frm address 3 */
1612 ushort haddr4; /* user defined frm address 4 */
1613 ushort tmp; /* temp */
1614 ushort tmp_mb; /* temp */
1615} hdlc_pram_t;
1616
1617/* CPM interrupts. There are nearly 32 interrupts generated by CPM
1618 * channels or devices. All of these are presented to the PPC core
1619 * as a single interrupt. The CPM interrupt handler dispatches its
1620 * own handlers, in a similar fashion to the PPC core handler. We
1621 * use the table as defined in the manuals (i.e. no special high
1622 * priority and SCC1 == SCCa, etc...).
1623 */
1624#define CPMVEC_NR 32
7c7a23bd
WD		 1625#define CPMVEC_OFFSET 0x00010000
1626#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
1627#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
1628#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
1629#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
1630#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
1631#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
1632#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
1633#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
1634#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
1635#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
1636#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
1637#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
1638#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
1639#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
1640#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
1641#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
1642#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
1643#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
1644#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
1645#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
1646#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
1647#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
1648#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
1649#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
1650#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
1651#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
1652#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
1653#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
1654#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
fe8c2806
WD		 1655
1656extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1657
1658/* CPM interrupt configuration vector.
1659*/
1660#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
1661#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
1662#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
1663#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
1664#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
1665#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
1666#define CICR_IEN ((uint)0x00000080) /* Int. enable */
1667#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
1668#endif /* __CPM_8XX__ */
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