[people/ms/u-boot.git] / include / configs / A3000.h

/*
 * (C) Copyright 2001, 2002, 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* ------------------------------------------------------------------------- */
/*
 * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
 * http://artismicro.com
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_A3000		1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_BOOTDELAY	5


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


/*
 * Miscellaneous configurable options
 */
#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"A3000> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

/* Print Buffer Size
 */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support		*/
#undef	CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_NET_MULTI		/* Multi ethernet cards support */

/* #define CONFIG_TULIP */
/* #define CONFIG_EEPRO100 */
#define CONFIG_NATSEMI

#define PCI_ENET0_IOADDR		0x80000000
#define PCI_ENET0_MEMADDR		0x80000000
#define PCI_ENET1_IOADDR		0x81000000
#define PCI_ENET1_MEMADDR		0x81000000
#define PCI_ENET2_IOADDR		0x82000000
#define PCI_ENET2_MEMADDR		0x82000000
#define PCI_ENET3_IOADDR		0x83000000
#define PCI_ENET3_MEMADDR		0x83000000


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE			0x00000000

#define CONFIG_SYS_FLASH_BASE0_PRELIM		0xFF000000	/* FLASH bank on RCS#0 */
#define CONFIG_SYS_FLASH_BASE1_PRELIM		0xFF000000	/* FLASH bank on RCS#1 */
#define CONFIG_SYS_FLASH_BASE			CONFIG_SYS_FLASH_BASE0_PRELIM
#define CONFIG_SYS_FLASH_BANKS			{ CONFIG_SYS_FLASH_BASE0_PRELIM }

/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
 * reset vector is actually located at FFB00100, but the 8245
 * takes care of us.
 */
#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100

#define CONFIG_SYS_EUMB_ADDR	    0xFC000000

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

	/* Maximum amount of RAM.
	 */
#define CONFIG_SYS_MAX_RAM_SIZE    0x04000000	/* 0 .. 128 MB of (S)DRAM */


#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

/* #define CONFIG_SYS_MONITOR_BASE	   CONFIG_SYS_TEXT_BASE */
#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)


/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
#define CONFIG_SYS_HZ		     1000

	/* Bit-field values for MCCR1.
	 */
#define CONFIG_SYS_ROMNAL	    7
#define CONFIG_SYS_ROMFAL	    11
#define CONFIG_SYS_DBUS_SIZE	    0x3

	/* Bit-field values for MCCR2.
	 */
#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CONFIG_SYS_BSTOPRE	    121

	/* Bit-field values for MCCR3.
	 */
#define CONFIG_SYS_REFREC	    8	    /* Refresh to activate interval */

	/* Bit-field values for MCCR4.
	 */
#define CONFIG_SYS_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
#define CONFIG_SYS_ACTORW	    3		/* FIXME was 2 */
#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
#define CONFIG_SYS_EXTROM	    1
#define CONFIG_SYS_REGDIMM	    0

#define CONFIG_SYS_PGMAX	    0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/

#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START	    0x3ff00000
#define CONFIG_SYS_BANK1_END	    0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START	    0x3ff00000
#define CONFIG_SYS_BANK2_END	    0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START	    0x3ff00000
#define CONFIG_SYS_BANK3_END	    0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START	    0x3ff00000
#define CONFIG_SYS_BANK4_END	    0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START	    0x3ff00000
#define CONFIG_SYS_BANK5_END	    0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START	    0x3ff00000
#define CONFIG_SYS_BANK6_END	    0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START	    0x3ff00000
#define CONFIG_SYS_BANK7_END	    0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR	    0xff

#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* Max number of sectors per flash	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */


	/* Warining: environment is not EMBEDDED in the U-Boot code.
	 * It's stored in flash separately.
	 */
#define CONFIG_ENV_IS_IN_FLASH	    1
#define CONFIG_ENV_ADDR		0xFFFE0000
#define CONFIG_ENV_SIZE		0x00020000 /* Size of the Environment		*/
#define CONFIG_ENV_SECT_SIZE	0x00020000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
0332990b WD	1	/*
	2	* (C) Copyright 2001, 2002, 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/* ------------------------------------------------------------------------- */
	25	/*
	26	* Configuration settings for the A-3000 board (Artis Microsystems Inc.).
	27	* http://artismicro.com
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_MPC824X 1
	45	#define CONFIG_MPC8245 1
	46	#define CONFIG_A3000 1
	47
2ae18241	48	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
0332990b WD	49
	50	#define CONFIG_CONS_INDEX 1
	51	#define CONFIG_BAUDRATE 9600
6d0f6bcf	52	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
0332990b WD	53
	54	#define CONFIG_BOOTDELAY 5
	55
0332990b	56
11799434 JL	57	/*
	58	* BOOTP options
	59	*/
	60	#define CONFIG_BOOTP_BOOTFILESIZE
	61	#define CONFIG_BOOTP_BOOTPATH
	62	#define CONFIG_BOOTP_GATEWAY
	63	#define CONFIG_BOOTP_HOSTNAME
	64
	65
498ff9a2 JL	66	/*
	67	* Command line configuration.
	68	*/
	69	#include <config_cmd_default.h>
0332990b WD	70
	71
	72	/*
	73	* Miscellaneous configurable options
	74	*/
6d0f6bcf JCPV	75	#undef CONFIG_SYS_LONGHELP /* undef to save memory */
	76	#define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */
	77	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0332990b WD	78
	79	/* Print Buffer Size
	80	*/
6d0f6bcf JCPV	81	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	82	#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
	83	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	84	#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */
0332990b WD	85
	86	/*-----------------------------------------------------------------------
	87	* PCI stuff
	88	*-----------------------------------------------------------------------
	89	*/
	90	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
53677ef1	91	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	92	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	93	#define CONFIG_SYS_I2C_SLAVE 0x7F
0332990b WD	94
	95	/*-----------------------------------------------------------------------
	96	* PCI stuff
	97	*-----------------------------------------------------------------------
	98	*/
53677ef1 WD	99	#define CONFIG_PCI /* include pci support */
	100	#undef CONFIG_PCI_PNP
	101	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
0332990b WD	102
	103	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	104
	105	/* #define CONFIG_TULIP */
	106	/* #define CONFIG_EEPRO100 */
8bde7f77	107	#define CONFIG_NATSEMI
0332990b WD	108
	109	#define PCI_ENET0_IOADDR 0x80000000
	110	#define PCI_ENET0_MEMADDR 0x80000000
	111	#define PCI_ENET1_IOADDR 0x81000000
	112	#define PCI_ENET1_MEMADDR 0x81000000
	113	#define PCI_ENET2_IOADDR 0x82000000
	114	#define PCI_ENET2_MEMADDR 0x82000000
8564acf9 WD	115	#define PCI_ENET3_IOADDR 0x83000000
8564acf9 WD	116	#define PCI_ENET3_MEMADDR 0x83000000
0332990b WD	117
	118
	119	/*-----------------------------------------------------------------------
	120	* Start addresses for the final memory configuration
	121	* (Set up by the startup code)
6d0f6bcf	122	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0332990b	123	*/
6d0f6bcf	124	#define CONFIG_SYS_SDRAM_BASE 0x00000000
0332990b	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
	127	#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
	128	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM
	129	#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM }
0332990b WD	130
	131	/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
	132	* reset vector is actually located at FFB00100, but the 8245
	133	* takes care of us.
	134	*/
6d0f6bcf	135	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
0332990b	136
6d0f6bcf	137	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
0332990b	138
14d0a02a	139	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	140	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	141	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0332990b	142
6d0f6bcf JCPV	143	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	144	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
0332990b WD	145
	146	/* Maximum amount of RAM.
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */
0332990b WD	149
0332990b WD	150
6d0f6bcf JCPV	151	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	152	#undef CONFIG_SYS_RAMBOOT
0332990b	153	#else
6d0f6bcf	154	#define CONFIG_SYS_RAMBOOT
0332990b WD	155	#endif
	156
	157	/*
	158	* NS16550 Configuration
	159	*/
6d0f6bcf JCPV	160	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	161	#define CONFIG_SYS_NS16550_SERIAL
0332990b	162
6d0f6bcf	163	#define CONFIG_SYS_NS16550_REG_SIZE 1
0332990b	164
6d0f6bcf	165	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
0332990b	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
6d0f6bcf JCPV	168	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
0332990b WD	169
	170	/*-----------------------------------------------------------------------
	171	* Definitions for initial stack pointer and data area
	172	*/
	173
14d0a02a	174	/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
6d0f6bcf	175	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	176	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	177	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
0332990b WD	178
	179
	180	/*
	181	* Low Level Configuration Settings
	182	* (address mappings, register initial values, etc.)
	183	* You should know what you are doing if you make changes here.
	184	* For the detail description refer to the MPC8240 user's manual.
	185	*/
	186
	187	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
6d0f6bcf	188	#define CONFIG_SYS_HZ 1000
0332990b WD	189
	190	/* Bit-field values for MCCR1.
	191	*/
6d0f6bcf JCPV	192	#define CONFIG_SYS_ROMNAL 7
	193	#define CONFIG_SYS_ROMFAL 11
	194	#define CONFIG_SYS_DBUS_SIZE 0x3
0332990b WD	195
	196	/* Bit-field values for MCCR2.
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
6d0f6bcf JCPV	199	#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
0332990b WD	200
	201	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	202	*/
6d0f6bcf	203	#define CONFIG_SYS_BSTOPRE 121
0332990b WD	204
	205	/* Bit-field values for MCCR3.
	206	*/
6d0f6bcf	207	#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
0332990b WD	208
	209	/* Bit-field values for MCCR4.
	210	*/
6d0f6bcf JCPV	211	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
	212	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
	213	#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */
	214	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
	215	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	216	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	217	#define CONFIG_SYS_EXTROM 1
	218	#define CONFIG_SYS_REGDIMM 0
0332990b	219
6d0f6bcf	220	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
0332990b	221
6d0f6bcf	222	#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
0332990b WD	223
	224	/* Memory bank settings.
	225	* Only bits 20-29 are actually used from these vales to set the
	226	* start/end addresses. The upper two bits will always be 0, and the lower
	227	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	228	* address. Refer to the MPC8240 book.
	229	*/
	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_BANK0_START 0x00000000
	232	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	233	#define CONFIG_SYS_BANK0_ENABLE 1
	234	#define CONFIG_SYS_BANK1_START 0x3ff00000
	235	#define CONFIG_SYS_BANK1_END 0x3fffffff
	236	#define CONFIG_SYS_BANK1_ENABLE 0
	237	#define CONFIG_SYS_BANK2_START 0x3ff00000
	238	#define CONFIG_SYS_BANK2_END 0x3fffffff
	239	#define CONFIG_SYS_BANK2_ENABLE 0
	240	#define CONFIG_SYS_BANK3_START 0x3ff00000
	241	#define CONFIG_SYS_BANK3_END 0x3fffffff
	242	#define CONFIG_SYS_BANK3_ENABLE 0
	243	#define CONFIG_SYS_BANK4_START 0x3ff00000
	244	#define CONFIG_SYS_BANK4_END 0x3fffffff
	245	#define CONFIG_SYS_BANK4_ENABLE 0
	246	#define CONFIG_SYS_BANK5_START 0x3ff00000
	247	#define CONFIG_SYS_BANK5_END 0x3fffffff
	248	#define CONFIG_SYS_BANK5_ENABLE 0
	249	#define CONFIG_SYS_BANK6_START 0x3ff00000
	250	#define CONFIG_SYS_BANK6_END 0x3fffffff
	251	#define CONFIG_SYS_BANK6_ENABLE 0
	252	#define CONFIG_SYS_BANK7_START 0x3ff00000
	253	#define CONFIG_SYS_BANK7_END 0x3fffffff
	254	#define CONFIG_SYS_BANK7_ENABLE 0
	255
	256	#define CONFIG_SYS_ODCR 0xff
	257
	258	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	259	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	260
	261	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	262	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	263
	264	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	265	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	266
	267	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	268	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	269
	270	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	271	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	272	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	273	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	274	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	275	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	276	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	277	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
0332990b WD	278
	279	/*
	280	* For booting Linux, the board info and command line data
	281	* have to be in the first 8 MB of memory, since this is
	282	* the maximum mapped by the Linux kernel during initialization.
	283	*/
6d0f6bcf	284	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0332990b WD	285
	286	/*-----------------------------------------------------------------------
	287	* FLASH organization
	288	*/
6d0f6bcf JCPV	289	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
6d0f6bcf JCPV	290	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */
0332990b	291
6d0f6bcf JCPV	292	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	293	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0332990b WD	294
	295
	296	/* Warining: environment is not EMBEDDED in the U-Boot code.
	297	* It's stored in flash separately.
	298	*/
5a1aceb0	299	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	300	#define CONFIG_ENV_ADDR 0xFFFE0000
	301	#define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */
	302	#define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */
0332990b WD	303
	304	/*-----------------------------------------------------------------------
	305	* Cache Configuration
	306	*/
6d0f6bcf	307	#define CONFIG_SYS_CACHELINE_SIZE 32
498ff9a2	308	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	309	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
0332990b WD	310	#endif
0332990b WD	311
0332990b	312	#endif /* __CONFIG_H */