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7521af1c WD |
1 | /* |
2 | * AMIRIX.h: AMIRIX specific config options | |
3 | * | |
4 | * Author : Frank Smith (smith at amirix dot com) | |
5 | * | |
6 | * Derived from : other configuration header files in this tree | |
7 | * | |
8 | * This software may be used and distributed according to the terms of | |
9 | * the GNU General Public License (GPL) version 2, incorporated herein by | |
10 | * reference. Drivers based on or derived from this code fall under the GPL | |
11 | * and must retain the authorship, copyright and this license notice. This | |
12 | * file is not a complete program and may only be used when the entire | |
13 | * program is licensed under the GPL. | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
24 | ||
f57f70aa WD |
25 | #define CONFIG_405 1 /* This is a PPC405 CPU */ |
26 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
7521af1c | 27 | |
f57f70aa | 28 | #define CONFIG_AP1000 1 /* ...on an AP1000 board */ |
7521af1c | 29 | |
2ae18241 WD |
30 | /* |
31 | * Start at bottom of RAM, but at an aliased address so that it looks | |
32 | * like it's not in RAM. This is a bit of voodoo to allow it to be | |
33 | * run from RAM instead of Flash. | |
34 | */ | |
35 | #define CONFIG_SYS_TEXT_BASE 0x08000000 | |
2ced53e1 | 36 | #define CONFIG_SYS_LDSCRIPT "board/amirix/ap1000/u-boot.lds" |
2ae18241 | 37 | |
f57f70aa | 38 | #define CONFIG_PCI 1 |
7521af1c | 39 | |
6d0f6bcf JCPV |
40 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
41 | #define CONFIG_SYS_PROMPT "0> " | |
42 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
7521af1c | 43 | |
f57f70aa | 44 | #define CONFIG_COMMAND_EDIT 1 |
7521af1c WD |
45 | #define CONFIG_COMPLETE_ADDRESSES 1 |
46 | ||
5a1aceb0 | 47 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 48 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
7521af1c | 49 | |
9314cee6 | 50 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
5a1aceb0 | 51 | #undef CONFIG_ENV_IS_IN_FLASH |
7521af1c | 52 | #else |
5a1aceb0 | 53 | #ifdef CONFIG_ENV_IS_IN_FLASH |
9314cee6 | 54 | #undef CONFIG_ENV_IS_IN_NVRAM |
7521af1c WD |
55 | #endif |
56 | #endif | |
57 | ||
f57f70aa WD |
58 | #define CONFIG_BAUDRATE 57600 |
59 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
7521af1c | 60 | |
f57f70aa | 61 | #define CONFIG_BOOTCOMMAND "" /* autoboot command */ |
7521af1c | 62 | |
f57f70aa | 63 | #define CONFIG_BOOTARGS "console=ttyS0,57600" |
7521af1c | 64 | |
f57f70aa | 65 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 66 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
7521af1c | 67 | |
498ff9a2 | 68 | |
11799434 JL |
69 | /* |
70 | * BOOTP options | |
71 | */ | |
72 | #define CONFIG_BOOTP_BOOTFILESIZE | |
73 | #define CONFIG_BOOTP_BOOTPATH | |
74 | #define CONFIG_BOOTP_GATEWAY | |
75 | #define CONFIG_BOOTP_HOSTNAME | |
76 | ||
498ff9a2 JL |
77 | /* |
78 | * Command line configuration. | |
79 | */ | |
80 | #include <config_cmd_default.h> | |
81 | ||
82 | #define CONFIG_CMD_ASKENV | |
83 | #define CONFIG_CMD_DHCP | |
84 | #define CONFIG_CMD_ELF | |
85 | #define CONFIG_CMD_IRQ | |
86 | #define CONFIG_CMD_MVENV | |
87 | #define CONFIG_CMD_PCI | |
88 | #define CONFIG_CMD_PING | |
89 | ||
7521af1c | 90 | |
f57f70aa | 91 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
7521af1c | 92 | |
f57f70aa | 93 | #define CONFIG_SYS_CLK_FREQ 30000000 |
7521af1c | 94 | |
f57f70aa | 95 | #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ |
7521af1c | 96 | |
ee8028b7 WD |
97 | /* |
98 | * I2C | |
99 | */ | |
100 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
101 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ | |
102 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
103 | #define CONFIG_SYS_I2C_SPEED 400000 | |
104 | ||
7521af1c WD |
105 | /* |
106 | * Miscellaneous configurable options | |
107 | */ | |
6d0f6bcf | 108 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
498ff9a2 | 109 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 110 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7521af1c | 111 | #else |
6d0f6bcf | 112 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7521af1c | 113 | #endif |
6d0f6bcf JCPV |
114 | /* usually: (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) */ |
115 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+4+16) /* Print Buffer Size */ | |
116 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
117 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
7521af1c | 118 | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_ALT_MEMTEST 1 |
120 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
121 | #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */ | |
7521af1c WD |
122 | |
123 | /* | |
6d0f6bcf JCPV |
124 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
125 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
126 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
7521af1c WD |
127 | * The Linux BASE_BAUD define should match this configuration. |
128 | * baseBaud = cpuClock/(uartDivisor*16) | |
6d0f6bcf | 129 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
7521af1c WD |
130 | * set Linux BASE_BAUD to 403200. |
131 | */ | |
6d0f6bcf JCPV |
132 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
133 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
134 | ||
135 | #define CONFIG_SYS_NS16550_CLK 40000000 | |
136 | #define CONFIG_SYS_DUART_CHAN 0 | |
137 | #define CONFIG_SYS_NS16550_COM1 (0x4C000000 + 0x1000) | |
138 | #define CONFIG_SYS_NS16550_COM2 (0x4C800000 + 0x1000) | |
139 | #define CONFIG_SYS_NS16550_REG_SIZE 4 | |
140 | #define CONFIG_SYS_NS16550 1 | |
141 | #define CONFIG_SYS_INIT_CHAN1 1 | |
142 | #define CONFIG_SYS_INIT_CHAN2 0 | |
7521af1c WD |
143 | |
144 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7521af1c WD |
146 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
147 | ||
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_LOAD_ADDR 0x00200000 /* default load address */ |
149 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
7521af1c | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
7521af1c WD |
152 | |
153 | /*----------------------------------------------------------------------- | |
154 | * Start addresses for the final memory configuration | |
155 | * (Set up by the startup code) | |
6d0f6bcf | 156 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
7521af1c | 157 | */ |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
159 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
14d0a02a | 160 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ |
162 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
7521af1c WD |
163 | |
164 | /* | |
165 | * For booting Linux, the board info and command line data | |
166 | * have to be in the first 8 MB of memory, since this is | |
167 | * the maximum mapped by the Linux kernel during initialization. | |
168 | */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7521af1c WD |
170 | /*----------------------------------------------------------------------- |
171 | * FLASH organization | |
172 | */ | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_FLASH_CFI 1 |
174 | #define CONFIG_SYS_PROGFLASH_BASE CONFIG_SYS_FLASH_BASE | |
175 | #define CONFIG_SYS_CONFFLASH_BASE 0x24000000 | |
7521af1c | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
178 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
7521af1c | 179 | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
181 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
7521af1c | 182 | |
6d0f6bcf | 183 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ |
7521af1c WD |
184 | |
185 | /* BEG ENVIRONNEMENT FLASH */ | |
5a1aceb0 | 186 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
187 | #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
188 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
189 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */ | |
7521af1c WD |
190 | #endif |
191 | /* END ENVIRONNEMENT FLASH */ | |
192 | /*----------------------------------------------------------------------- | |
193 | * NVRAM organization | |
194 | */ | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
196 | #define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ | |
7521af1c | 197 | |
9314cee6 | 198 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
0e8d1586 JCPV |
199 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
200 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 201 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
7521af1c | 202 | #endif |
7521af1c WD |
203 | |
204 | /* | |
205 | * Init Memory Controller: | |
206 | * | |
207 | * BR0/1 and OR0/1 (FLASH) | |
208 | */ | |
209 | ||
6d0f6bcf | 210 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
f57f70aa | 211 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
7521af1c WD |
212 | |
213 | /* Configuration Port location */ | |
f57f70aa | 214 | #define CONFIG_PORT_ADDR 0xF0000500 |
7521af1c WD |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * Definitions for initial stack pointer and data area (in DPRAM) | |
218 | */ | |
219 | ||
6d0f6bcf | 220 | #define CONFIG_SYS_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */ |
553f0982 | 221 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 222 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 223 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
7521af1c WD |
224 | |
225 | /*----------------------------------------------------------------------- | |
226 | * Definitions for Serial Presence Detect EEPROM address | |
227 | * (to get SDRAM settings) | |
228 | */ | |
3df5bea0 | 229 | #define SPD_EEPROM_ADDRESS 0x50 |
7521af1c | 230 | |
498ff9a2 | 231 | #if defined(CONFIG_CMD_KGDB) |
3df5bea0 | 232 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
f57f70aa | 233 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
7521af1c WD |
234 | #endif |
235 | ||
236 | /* JFFS2 stuff */ | |
237 | ||
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
239 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
240 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 1 | |
7521af1c WD |
241 | |
242 | #define CONFIG_NET_MULTI | |
243 | #define CONFIG_E1000 | |
244 | ||
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_ETH_DEV_FN 0x0800 |
246 | #define CONFIG_SYS_ETH_IOBASE 0x31000000 | |
247 | #define CONFIG_SYS_ETH_MEMBASE 0x32000000 | |
7521af1c | 248 | |
3df5bea0 | 249 | #endif /* __CONFIG_H */ |