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a20b27a3 | 1 | /* |
1c686676 MF |
2 | * (C) Copyright 2005-2008 |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
a20b27a3 SR |
5 | * (C) Copyright 2001-2004 |
6 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * board/config.h - configuration options, board specific | |
29 | */ | |
a20b27a3 SR |
30 | #ifndef __CONFIG_H |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
a20b27a3 SR |
37 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
38 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
53677ef1 | 39 | #define CONFIG_APCG405 1 /* ...on a APC405 board */ |
a20b27a3 | 40 | |
2ae18241 WD |
41 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
42 | ||
a20b27a3 | 43 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
1c686676 | 44 | #define CONFIG_BOARD_EARLY_INIT_R 1 |
a20b27a3 SR |
45 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
46 | ||
47 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ | |
48 | ||
04e93ec9 SR |
49 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
50 | ||
1c686676 MF |
51 | #define CONFIG_BAUDRATE 115200 |
52 | #define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */ | |
8e048c43 | 53 | #define CONFIG_BOOTCOUNT_LIMIT 1 |
a20b27a3 SR |
54 | |
55 | #undef CONFIG_BOOTARGS | |
1c686676 | 56 | |
6d0f6bcf | 57 | #define CONFIG_SYS_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \ |
1c686676 | 58 | "fatload usb 0 300000 pImage.initrd" |
6d0f6bcf | 59 | #define CONFIG_SYS_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \ |
1c686676 MF |
60 | "run ramargs addip addcon usbargs;" \ |
61 | "bootm 200000 300000" | |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_USB_ARGS "setenv bootargs $(bootargs) usbboot=1" |
63 | #define CONFIG_SYS_BOOTLIMIT "3" | |
64 | #define CONFIG_SYS_ALT_BOOTCOMMAND "run usb_self;reset" | |
1c686676 MF |
65 | |
66 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
b789cb4a SR |
67 | "hostname=abg405\0" \ |
68 | "bd_type=abg405\0" \ | |
1c686676 | 69 | "serial#=AA0000\0" \ |
b789cb4a SR |
70 | "kernel_addr=fe000000\0" \ |
71 | "ramdisk_addr=fe100000\0" \ | |
72 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
73 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
74 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
75 | "addip=setenv bootargs $(bootargs) " \ | |
76 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
77 | ":$(hostname)::off panic=1\0" \ | |
78 | "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \ | |
79 | " $(optargs)\0" \ | |
80 | "flash_self=run ramargs addip addcon;" \ | |
81 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
82 | "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \ | |
83 | "bootm\0" \ | |
84 | "rootpath=/tftpboot/abg405/target_root\0" \ | |
85 | "img=/tftpboot/abg405/pImage\0" \ | |
86 | "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \ | |
87 | "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ | |
88 | "cp.b 100000 fff80000 80000\0" \ | |
89 | "ipaddr=10.0.111.111\0" \ | |
90 | "netmask=255.255.0.0\0" \ | |
91 | "serverip=10.0.0.190\0" \ | |
92 | "splashimage=ffe80000\0" \ | |
6d0f6bcf JCPV |
93 | "usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0" \ |
94 | "usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0" \ | |
95 | "usbargs="CONFIG_SYS_USB_ARGS"\0" \ | |
96 | "bootlimit="CONFIG_SYS_BOOTLIMIT"\0" \ | |
97 | "altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0" \ | |
b789cb4a | 98 | "" |
8e048c43 | 99 | #define CONFIG_BOOTCOMMAND "run flash_self;reset" |
1c686676 MF |
100 | |
101 | #define CONFIG_ETHADDR 00:02:27:8e:00:00 | |
a20b27a3 SR |
102 | |
103 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 104 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
a20b27a3 | 105 | |
1c686676 MF |
106 | #define CONFIG_NET_MULTI 1 |
107 | #undef CONFIG_HAS_ETH1 | |
108 | ||
38570b2f | 109 | #define CONFIG_PPC4xx_EMAC |
a20b27a3 | 110 | #define CONFIG_MII 1 /* MII PHY management */ |
1c686676 MF |
111 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
112 | #define CONFIG_LXT971_NO_SLEEP 1 | |
113 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ | |
a20b27a3 SR |
114 | |
115 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
116 | ||
11799434 JL |
117 | /* |
118 | * BOOTP options | |
119 | */ | |
120 | #define CONFIG_BOOTP_BOOTFILESIZE | |
121 | #define CONFIG_BOOTP_BOOTPATH | |
122 | #define CONFIG_BOOTP_GATEWAY | |
123 | #define CONFIG_BOOTP_HOSTNAME | |
124 | ||
498ff9a2 JL |
125 | /* |
126 | * Command line configuration. | |
127 | */ | |
128 | #include <config_cmd_default.h> | |
129 | ||
74de7aef | 130 | #define CONFIG_CMD_DATE |
498ff9a2 | 131 | #define CONFIG_CMD_DHCP |
74de7aef | 132 | #define CONFIG_CMD_EEPROM |
498ff9a2 | 133 | #define CONFIG_CMD_ELF |
74de7aef | 134 | #define CONFIG_CMD_FAT |
498ff9a2 | 135 | #define CONFIG_CMD_I2C |
74de7aef WD |
136 | #define CONFIG_CMD_IDE |
137 | #define CONFIG_CMD_IRQ | |
498ff9a2 | 138 | #define CONFIG_CMD_MII |
74de7aef | 139 | #define CONFIG_CMD_PCI |
498ff9a2 | 140 | #define CONFIG_CMD_PING |
74de7aef | 141 | #define CONFIG_CMD_SOURCE |
1c686676 | 142 | #define CONFIG_CMD_USB |
a20b27a3 SR |
143 | |
144 | #define CONFIG_MAC_PARTITION | |
145 | #define CONFIG_DOS_PARTITION | |
146 | ||
147 | #define CONFIG_SUPPORT_VFAT | |
148 | ||
1c686676 | 149 | #define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */ |
a20b27a3 | 150 | |
1c686676 | 151 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
a20b27a3 | 152 | |
1c686676 | 153 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
6d0f6bcf | 154 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
1c686676 MF |
155 | |
156 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
a20b27a3 SR |
157 | |
158 | /* | |
159 | * Miscellaneous configurable options | |
160 | */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
162 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
1c686676 | 163 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a20b27a3 | 164 | |
498ff9a2 | 165 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 166 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a20b27a3 | 167 | #else |
6d0f6bcf | 168 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a20b27a3 | 169 | #endif |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
171 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
172 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a20b27a3 | 173 | |
6d0f6bcf | 174 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
a20b27a3 | 175 | |
6d0f6bcf | 176 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
a20b27a3 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
179 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
a20b27a3 | 180 | |
550650dd SR |
181 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
182 | #define CONFIG_SYS_NS16550 | |
183 | #define CONFIG_SYS_NS16550_SERIAL | |
184 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
185 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
186 | ||
6d0f6bcf | 187 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ |
a20b27a3 SR |
188 | |
189 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
1c686676 | 191 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
efe2a4d5 | 192 | 57600, 115200, 230400, 460800, 921600 } |
a20b27a3 | 193 | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
195 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
a20b27a3 | 196 | |
6d0f6bcf | 197 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
a20b27a3 SR |
198 | |
199 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
200 | ||
201 | /* Only interrupt boot if space is pressed */ | |
202 | /* If a long serial cable is connected but */ | |
203 | /* other end is dead, garbage will be read */ | |
1c686676 | 204 | #define CONFIG_AUTOBOOT_KEYED 1 |
c37207d7 WD |
205 | #define CONFIG_AUTOBOOT_PROMPT \ |
206 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
1c686676 | 207 | #undef CONFIG_AUTOBOOT_DELAY_STR |
a20b27a3 SR |
208 | #define CONFIG_AUTOBOOT_STOP_STR " " |
209 | ||
1c686676 | 210 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
a20b27a3 | 211 | |
6d0f6bcf | 212 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
a20b27a3 | 213 | |
1c686676 | 214 | /* |
a20b27a3 | 215 | * PCI stuff |
a20b27a3 | 216 | */ |
1c686676 MF |
217 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
218 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
219 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
a20b27a3 | 220 | |
1c686676 MF |
221 | #define CONFIG_PCI /* include pci support */ |
222 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
a20b27a3 | 223 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
efe2a4d5 | 224 | /* resource configuration */ |
a20b27a3 | 225 | |
1c686676 MF |
226 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
227 | #define CONFIG_PCI_SKIP_HOST_BRIDGE 1 | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
229 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
230 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
231 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
232 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
233 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
234 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
235 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
236 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
a20b27a3 | 237 | |
1c686676 | 238 | /* |
a20b27a3 | 239 | * IDE/ATA stuff |
a20b27a3 | 240 | */ |
1c686676 MF |
241 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
242 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
243 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
a20b27a3 | 244 | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
246 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */ | |
a20b27a3 | 247 | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
249 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
a20b27a3 | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
252 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ | |
253 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
a20b27a3 | 254 | |
1c686676 | 255 | /* |
a20b27a3 SR |
256 | * Start addresses for the final memory configuration |
257 | * (Set up by the startup code) | |
6d0f6bcf | 258 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a20b27a3 | 259 | */ |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
261 | #define CONFIG_SYS_MONITOR_BASE 0xFFF80000 | |
262 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
263 | #define CONFIG_SYS_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ | |
a20b27a3 SR |
264 | |
265 | /* | |
266 | * For booting Linux, the board info and command line data | |
267 | * have to be in the first 8 MB of memory, since this is | |
268 | * the maximum mapped by the Linux kernel during initialization. | |
269 | */ | |
6d0f6bcf | 270 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */ |
a20b27a3 | 271 | |
1c686676 | 272 | /* |
a20b27a3 SR |
273 | * FLASH organization |
274 | */ | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
276 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
00b1883a | 277 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf | 278 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 |
280 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 | |
281 | #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 | |
282 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
283 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \ | |
1c686676 MF |
284 | {0xfe000000, 0x500000}, \ |
285 | {0xffe80000, 0x180000} \ | |
286 | } | |
6d0f6bcf JCPV |
287 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
288 | #define CONFIG_SYS_FLASH_BANKS_LIST { \ | |
289 | CONFIG_SYS_FLASH_BASE, \ | |
290 | CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \ | |
1c686676 | 291 | } |
6d0f6bcf | 292 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
a20b27a3 | 293 | |
1c686676 | 294 | /* |
a20b27a3 SR |
295 | * Environment Variable setup |
296 | */ | |
bb1f8b4f | 297 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 | 298 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the */ |
1c686676 | 299 | /* beginning of the EEPROM */ |
0e8d1586 | 300 | #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ |
1c686676 | 301 | #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */ |
a20b27a3 | 302 | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
304 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ | |
a20b27a3 | 305 | |
1c686676 | 306 | /* |
a20b27a3 SR |
307 | * I2C EEPROM (CAT24WC16) for environment |
308 | */ | |
309 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
d3061c69 | 310 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
312 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
a20b27a3 | 313 | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
315 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
1c686676 | 316 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
318 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
a20b27a3 | 319 | /* 16 byte page write mode using*/ |
1c686676 | 320 | /* last 4 bits of the address */ |
6d0f6bcf | 321 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
a20b27a3 | 322 | |
1c686676 | 323 | /* |
a20b27a3 SR |
324 | * External Bus Controller (EBC) Setup |
325 | */ | |
6d0f6bcf JCPV |
326 | #define FLASH0_BA (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */ |
327 | #define FLASH1_BA CONFIG_SYS_FLASH_BASE /* FLASH 1 Base Address */ | |
1c686676 MF |
328 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
329 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ | |
330 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
331 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
332 | #define PS2_BA 0xF0000600 /* PS/2 Base Address */ | |
333 | #define CF_BA 0xF0100000 /* CompactFlash Base Address */ | |
334 | #define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ | |
335 | #define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ | |
336 | #define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ | |
337 | #define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ | |
338 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
339 | ||
6d0f6bcf | 340 | #define CONFIG_SYS_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ |
1c686676 MF |
341 | |
342 | /* Memory Bank 0 (Flash Bank 0) initialization */ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
344 | #define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ | |
345 | #define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP | |
346 | #define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */ | |
a20b27a3 | 347 | |
1c686676 | 348 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
350 | #define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ | |
a20b27a3 SR |
351 | |
352 | /* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */ | |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
354 | #define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 SR |
355 | |
356 | /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
358 | #define CONFIG_SYS_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
359 | |
360 | /* Memory Bank 4 (PCMCIA Slot 1) initialization */ | |
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
362 | #define CONFIG_SYS_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/ | |
a20b27a3 SR |
363 | |
364 | /* Memory Bank 5 (Epson VGA) initialization */ | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ |
366 | #define CONFIG_SYS_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
367 | |
368 | /* Memory Bank 6 (PCMCIA Slot 2) initialization */ | |
6d0f6bcf JCPV |
369 | #define CONFIG_SYS_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
370 | #define CONFIG_SYS_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/ | |
a20b27a3 | 371 | |
1c686676 | 372 | /* |
a20b27a3 SR |
373 | * FPGA stuff |
374 | */ | |
375 | ||
376 | /* FPGA internal regs */ | |
6d0f6bcf JCPV |
377 | #define CONFIG_SYS_FPGA_CTRL 0x008 |
378 | #define CONFIG_SYS_FPGA_CTRL2 0x00a | |
a20b27a3 SR |
379 | |
380 | /* FPGA Control Reg */ | |
6d0f6bcf JCPV |
381 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
382 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 | |
383 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 | |
a20b27a3 | 384 | |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
386 | #define CONFIG_SYS_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */ | |
a20b27a3 SR |
387 | |
388 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
389 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
390 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
391 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
392 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
393 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
a20b27a3 | 394 | |
1c686676 | 395 | /* |
a20b27a3 SR |
396 | * LCD Setup |
397 | */ | |
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */ |
399 | #define CONFIG_SYS_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */ | |
a20b27a3 | 400 | |
1c686676 | 401 | #define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ |
a20b27a3 SR |
402 | |
403 | /* Image information... */ | |
1c686676 | 404 | #define CONFIG_LCD_USED CONFIG_LCD_BIG |
a20b27a3 | 405 | |
6d0f6bcf JCPV |
406 | #define CONFIG_SYS_LCD_MEM CONFIG_SYS_LCD_BIG_MEM |
407 | #define CONFIG_SYS_LCD_REG CONFIG_SYS_LCD_BIG_REG | |
a20b27a3 | 408 | |
6d0f6bcf | 409 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20) |
a20b27a3 | 410 | |
1c686676 | 411 | /* |
a20b27a3 SR |
412 | * Definitions for initial stack pointer and data area (in data cache) |
413 | */ | |
414 | ||
415 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 416 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
a20b27a3 SR |
417 | |
418 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
419 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
420 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
a20b27a3 | 421 | |
6d0f6bcf | 422 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
553f0982 | 423 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
25ddd1fb | 424 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
8e048c43 | 425 | /* reserve some memory for BOOT limit info */ |
6d0f6bcf | 426 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16) |
8e048c43 MF |
427 | |
428 | #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ | |
6d0f6bcf | 429 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8) |
8e048c43 | 430 | #endif |
a20b27a3 | 431 | |
1c686676 MF |
432 | /* |
433 | * PCI OHCI controller | |
434 | */ | |
435 | #define CONFIG_USB_OHCI_NEW 1 | |
436 | #define CONFIG_PCI_OHCI 1 | |
6d0f6bcf JCPV |
437 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
438 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
439 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
1c686676 | 440 | #define CONFIG_USB_STORAGE 1 |
6d0f6bcf | 441 | #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 |
1c686676 MF |
442 | |
443 | #endif /* __CONFIG_H */ |