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ab255f26 | 1 | /* |
8b1ccd86 | 2 | * (C) Copyright 2001-2004 |
ab255f26 WD |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ | |
c837dcb1 WD |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
38 | #define CONFIG_AR405 1 /* ...on a AR405 board */ | |
ab255f26 | 39 | |
2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
41 | ||
c837dcb1 | 42 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
ab255f26 | 43 | |
c837dcb1 | 44 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
ab255f26 | 45 | |
8b1ccd86 SR |
46 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
47 | ||
ab255f26 WD |
48 | #define CONFIG_BAUDRATE 9600 |
49 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
50 | ||
51 | #if 1 | |
52 | #define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */ | |
53 | #else | |
54 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
55 | #endif | |
56 | ||
57 | #if 0 | |
c837dcb1 WD |
58 | #define CONFIG_BOOTARGS "root=/dev/nfs " \ |
59 | "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ | |
ab255f26 WD |
60 | "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" |
61 | #else | |
62 | #define CONFIG_BOOTARGS "root=/dev/hda1 " \ | |
63 | "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" | |
64 | ||
65 | #endif | |
66 | ||
8b1ccd86 SR |
67 | #define CONFIG_PREBOOT /* enable preboot variable */ |
68 | ||
ab255f26 | 69 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 70 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
ab255f26 | 71 | |
96e21f86 | 72 | #define CONFIG_PPC4xx_EMAC |
ab255f26 | 73 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 74 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
8b1ccd86 | 75 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
ab255f26 | 76 | |
498ff9a2 | 77 | |
11799434 JL |
78 | /* |
79 | * BOOTP options | |
80 | */ | |
81 | #define CONFIG_BOOTP_BOOTFILESIZE | |
82 | #define CONFIG_BOOTP_BOOTPATH | |
83 | #define CONFIG_BOOTP_GATEWAY | |
84 | #define CONFIG_BOOTP_HOSTNAME | |
85 | ||
86 | ||
498ff9a2 JL |
87 | /* |
88 | * Command line configuration. | |
89 | */ | |
90 | #include <config_cmd_default.h> | |
91 | ||
92 | #define CONFIG_CMD_DHCP | |
93 | #define CONFIG_CMD_PCI | |
94 | #define CONFIG_CMD_IRQ | |
95 | #define CONFIG_CMD_ELF | |
96 | #define CONFIG_CMD_MII | |
4710cee1 | 97 | #undef CONFIG_CMD_NFS |
498ff9a2 JL |
98 | #define CONFIG_CMD_PING |
99 | #define CONFIG_CMD_BSP | |
100 | ||
ab255f26 WD |
101 | |
102 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
103 | ||
c837dcb1 | 104 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
ab255f26 WD |
105 | |
106 | /* | |
107 | * Miscellaneous configurable options | |
108 | */ | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
110 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
498ff9a2 | 111 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 112 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
ab255f26 | 113 | #else |
6d0f6bcf | 114 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
ab255f26 | 115 | #endif |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
117 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
118 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
ab255f26 | 119 | |
6d0f6bcf | 120 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
8b1ccd86 | 121 | |
6d0f6bcf | 122 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
ab255f26 | 123 | |
8b1ccd86 | 124 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
a20b27a3 SR |
125 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
126 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
8b1ccd86 | 127 | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
129 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
ab255f26 | 130 | |
550650dd SR |
131 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
132 | #define CONFIG_SYS_NS16550 | |
133 | #define CONFIG_SYS_NS16550_SERIAL | |
134 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
135 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
136 | ||
6d0f6bcf | 137 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ |
ab255f26 WD |
138 | |
139 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 140 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8bde7f77 WD |
141 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
142 | 57600, 115200, 230400, 460800, 921600 } | |
ab255f26 | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
145 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
ab255f26 | 146 | |
6d0f6bcf | 147 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
ab255f26 WD |
148 | |
149 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
150 | ||
151 | /*----------------------------------------------------------------------- | |
152 | * PCI stuff | |
153 | *----------------------------------------------------------------------- | |
154 | */ | |
c837dcb1 WD |
155 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
156 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
157 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
ab255f26 | 158 | |
c837dcb1 WD |
159 | #define CONFIG_PCI /* include pci support */ |
160 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
161 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
162 | /* resource configuration */ | |
ab255f26 | 163 | |
c837dcb1 | 164 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
ad10dd9a | 165 | |
a20b27a3 SR |
166 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ |
167 | ||
c837dcb1 | 168 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
ad10dd9a | 169 | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
171 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */ | |
172 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
173 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
174 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
175 | #define CONFIG_SYS_PCI_PTM2LA 0xfff00000 /* point to flash */ | |
176 | #define CONFIG_SYS_PCI_PTM2MS 0xfff00001 /* 1MB, enable */ | |
177 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
ab255f26 WD |
178 | |
179 | /*----------------------------------------------------------------------- | |
180 | * Start addresses for the final memory configuration | |
181 | * (Set up by the startup code) | |
6d0f6bcf | 182 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
ab255f26 | 183 | */ |
6d0f6bcf | 184 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
f3dc7f19 | 185 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
14d0a02a WD |
186 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
187 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
6d0f6bcf | 188 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
ab255f26 WD |
189 | |
190 | /* | |
191 | * For booting Linux, the board info and command line data | |
192 | * have to be in the first 8 MB of memory, since this is | |
193 | * the maximum mapped by the Linux kernel during initialization. | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
ab255f26 WD |
196 | /*----------------------------------------------------------------------- |
197 | * FLASH organization | |
198 | */ | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
200 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
ab255f26 | 201 | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
203 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
ab255f26 | 204 | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
206 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
207 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
ab255f26 WD |
208 | /* |
209 | * The following defines are added for buggy IOP480 byte interface. | |
210 | * All other boards should use the standard values (CPCI405 etc.) | |
211 | */ | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
213 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
214 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
ab255f26 | 215 | |
6d0f6bcf | 216 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
ab255f26 | 217 | |
5a1aceb0 | 218 | #define CONFIG_ENV_IS_IN_FLASH 1 |
f3dc7f19 | 219 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
220 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ |
221 | #define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ | |
a20b27a3 | 222 | |
f3dc7f19 | 223 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 224 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
ab255f26 | 225 | |
ab255f26 WD |
226 | /* |
227 | * Init Memory Controller: | |
228 | * | |
229 | * BR0/1 and OR0/1 (FLASH) | |
230 | */ | |
231 | ||
8b1ccd86 | 232 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
ab255f26 WD |
233 | |
234 | /*----------------------------------------------------------------------- | |
235 | * External Bus Controller (EBC) Setup | |
236 | */ | |
237 | ||
c837dcb1 | 238 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
240 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
ab255f26 | 241 | |
c837dcb1 | 242 | /* Memory Bank 1 (CAN0, 1, 2, 3) initialization */ |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */ |
244 | #define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
ab255f26 | 245 | |
c837dcb1 | 246 | /* Memory Bank 2 (Expension Bus) initialization */ |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */ |
248 | #define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ | |
ab255f26 | 249 | |
c837dcb1 | 250 | /* Memory Bank 3 (16552) initialization */ |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */ |
252 | #define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
ab255f26 | 253 | |
c837dcb1 | 254 | /* Memory Bank 4 (FPGA regs) initialization */ |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */ |
256 | #define CONFIG_SYS_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */ | |
ab255f26 | 257 | |
c837dcb1 | 258 | /* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */ |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_EBC_PB5AP 0x92015480 |
260 | #define CONFIG_SYS_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
ab255f26 WD |
261 | |
262 | /*----------------------------------------------------------------------- | |
c5d22906 | 263 | * Definitions for initial stack pointer and data area (in data cache) |
ab255f26 | 264 | */ |
6d0f6bcf | 265 | #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
ab255f26 | 266 | |
6d0f6bcf | 267 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
553f0982 | 268 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 269 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 270 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
ab255f26 | 271 | |
ab255f26 | 272 | #endif /* __CONFIG_H */ |