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ab255f26 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ | |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
38 | #define CONFIG_AR405 1 /* ...on a AR405 board */ | |
39 | ||
40 | #define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ | |
41 | ||
42 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
43 | ||
44 | #define CONFIG_BAUDRATE 9600 | |
45 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
46 | ||
47 | #if 1 | |
48 | #define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */ | |
49 | #else | |
50 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
51 | #endif | |
52 | ||
53 | #if 0 | |
54 | #define CONFIG_BOOTARGS "root=/dev/nfs " \ | |
55 | "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ | |
56 | "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" | |
57 | #else | |
58 | #define CONFIG_BOOTARGS "root=/dev/hda1 " \ | |
59 | "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" | |
60 | ||
61 | #endif | |
62 | ||
63 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
64 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
65 | ||
66 | #define CONFIG_MII 1 /* MII PHY management */ | |
67 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
68 | ||
69 | #define CONFIG_COMMANDS \ | |
70 | (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV) | |
71 | ||
72 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
73 | #include <cmd_confdefs.h> | |
74 | ||
75 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
76 | ||
77 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
78 | ||
79 | /* | |
80 | * Miscellaneous configurable options | |
81 | */ | |
82 | #define CFG_LONGHELP /* undef to save memory */ | |
83 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
84 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
85 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
86 | #else | |
87 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
88 | #endif | |
89 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
90 | #define CFG_MAXARGS 16 /* max number of command args */ | |
91 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
92 | ||
93 | #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ | |
94 | ||
95 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
96 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
97 | ||
98 | #define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ | |
99 | ||
100 | /* The following table includes the supported baudrates */ | |
101 | #define CFG_BAUDRATE_TABLE \ | |
102 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ | |
103 | 57600, 115200, 230400, 460800, 921600 } | |
104 | ||
105 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
106 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
107 | ||
108 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
109 | ||
110 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
111 | ||
112 | /*----------------------------------------------------------------------- | |
113 | * PCI stuff | |
114 | *----------------------------------------------------------------------- | |
115 | */ | |
116 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
117 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
118 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
119 | ||
120 | #define CONFIG_PCI /* include pci support */ | |
121 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
122 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
123 | /* resource configuration */ | |
124 | ||
ad10dd9a SR |
125 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
126 | ||
127 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ | |
128 | ||
ab255f26 WD |
129 | #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
130 | #define CFG_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */ | |
131 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
132 | #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
133 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
134 | #define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */ | |
135 | #define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */ | |
136 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
137 | ||
138 | /*----------------------------------------------------------------------- | |
139 | * Start addresses for the final memory configuration | |
140 | * (Set up by the startup code) | |
141 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
142 | */ | |
143 | #define CFG_SDRAM_BASE 0x00000000 | |
144 | #define CFG_FLASH_BASE 0xFFFD0000 | |
145 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
146 | #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ | |
147 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
148 | ||
149 | /* | |
150 | * For booting Linux, the board info and command line data | |
151 | * have to be in the first 8 MB of memory, since this is | |
152 | * the maximum mapped by the Linux kernel during initialization. | |
153 | */ | |
154 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
155 | /*----------------------------------------------------------------------- | |
156 | * FLASH organization | |
157 | */ | |
158 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
159 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
160 | ||
161 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
162 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
163 | ||
164 | #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ | |
165 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
166 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
167 | /* | |
168 | * The following defines are added for buggy IOP480 byte interface. | |
169 | * All other boards should use the standard values (CPCI405 etc.) | |
170 | */ | |
171 | #define CFG_FLASH_READ0 0x0000 /* 0 is standard */ | |
172 | #define CFG_FLASH_READ1 0x0001 /* 1 is standard */ | |
173 | #define CFG_FLASH_READ2 0x0002 /* 2 is standard */ | |
174 | ||
175 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
176 | ||
177 | #define CFG_ENV_IS_IN_FLASH 1 | |
178 | #define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ | |
179 | #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
180 | ||
181 | #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ | |
182 | ||
183 | /*----------------------------------------------------------------------- | |
184 | * Cache Configuration | |
185 | */ | |
186 | #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ | |
187 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
188 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
189 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
190 | #endif | |
191 | ||
192 | /* | |
193 | * Init Memory Controller: | |
194 | * | |
195 | * BR0/1 and OR0/1 (FLASH) | |
196 | */ | |
197 | ||
198 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
199 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
200 | ||
201 | /*----------------------------------------------------------------------- | |
202 | * External Bus Controller (EBC) Setup | |
203 | */ | |
204 | ||
205 | /* Memory Bank 0 (Flash Bank 0) initialization */ | |
206 | #define CFG_EBC_PB0AP 0x92015480 | |
207 | #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
208 | ||
209 | /* Memory Bank 1 (CAN0, 1, 2, 3) initialization */ | |
210 | #define CFG_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */ | |
211 | #define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
212 | ||
213 | /* Memory Bank 2 (Expension Bus) initialization */ | |
214 | #define CFG_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */ | |
215 | #define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ | |
216 | ||
217 | /* Memory Bank 3 (16552) initialization */ | |
218 | #define CFG_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */ | |
219 | #define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
220 | ||
221 | /* Memory Bank 4 (FPGA regs) initialization */ | |
222 | #define CFG_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */ | |
223 | #define CFG_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */ | |
224 | ||
225 | /* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */ | |
226 | #define CFG_EBC_PB5AP 0x92015480 | |
227 | #define CFG_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
228 | ||
229 | /*----------------------------------------------------------------------- | |
230 | * Definitions for initial stack pointer and data area (in RAM) | |
231 | */ | |
232 | #define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ | |
233 | #define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ | |
234 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
235 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
236 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
237 | ||
238 | ||
239 | /* | |
240 | * Internal Definitions | |
241 | * | |
242 | * Boot Flags | |
243 | */ | |
244 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
245 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
246 | ||
247 | #endif /* __CONFIG_H */ |