[people/ms/u-boot.git] / include / configs / ATUM8548.h

/*
 * Copyright 2007
 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
 *
 * Copyright 2004, 2007 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * atum8548 board configuration file
 *
 * Please refer to doc/README.atum8548 for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* Debug Options, Disable in production
#define ET_DEBUG		1
#define CONFIG_PANIC_HANG	1
#define DEBUG			1
*/

/* CPLD Configuration Options */
#define MPC85xx_ATUM_CLKOCR            0x80000002

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548		1	/* MPC8548 specific */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xfff80000
#endif

#define CONFIG_PCI		1	/* enable any pci type devices */
#define CONFIG_PCI1		1	/* PCI controller 1 */
#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
#define CONFIG_PCI2             1	/* PCI controller 2 */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */

#define CONFIG_TSEC_ENET	1	/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#define CONFIG_SYS_CLK_FREQ	33000000

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#define CONFIG_CMD_SDRAM		1	/* SDRAM DIMM SPD info printout */
#define CONFIG_ENABLE_36BIT_PHYS	1
#undef	CONFIG_SYS_DRAM_TEST
#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */

#define PCI_SPEED		33333000        /* CPLD currenlty does not have PCI setup info */

/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Manually set up DDR parameters */
#define CONFIG_SYS_SDRAM_SIZE	1024		/* DDR is 1024MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f	/* 0-1024 */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000102
#define CONFIG_SYS_DDR_TIMING_0	0x00260802
#define CONFIG_SYS_DDR_TIMING_1	0x38355322
#define CONFIG_SYS_DDR_TIMING_2	0x039048c7
#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE	0x00000432
#define CONFIG_SYS_DDR_INTERVAL	0x05150100
#define DDR_SDRAM_CFG	0x43000000

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * based on flash chip S29GL01GP
 * One bank, 128M, using the CFI driver.
 * Boot from BR0 bank at 0xf800_0000
 *
 * BR0:
 *    Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001    BR0
 *
 * OR0:
 *    Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
 *    Reserved ORx[17:18] = 00
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65    ORx
 */

#define CONFIG_SYS_BOOT_BLOCK		0xf8000000	/* boot TLB block */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK	/* start of FLASH 128M */

#define CONFIG_SYS_BR0_PRELIM		0xf8001001

#define	CONFIG_SYS_OR0_PRELIM		0xf8000E65

#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	512000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	8000	/* Flash Write Timeout (ms) */


#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER    1
#define CONFIG_SYS_FLASH_CFI           1
#define CONFIG_SYS_FLASH_EMPTY_INFO

/*
 * Flash on the LocalBus
 */
#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */

/* Memory */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */

#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#ifdef CONFIG_PCI2
#define CONFIG_SYS_PCI2_MEM_BUS		0xC0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS	0xe2800000
#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
#endif

#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
#endif


#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC2"
#define CONFIG_TSEC4	1
#define CONFIG_TSEC4_NAME	"eTSEC3"
#undef CONFIG_MPC85XX_FEC

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC3_PHY_ADDR		2
#define TSEC4_PHY_ADDR		3

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC3_PHYIDX		0
#define TSEC4_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define TSEC3_FLAGS		TSEC_GIGABIT
#define TSEC4_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME		"eTSEC2"
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR	 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR	 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR	 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR	 00:E0:0C:00:03:FD
#endif

#define CONFIG_IPADDR	 10.101.43.142

#define CONFIG_HOSTNAME	 atum
#define CONFIG_ROOTPATH	 /nfsroot
#define CONFIG_BOOTFILE	 /tftpboot/uImage.atum
#define CONFIG_UBOOTPATH	/tftpboot/uboot.bin	/* TFTP server */

#define CONFIG_SERVERIP	 10.101.43.10
#define CONFIG_GATEWAYIP 10.101.45.1
#define CONFIG_NETMASK	 255.255.248.0

#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/

#define CONFIG_BAUDRATE	115200

#define CONFIG_NFSBOOTCOMMAND						\
   "setenv bootargs root=/dev/nfs rw "					\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"	                \
   "tftp $loadaddr $bootfile;"						\
   "tftp $dtbaddr $dtbfile;"						\
   "bootm $loadaddr - $dtbaddr"


#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "					\
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $ramdiskaddr $ramdiskfile;"					\
   "tftp $loadaddr $bootfile;"						\
   "tftp $dtbaddr $dtbfile;"						\
   "bootm $loadaddr $ramdiskaddr $dtbaddr"

#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
7bd6104b	1	/*
	2	* Copyright 2007
	3	* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
	4	*
	5	* Copyright 2004, 2007 Freescale Semiconductor.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* atum8548 board configuration file
	28	*
	29	* Please refer to doc/README.atum8548 for more info.
	30	*
	31	*/
	32	#ifndef __CONFIG_H
	33	#define __CONFIG_H
	34
	35	/* Debug Options, Disable in production
	36	#define ET_DEBUG 1
	37	#define CONFIG_PANIC_HANG 1
	38	#define DEBUG 1
	39	*/
	40
	41	/* CPLD Configuration Options */
	42	#define MPC85xx_ATUM_CLKOCR 0x80000002
	43
	44	/* High Level Configuration Options */
	45	#define CONFIG_BOOKE 1 /* BOOKE */
	46	#define CONFIG_E500 1 /* BOOKE e500 family */
	47	#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
	48	#define CONFIG_MPC8548 1 /* MPC8548 specific */
	49
2ae18241 WD	50	#ifndef CONFIG_SYS_TEXT_BASE
	51	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	52	#endif
	53
7bd6104b	54	#define CONFIG_PCI 1 /* enable any pci type devices */
	55	#define CONFIG_PCI1 1 /* PCI controller 1 */
	56	#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
	57	#define CONFIG_PCI2 1 /* PCI controller 2 */
	58	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
	59
	60	#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
	61	#define CONFIG_ENV_OVERWRITE
7bd6104b	62
7bd6104b	63	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
7bd6104b	64
4d3521cc KG	65	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
4d3521cc KG	66
7bd6104b	67	#define CONFIG_SYS_CLK_FREQ 33000000
	68
	69	/*
	70	* These can be toggled for performance analysis, otherwise use default.
	71	*/
	72	#define CONFIG_L2_CACHE /* toggle L2 cache */
	73	#define CONFIG_BTB /* toggle branch predition */
7bd6104b	74
	75	/*
	76	* Only possible on E500 Version 2 or newer cores.
	77	*/
	78	#define CONFIG_ENABLE_36BIT_PHYS 1
	79
	80	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	81
53677ef1	82	#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
7bd6104b	83	#define CONFIG_ENABLE_36BIT_PHYS 1
6d0f6bcf JCPV	84	#undef CONFIG_SYS_DRAM_TEST
	85	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
	86	#define CONFIG_SYS_MEMTEST_END 0x00400000
7bd6104b	87
	88	/*
	89	* Base addresses -- Note these are effective addresses where the
	90	* actual resources get mapped (not physical addresses)
	91	*/
6d0f6bcf JCPV	92	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	93	#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
	94	#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
	95	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
7bd6104b	96
7bd6104b	97	#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
7bd6104b	98
a947e4c7 KG	99	/* DDR Setup */
	100	#define CONFIG_FSL_DDR2
	101	#undef CONFIG_FSL_DDR_INTERACTIVE
	102	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	103	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	104	#define CONFIG_DDR_SPD
7bd6104b	105
a947e4c7 KG	106	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	107	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	108
6d0f6bcf JCPV	109	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	110	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
a947e4c7 KG	111	#define CONFIG_VERY_BIG_RAM
	112
	113	#define CONFIG_NUM_DDR_CONTROLLERS 1
	114	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	115	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	116
	117	/* I2C addresses of SPD EEPROMs */
	118	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	119
	120	/* Manually set up DDR parameters */
6d0f6bcf JCPV	121	#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
	122	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
	123	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
	124	#define CONFIG_SYS_DDR_TIMING_0 0x00260802
	125	#define CONFIG_SYS_DDR_TIMING_1 0x38355322
	126	#define CONFIG_SYS_DDR_TIMING_2 0x039048c7
	127	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	128	#define CONFIG_SYS_DDR_MODE 0x00000432
	129	#define CONFIG_SYS_DDR_INTERVAL 0x05150100
a947e4c7	130	#define DDR_SDRAM_CFG 0x43000000
7bd6104b	131
	132	#undef CONFIG_CLOCKS_IN_MHZ
	133
	134	/*
	135	* Local Bus Definitions
	136	*/
	137
	138	/*
	139	* FLASH on the Local Bus
	140	* based on flash chip S29GL01GP
	141	* One bank, 128M, using the CFI driver.
	142	* Boot from BR0 bank at 0xf800_0000
	143	*
	144	* BR0:
	145	* Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
	146	* Port Size = 16 bits = BRx[19:20] = 10
	147	* Use GPCM = BRx[24:26] = 000
	148	* Valid = BRx[31] = 1
	149	*
	150	* 0 4 8 12 16 20 24 28
	151	* 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
	152	*
	153	* OR0:
	154	* Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
	155	* Reserved ORx[17:18] = 00
	156	* CSNT = ORx[20] = 1
	157	* ACS = half cycle delay = ORx[21:22] = 11
	158	* SCY = 6 = ORx[24:27] = 0110
	159	* TRLX = use relaxed timing = ORx[29] = 1
	160	* EAD = use external address latch delay = OR[31] = 1
	161	*
	162	* 0 4 8 12 16 20 24 28
	163	* 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
	164	*/
	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
6d0f6bcf JCPV	167	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
7bd6104b	168
6d0f6bcf	169	#define CONFIG_SYS_BR0_PRELIM 0xf8001001
7bd6104b	170
6d0f6bcf	171	#define CONFIG_SYS_OR0_PRELIM 0xf8000E65
7bd6104b	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	174	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	175	#undef CONFIG_SYS_FLASH_CHECKSUM
	176	#define CONFIG_SYS_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
	177	#define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
7bd6104b	178
7bd6104b	179
14d0a02a	180	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
7bd6104b	181
00b1883a	182	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	183	#define CONFIG_SYS_FLASH_CFI 1
6d0f6bcf JCPV	184	#define CONFIG_SYS_FLASH_EMPTY_INFO
7bd6104b	185
	186	/*
	187	* Flash on the LocalBus
	188	*/
6d0f6bcf	189	#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
7bd6104b	190
7bd6104b	191	/* Memory */
6d0f6bcf JCPV	192	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	193	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	194	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
7bd6104b	195
6d0f6bcf	196	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
7bd6104b	197
6d0f6bcf	198	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
553f0982	199	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	200	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7bd6104b	201
6d0f6bcf JCPV	202	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	203	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
7bd6104b	204
	205	/* Serial Port */
	206	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	207	#define CONFIG_SYS_NS16550
	208	#define CONFIG_SYS_NS16550_SERIAL
	209	#define CONFIG_SYS_NS16550_REG_SIZE 1
	210	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
7bd6104b	211
6d0f6bcf	212	#define CONFIG_SYS_BAUDRATE_TABLE \
7bd6104b	213	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
7bd6104b	214
6d0f6bcf JCPV	215	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	216	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
7bd6104b	217
7bd6104b	218	/* Use the HUSH parser */
6d0f6bcf JCPV	219	#define CONFIG_SYS_HUSH_PARSER
	220	#ifdef CONFIG_SYS_HUSH_PARSER
	221	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
7bd6104b	222	#endif
	223
	224	/* pass open firmware flat tree */
	225	#define CONFIG_OF_LIBFDT 1
	226	#define CONFIG_OF_BOARD_SETUP 1
	227
	228	/*
	229	* I2C
	230	*/
	231	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	232	#define CONFIG_HARD_I2C /* I2C with hardware support*/
	233	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	234	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	235	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	236	#define CONFIG_SYS_I2C_SLAVE 0x7F
	237	#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	238	#define CONFIG_SYS_I2C_OFFSET 0x3000
7bd6104b	239
	240	/*
	241	* General PCI
	242	* Memory space is mapped 1-1, but I/O space must start from 0.
	243	*/
6d0f6bcf	244	#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
7bd6104b	245
feadd5d5 KG	246	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
feadd5d5 KG	247	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
6d0f6bcf	248	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
feadd5d5	249	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	250	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	251	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
7bd6104b	252
7bd6104b	253	#ifdef CONFIG_PCI2
feadd5d5 KG	254	#define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000
feadd5d5 KG	255	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
6d0f6bcf	256	#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
feadd5d5	257	#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
6d0f6bcf JCPV	258	#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
6d0f6bcf JCPV	259	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
7bd6104b	260	#endif
	261
	262	#ifdef CONFIG_PCIE1
feadd5d5 KG	263	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
feadd5d5 KG	264	#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
6d0f6bcf	265	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
feadd5d5	266	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
6d0f6bcf JCPV	267	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
6d0f6bcf JCPV	268	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
7bd6104b	269	#endif
	270
	271
	272	#if !defined(CONFIG_PCI_PNP)
	273	#define PCI_ENET0_IOADDR 0xe0000000
	274	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	275	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
7bd6104b	276	#endif
	277
	278	#if defined(CONFIG_PCI)
	279
	280	#define CONFIG_NET_MULTI
	281	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	282
	283	#undef CONFIG_EEPRO100
	284	#undef CONFIG_TULIP
	285
	286	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	287
7bd6104b	288	#endif /* CONFIG_PCI */
	289
	290	#if defined(CONFIG_TSEC_ENET)
	291
	292	#ifndef CONFIG_NET_MULTI
	293	#define CONFIG_NET_MULTI 1
	294	#endif
	295
	296	#define CONFIG_MII 1 /* MII PHY management */
	297	#define CONFIG_TSEC1 1
	298	#define CONFIG_TSEC1_NAME "eTSEC0"
	299	#define CONFIG_TSEC2 1
	300	#define CONFIG_TSEC2_NAME "eTSEC1"
	301	#define CONFIG_TSEC3 1
	302	#define CONFIG_TSEC3_NAME "eTSEC2"
	303	#define CONFIG_TSEC4 1
	304	#define CONFIG_TSEC4_NAME "eTSEC3"
	305	#undef CONFIG_MPC85XX_FEC
	306
	307	#define TSEC1_PHY_ADDR 0
	308	#define TSEC2_PHY_ADDR 1
	309	#define TSEC3_PHY_ADDR 2
	310	#define TSEC4_PHY_ADDR 3
	311
	312	#define TSEC1_PHYIDX 0
	313	#define TSEC2_PHYIDX 0
	314	#define TSEC3_PHYIDX 0
	315	#define TSEC4_PHYIDX 0
	316	#define TSEC1_FLAGS TSEC_GIGABIT
	317	#define TSEC2_FLAGS TSEC_GIGABIT
	318	#define TSEC3_FLAGS TSEC_GIGABIT
	319	#define TSEC4_FLAGS TSEC_GIGABIT
	320
	321	/* Options are: eTSEC[0-3] */
	322	#define CONFIG_ETHPRIME "eTSEC2"
	323	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	324	#endif /* CONFIG_TSEC_ENET */
	325
	326	/*
	327	* Environment
	328	*/
5a1aceb0	329	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	330	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	331	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	332	#define CONFIG_ENV_SIZE 0x2000
7bd6104b	333
7bd6104b	334	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	335	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
7bd6104b	336
	337	/*
	338	* BOOTP options
	339	*/
	340	#define CONFIG_BOOTP_BOOTFILESIZE
	341	#define CONFIG_BOOTP_BOOTPATH
	342	#define CONFIG_BOOTP_GATEWAY
	343	#define CONFIG_BOOTP_HOSTNAME
	344
	345
	346	/*
	347	* Command line configuration.
	348	*/
	349	#include <config_cmd_default.h>
	350
	351	#define CONFIG_CMD_PING
	352	#define CONFIG_CMD_I2C
	353	#define CONFIG_CMD_MII
	354
	355	#if defined(CONFIG_PCI)
	356	#define CONFIG_CMD_PCI
	357	#endif
	358
	359
	360	#undef CONFIG_WATCHDOG /* watchdog disabled */
	361
	362	/*
	363	* Miscellaneous configurable options
	364	*/
6d0f6bcf JCPV	365	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	366	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	367	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
7bd6104b	368	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	369	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7bd6104b	370	#else
6d0f6bcf	371	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7bd6104b	372	#endif
6d0f6bcf JCPV	373	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	374	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	375	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	376	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
7bd6104b	377
	378	/*
	379	* For booting Linux, the board info and command line data
	380	* have to be in the first 8 MB of memory, since this is
	381	* the maximum mapped by the Linux kernel during initialization.
	382	*/
6d0f6bcf	383	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
7bd6104b	384
7bd6104b	385	#if defined(CONFIG_CMD_KGDB)
	386	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	387	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	388	#endif
	389
	390	/*
	391	* Environment Configuration
	392	*/
	393
	394	/* The mac addresses for all ethernet interface */
	395	#if defined(CONFIG_TSEC_ENET)
	396	#define CONFIG_HAS_ETH0
	397	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	398	#define CONFIG_HAS_ETH1
	399	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
	400	#define CONFIG_HAS_ETH2
	401	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
	402	#define CONFIG_HAS_ETH3
	403	#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
	404	#endif
	405
	406	#define CONFIG_IPADDR 10.101.43.142
	407
	408	#define CONFIG_HOSTNAME atum
	409	#define CONFIG_ROOTPATH /nfsroot
	410	#define CONFIG_BOOTFILE /tftpboot/uImage.atum
	411	#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
	412
	413	#define CONFIG_SERVERIP 10.101.43.10
	414	#define CONFIG_GATEWAYIP 10.101.45.1
	415	#define CONFIG_NETMASK 255.255.248.0
	416
	417	#define CONFIG_LOADADDR 1000000 /default location for tftp and bootm/
	418
	419	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	420	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
	421
	422	#define CONFIG_BAUDRATE 115200
	423
	424	#define CONFIG_NFSBOOTCOMMAND \
	425	"setenv bootargs root=/dev/nfs rw " \
	426	"nfsroot=$serverip:$rootpath " \
	427	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	428	"console=$consoledev,$baudrate $othbootargs;" \
	429	"tftp $loadaddr $bootfile;" \
	430	"tftp $dtbaddr $dtbfile;" \
	431	"bootm $loadaddr - $dtbaddr"
	432
	433
	434	#define CONFIG_RAMBOOTCOMMAND \
	435	"setenv bootargs root=/dev/ram rw " \
	436	"console=$consoledev,$baudrate $othbootargs;" \
	437	"tftp $ramdiskaddr $ramdiskfile;" \
	438	"tftp $loadaddr $bootfile;" \
	439	"tftp $dtbaddr $dtbfile;" \
	440	"bootm $loadaddr $ramdiskaddr $dtbaddr"
	441
	442	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	443
	444	#endif /* __CONFIG_H */