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6ca24c64 | 1 | /* |
2 | * -- Version 1.1 -- | |
3 | * | |
4 | * (C) Copyright 2003-2005 | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * | |
7 | * (C) Copyright 2004-2005 | |
8 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
9 | * | |
10 | * (C) Copyright 2005 | |
11 | * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de. | |
12 | * | |
13 | * History: | |
14 | * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK | |
15 | * | |
16 | * See file CREDITS for list of people who contributed to this | |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
38 | /* | |
39 | * High Level Configuration Options | |
40 | */ | |
41 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
42 | #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ | |
43 | #define CONFIG_TQM5200 1 /* ... on a TQM5200 module */ | |
44 | ||
610cf367 WD |
45 | #define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */ |
46 | #define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */ | |
47 | #define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */ | |
6ca24c64 | 48 | #define CONFIG_BC3450_USB 1 /* + USB support */ |
49 | # define CONFIG_FAT 1 /* + FAT support */ | |
50 | # define CONFIG_EXT2 1 /* + EXT2 support */ | |
51 | #undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */ | |
52 | #undef CONFIG_BC3450_CAN /* + CAN transceiver */ | |
53 | #undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */ | |
610cf367 WD |
54 | #undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */ |
55 | #undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */ | |
6ca24c64 | 56 | #define CONFIG_BC3450_FP 1 /* + enable FP O/P */ |
57 | #undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */ | |
58 | ||
2ae18241 WD |
59 | /* |
60 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
61 | * 0xFC000000 boot low (standard configuration with room for | |
62 | * max 64 MByte Flash ROM) | |
63 | * 0x00100000 boot from RAM (for testing only) | |
64 | */ | |
65 | #ifndef CONFIG_SYS_TEXT_BASE | |
66 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
67 | #endif | |
68 | ||
6d0f6bcf | 69 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
6ca24c64 | 70 | |
31d82672 BB |
71 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
72 | ||
6ca24c64 | 73 | /* |
74 | * Serial console configuration | |
75 | */ | |
76 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
77 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 78 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
6ca24c64 | 79 | |
80 | /* | |
81 | * AT-PS/2 Multiplexer | |
82 | */ | |
83 | #ifdef CONFIG_BC3450_PS2 | |
84 | # define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ | |
85 | # define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
86 | # define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ | |
6d0f6bcf | 87 | # define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ |
6ca24c64 | 88 | # define CONFIG_BOARD_EARLY_INIT_R |
89 | #endif /* CONFIG_BC3450_PS2 */ | |
90 | ||
91 | /* | |
92 | * PCI Mapping: | |
93 | * 0x40000000 - 0x4fffffff - PCI Memory | |
94 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
95 | */ | |
96 | # define CONFIG_PCI 1 | |
97 | # define CONFIG_PCI_PNP 1 | |
610cf367 | 98 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ |
f33fca22 | 99 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
6ca24c64 | 100 | |
101 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
102 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
103 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
104 | ||
105 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
106 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
107 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
108 | ||
6ca24c64 | 109 | /*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */ |
6d0f6bcf | 110 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
6ca24c64 | 111 | #define CONFIG_NS8382X 1 |
112 | ||
6ca24c64 | 113 | /* |
114 | * Video console | |
115 | */ | |
116 | # define CONFIG_VIDEO | |
117 | # define CONFIG_VIDEO_SM501 | |
118 | # define CONFIG_VIDEO_SM501_32BPP | |
119 | # define CONFIG_CFB_CONSOLE | |
120 | # define CONFIG_VIDEO_LOGO | |
121 | # define CONFIG_VGA_AS_SINGLE_DEVICE | |
122 | # define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */ | |
123 | # define CONFIG_VIDEO_SW_CURSOR | |
124 | # define CONFIG_SPLASH_SCREEN | |
6d0f6bcf | 125 | # define CONFIG_SYS_CONSOLE_IS_IN_ENV |
6ca24c64 | 126 | |
610cf367 WD |
127 | /* |
128 | * Partitions | |
6ca24c64 | 129 | */ |
130 | #define CONFIG_MAC_PARTITION | |
131 | #define CONFIG_DOS_PARTITION | |
132 | #define CONFIG_ISO_PARTITION | |
133 | ||
610cf367 WD |
134 | /* |
135 | * USB | |
6ca24c64 | 136 | */ |
137 | #ifdef CONFIG_BC3450_USB | |
138 | # define CONFIG_USB_OHCI | |
6ca24c64 | 139 | # define CONFIG_USB_STORAGE |
6ca24c64 | 140 | #endif /* CONFIG_BC3450_USB */ |
141 | ||
610cf367 WD |
142 | /* |
143 | * POST support | |
6ca24c64 | 144 | */ |
6d0f6bcf JCPV |
145 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
146 | CONFIG_SYS_POST_CPU | \ | |
147 | CONFIG_SYS_POST_I2C) | |
6ca24c64 | 148 | |
149 | #ifdef CONFIG_POST | |
6ca24c64 | 150 | /* preserve space for the post_word at end of on-chip SRAM */ |
151 | # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
6ca24c64 | 152 | #endif /* CONFIG_POST */ |
153 | ||
de8b2a6e | 154 | |
11799434 JL |
155 | /* |
156 | * BOOTP options | |
157 | */ | |
158 | #define CONFIG_BOOTP_BOOTFILESIZE | |
159 | #define CONFIG_BOOTP_BOOTPATH | |
160 | #define CONFIG_BOOTP_GATEWAY | |
161 | #define CONFIG_BOOTP_HOSTNAME | |
162 | ||
163 | ||
610cf367 | 164 | /* |
de8b2a6e | 165 | * Command line configuration. |
6ca24c64 | 166 | */ |
de8b2a6e JL |
167 | #include <config_cmd_default.h> |
168 | ||
169 | #define CONFIG_CMD_ASKENV | |
170 | #define CONFIG_CMD_DATE | |
171 | #define CONFIG_CMD_DHCP | |
172 | #define CONFIG_CMD_ECHO | |
173 | #define CONFIG_CMD_EEPROM | |
174 | #define CONFIG_CMD_I2C | |
175 | #define CONFIG_CMD_JFFS2 | |
176 | #define CONFIG_CMD_MII | |
177 | #define CONFIG_CMD_NFS | |
178 | #define CONFIG_CMD_PING | |
de8b2a6e JL |
179 | #define CONFIG_CMD_REGINFO |
180 | #define CONFIG_CMD_SNTP | |
181 | #define CONFIG_CMD_BSP | |
182 | ||
183 | #ifdef CONFIG_VIDEO | |
184 | #define CONFIG_CMD_BMP | |
185 | #endif | |
186 | ||
6ca24c64 | 187 | #ifdef CONFIG_BC3450_IDE |
de8b2a6e JL |
188 | #define CONFIG_CMD_IDE |
189 | #endif | |
6ca24c64 | 190 | |
de8b2a6e JL |
191 | #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB) |
192 | #ifdef CONFIG_FAT | |
193 | #define CONFIG_CMD_FAT | |
194 | #endif | |
6ca24c64 | 195 | |
de8b2a6e JL |
196 | #ifdef CONFIG_EXT2 |
197 | #define CONFIG_CMD_EXT2 | |
198 | #endif | |
199 | #endif | |
200 | ||
201 | #ifdef CONFIG_BC3450_USB | |
202 | #define CONFIG_CMD_USB | |
203 | #endif | |
5728be38 | 204 | |
de8b2a6e JL |
205 | #ifdef CONFIG_PCI |
206 | #define CONFIG_CMD_PCI | |
207 | #endif | |
6ca24c64 | 208 | |
af075ee9 JL |
209 | #ifdef CONFIG_POST |
210 | #define CONFIG_CMD_DIAG | |
211 | #endif | |
212 | ||
6ca24c64 | 213 | |
610cf367 | 214 | #define CONFIG_TIMESTAMP /* display image timestamps */ |
6ca24c64 | 215 | |
14d0a02a | 216 | #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ |
6d0f6bcf | 217 | # define CONFIG_SYS_LOWBOOT 1 |
6ca24c64 | 218 | #endif |
219 | ||
220 | /* | |
221 | * Autobooting | |
222 | */ | |
223 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
224 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
225 | ||
226 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 227 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
6ca24c64 | 228 | "echo;" |
229 | ||
230 | #undef CONFIG_BOOTARGS | |
231 | ||
232 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
233 | "netdev=eth0\0" \ | |
234 | "ipaddr=192.168.1.10\0" \ | |
235 | "serverip=192.168.1.3\0" \ | |
236 | "netmask=255.255.255.0\0" \ | |
610cf367 | 237 | "hostname=bc3450\0" \ |
6ca24c64 | 238 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
610cf367 WD |
239 | "kernel_addr=fc0a0000\0" \ |
240 | "ramdisk_addr=fc1c0000\0" \ | |
6ca24c64 | 241 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
242 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
243 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
610cf367 | 244 | "ideargs=setenv bootargs root=/dev/hda2 ro\0" \ |
6ca24c64 | 245 | "addip=setenv bootargs $(bootargs) " \ |
246 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
247 | ":$(hostname):$(netdev):off panic=1\0" \ | |
248 | "addcons=setenv bootargs $(bootargs) " \ | |
249 | "console=ttyS0,$(baudrate) console=tty0\0" \ | |
250 | "flash_self=run ramargs addip addcons;" \ | |
251 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
252 | "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \ | |
253 | "net_nfs=tftp 200000 $(bootfile); " \ | |
254 | "run nfsargs addip addcons; bootm\0" \ | |
610cf367 WD |
255 | "ide_nfs=run nfsargs addip addcons; " \ |
256 | "disk 200000 0:1; bootm\0" \ | |
257 | "ide_ide=run ideargs addip addcons; " \ | |
258 | "disk 200000 0:1; bootm\0" \ | |
6ca24c64 | 259 | "usb_self=run usbload; run ramargs addip addcons; " \ |
260 | "bootm 200000 400000\0" \ | |
261 | "usbload=usb reset; usb scan; usbboot 200000 0:1; " \ | |
262 | "usbboot 400000 0:2\0" \ | |
263 | "bootfile=uImage\0" \ | |
264 | "load=tftp 200000 $(u-boot)\0" \ | |
265 | "u-boot=u-boot.bin\0" \ | |
266 | "update=protect off FC000000 FC05FFFF;" \ | |
267 | "erase FC000000 FC05FFFF;" \ | |
268 | "cp.b 200000 FC000000 $(filesize);" \ | |
269 | "protect on FC000000 FC05FFFF\0" \ | |
270 | "" | |
271 | ||
272 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
273 | ||
274 | /* | |
275 | * IPB Bus clocking configuration. | |
276 | */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
6ca24c64 | 278 | |
279 | /* | |
280 | * PCI Bus clocking configuration | |
281 | * | |
282 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 283 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock |
c99512d6 | 284 | * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
6ca24c64 | 285 | */ |
6d0f6bcf JCPV |
286 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) |
287 | # define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ | |
6ca24c64 | 288 | #endif |
289 | ||
290 | /* | |
291 | * I2C configuration | |
292 | */ | |
293 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 294 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ |
6ca24c64 | 295 | |
296 | /* | |
297 | * I2C clock frequency | |
298 | * | |
299 | * Please notice, that the resulting clock frequency could differ from the | |
300 | * configured value. This is because the I2C clock is derived from system | |
301 | * clock over a frequency divider with only a few divider values. U-boot | |
6d0f6bcf | 302 | * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated |
6ca24c64 | 303 | * approximation allways lies below the configured value, never above. |
304 | */ | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
306 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
6ca24c64 | 307 | |
308 | /* | |
610cf367 | 309 | * EEPROM configuration for I²C EEPROM M24C32 |
6ca24c64 | 310 | * M24C64 should work also. For other EEPROMs config should be verified. |
610cf367 | 311 | * |
6ca24c64 | 312 | * The TQM5200 module may hold an EEPROM at address 0x50. |
313 | */ | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */ |
315 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
316 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
317 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
6ca24c64 | 318 | |
319 | /* | |
320 | * RTC configuration | |
321 | */ | |
322 | #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231) | |
323 | # define CONFIG_RTC_M41T11 1 | |
6d0f6bcf | 324 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
6ca24c64 | 325 | #else |
326 | # define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */ | |
327 | # define CONFIG_BOARD_EARLY_INIT_R | |
328 | #endif | |
329 | ||
330 | /* | |
331 | * Flash configuration | |
332 | */ | |
14d0a02a | 333 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ |
6ca24c64 | 334 | |
335 | /* use CFI flash driver if no module variant is spezified */ | |
6d0f6bcf | 336 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 337 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
339 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
340 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
341 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
342 | #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
343 | ||
344 | #if !defined(CONFIG_SYS_LOWBOOT) | |
345 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) | |
346 | #else /* CONFIG_SYS_LOWBOOT */ | |
347 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) | |
348 | #endif /* CONFIG_SYS_LOWBOOT */ | |
349 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
6ca24c64 | 350 | (= chip selects) */ |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
352 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
6ca24c64 | 353 | |
354 | /* Dynamic MTD partition support */ | |
68d7d651 | 355 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
356 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
357 | #define CONFIG_FLASH_CFI_MTD | |
6ca24c64 | 358 | #define MTDIDS_DEFAULT "nor0=TQM5200-0" |
359 | #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ | |
360 | "1408k(kernel)," \ | |
361 | "2m(initrd)," \ | |
362 | "4m(small-fs)," \ | |
363 | "16m(big-fs)," \ | |
364 | "8m(misc)" | |
365 | ||
366 | /* | |
367 | * Environment settings | |
368 | */ | |
5a1aceb0 | 369 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
370 | #define CONFIG_ENV_SIZE 0x10000 |
371 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
372 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
373 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
6ca24c64 | 374 | |
375 | /* | |
376 | * Memory map | |
377 | */ | |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_MBAR 0xF0000000 |
379 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
380 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
6ca24c64 | 381 | |
382 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 383 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
6ca24c64 | 384 | #ifdef CONFIG_POST |
385 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 386 | # define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
6ca24c64 | 387 | #else |
553f0982 | 388 | # define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
6ca24c64 | 389 | #endif /*CONFIG_POST*/ |
390 | ||
25ddd1fb | 391 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 392 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6ca24c64 | 393 | |
14d0a02a | 394 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
395 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
396 | # define CONFIG_SYS_RAMBOOT 1 | |
6ca24c64 | 397 | #endif |
398 | ||
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
400 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
401 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
6ca24c64 | 402 | |
403 | /* | |
404 | * Ethernet configuration | |
405 | * | |
86321fc1 | 406 | * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT |
6ca24c64 | 407 | */ |
408 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 BW |
409 | #define CONFIG_MPC5xxx_FEC_MII100 |
410 | #undef CONFIG_MPC5xxx_MII10 | |
6ca24c64 | 411 | #define CONFIG_PHY_ADDR 0x00 |
412 | ||
413 | /* | |
414 | * GPIO configuration on BC3450 | |
415 | * | |
610cf367 WD |
416 | * PSC1: UART1 (Service-UART) [0x xxxxxxx4] |
417 | * PSC2: UART2 [0x xxxxxx4x] | |
418 | * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x] | |
419 | * PSC3: USB2 [0x xxxxx1xx] | |
420 | * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx] | |
421 | * (this has to match | |
422 | * CONFIG_USB_CONFIG which is | |
423 | * used by usb_ohci.c to set | |
424 | * the USB ports) | |
425 | * Eth: 10/100Mbit Ethernet [0x xxx0xxxx] | |
426 | * (this is reset to '5' | |
427 | * in FEC driver: fec.c) | |
428 | * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx] | |
429 | * ATA/CS: ??? [0x x1xxxxxx] | |
430 | * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx] | |
6ca24c64 | 431 | * CS1: Use Pin gpio_wkup_6 as second |
610cf367 | 432 | * SDRAM chip select (mem_cs1) |
6ca24c64 | 433 | * Timer: CAN2 / SPI |
610cf367 | 434 | * I2C: CAN1 / I²C2 [0x bxxxxxxx] |
6ca24c64 | 435 | */ |
436 | #ifdef CONFIG_BC3450_AC97 | |
6d0f6bcf | 437 | # define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124 |
6ca24c64 | 438 | #else /* PSC2=UART2 */ |
6d0f6bcf | 439 | # define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144 |
6ca24c64 | 440 | #endif |
441 | ||
442 | /* | |
443 | * Miscellaneous configurable options | |
444 | */ | |
6d0f6bcf JCPV |
445 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
446 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
de8b2a6e | 447 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 448 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
6ca24c64 | 449 | #else |
6d0f6bcf | 450 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
6ca24c64 | 451 | #endif |
6d0f6bcf JCPV |
452 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
453 | #define CONFIG_SYS_MAXARGS 16 /* max no of command args */ | |
454 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */ | |
6ca24c64 | 455 | |
6d0f6bcf | 456 | #define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */ |
6ca24c64 | 457 | /* more extensive mem test */ |
458 | ||
6d0f6bcf JCPV |
459 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
460 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
6ca24c64 | 461 | |
6d0f6bcf | 462 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
6ca24c64 | 463 | |
6d0f6bcf | 464 | #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ |
6ca24c64 | 465 | |
6d0f6bcf | 466 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
de8b2a6e | 467 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 468 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
de8b2a6e JL |
469 | #endif |
470 | ||
6ca24c64 | 471 | /* |
11799434 | 472 | * Enable loopw command. |
6ca24c64 | 473 | */ |
474 | #define CONFIG_LOOPW | |
475 | ||
476 | /* | |
477 | * Various low-level settings | |
478 | */ | |
fd428c05 DZ |
479 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
480 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
6ca24c64 | 481 | |
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
483 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
484 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
485 | # define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
6ca24c64 | 486 | #else |
6d0f6bcf | 487 | # define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
6ca24c64 | 488 | #endif |
6d0f6bcf JCPV |
489 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
490 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
6ca24c64 | 491 | |
492 | /* automatic configuration of chip selects */ | |
493 | #ifdef CONFIG_TQM5200 | |
494 | # define CONFIG_LAST_STAGE_INIT | |
495 | #endif /* CONFIG_TQM5200 */ | |
496 | ||
497 | /* | |
498 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
499 | * for SDRAM autosizing. | |
500 | */ | |
501 | #ifdef CONFIG_TQM5200 | |
6d0f6bcf JCPV |
502 | # define CONFIG_SYS_CS2_START 0xE5000000 |
503 | # define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ | |
504 | # define CONFIG_SYS_CS2_CFG 0x0004D930 | |
6ca24c64 | 505 | #endif /* CONFIG_TQM5200 */ |
506 | ||
507 | /* | |
508 | * Grafic controller - Do not map below 2 GB in address space, because this | |
509 | * area is used for SDRAM autosizing. | |
510 | */ | |
511 | #ifdef CONFIG_TQM5200 | |
512 | # define SM501_FB_BASE 0xE0000000 | |
6d0f6bcf JCPV |
513 | # define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
514 | # define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
515 | # define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
516 | # define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
6ca24c64 | 517 | #endif /* CONFIG_TQM5200 */ |
518 | ||
6d0f6bcf JCPV |
519 | #define CONFIG_SYS_CS_BURST 0x00000000 |
520 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */ | |
6ca24c64 | 521 | /* flash and SM501 */ |
522 | ||
6d0f6bcf | 523 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
6ca24c64 | 524 | |
525 | /* | |
526 | * USB stuff | |
527 | */ | |
528 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
610cf367 | 529 | #define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */ |
6ca24c64 | 530 | |
531 | /* | |
532 | * IDE/ATA stuff Supports IDE harddisk | |
533 | */ | |
534 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
535 | ||
610cf367 WD |
536 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
537 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
6ca24c64 | 538 | |
610cf367 | 539 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
6ca24c64 | 540 | #define CONFIG_IDE_PREINIT |
541 | ||
6d0f6bcf JCPV |
542 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
543 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
6ca24c64 | 544 | |
6d0f6bcf | 545 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
6ca24c64 | 546 | |
6d0f6bcf | 547 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
6ca24c64 | 548 | |
549 | /* Offset for data I/O */ | |
6d0f6bcf | 550 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
6ca24c64 | 551 | |
552 | /* Offset for normal register accesses */ | |
6d0f6bcf | 553 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
6ca24c64 | 554 | |
555 | /* Offset for alternate registers */ | |
6d0f6bcf | 556 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
6ca24c64 | 557 | |
558 | /* Interval between registers */ | |
6d0f6bcf | 559 | #define CONFIG_SYS_ATA_STRIDE 4 |
6ca24c64 | 560 | |
561 | #endif /* __CONFIG_H */ |