[people/ms/u-boot.git] / include / configs / BC3450.h

/*
 * -- Version 1.1 --
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2005
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * (C) Copyright 2005
 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
 *
 * History:
 *	1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU	    */
#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU)   */
#define CONFIG_TQM5200		1	/* ... on a TQM5200 module	    */

#define CONFIG_BC3450		1	/* ... on a BC3450 mainboard	    */
#define CONFIG_BC3450_PS2	1	/*  + a PS/2 converter onboard	    */
#define CONFIG_BC3450_IDE	1	/*  + IDE drives (Compact Flash)    */
#define CONFIG_BC3450_USB	1	/*  + USB support		    */
# define CONFIG_FAT		1	/*    + FAT support		    */
# define CONFIG_EXT2		1	/*    + EXT2 support		    */
#undef CONFIG_BC3450_BUZZER		/*  + Buzzer onboard		    */
#undef CONFIG_BC3450_CAN		/*  + CAN transceiver		    */
#undef CONFIG_BC3450_DS1340		/*  + a RTC DS1340 onboard	    */
#undef CONFIG_BC3450_DS3231		/*  + a RTC DS3231 onboard	tbd */
#undef CONFIG_BC3450_AC97		/*  + AC97 on PSC2,		tbd */
#define CONFIG_BC3450_FP	1	/*  + enable FP O/P		    */
#undef CONFIG_BC3450_CRT		/*  + enable CRT O/P (Debug only!)  */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFC000000	boot low (standard configuration with room for
 *		max 64 MByte Flash ROM)
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFC000000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */

#define CONFIG_HIGH_BATS	1	/* High BATs supported		    */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps		*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * AT-PS/2 Multiplexer
 */
#ifdef CONFIG_BC3450_PS2
# define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
# define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
# define CONFIG_PS2SERIAL	6		/* .. on PSC6		*/
# define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
# define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_BC3450_PS2 */

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
# define CONFIG_PCI		1
# define CONFIG_PCI_PNP		1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
/*#define CONFIG_EEPRO100	XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1

/*
 * Video console
 */
# define CONFIG_VIDEO
# define CONFIG_VIDEO_SM501
# define CONFIG_VIDEO_SM501_32BPP
# define CONFIG_CFB_CONSOLE
# define CONFIG_VIDEO_LOGO
# define CONFIG_VGA_AS_SINGLE_DEVICE
# define CONFIG_CONSOLE_EXTRA_INFO	/* display Board/Device-Infos */
# define CONFIG_VIDEO_SW_CURSOR
# define CONFIG_SPLASH_SCREEN
# define CONFIG_SYS_CONSOLE_IS_IN_ENV

/*
 * Partitions
 */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * USB
 */
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
# define CONFIG_USB_STORAGE
#endif /* CONFIG_BC3450_USB */

/*
 * POST support
 */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
				 CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_I2C)

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif /* CONFIG_POST */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_BSP

#ifdef CONFIG_VIDEO
    #define CONFIG_CMD_BMP
#endif

#ifdef CONFIG_BC3450_IDE
    #define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
    #ifdef CONFIG_FAT
	#define CONFIG_CMD_FAT
    #endif

    #ifdef CONFIG_EXT2
	#define CONFIG_CMD_EXT2
    #endif
#endif

#ifdef CONFIG_BC3450_USB
    #define CONFIG_CMD_USB
#endif

#ifdef CONFIG_PCI
    #define CONFIG_CMD_PCI
#endif

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif


#define CONFIG_TIMESTAMP		/* display image timestamps */

#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo;"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"ipaddr=192.168.1.10\0"						\
	"serverip=192.168.1.3\0"					\
	"netmask=255.255.255.0\0"					\
	"hostname=bc3450\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"kernel_addr=fc0a0000\0"					\
	"ramdisk_addr=fc1c0000\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ideargs=setenv bootargs root=/dev/hda2 ro\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"addcons=setenv bootargs $(bootargs) "				\
		"console=ttyS0,$(baudrate) console=tty0\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"	\
	"net_nfs=tftp 200000 $(bootfile); "				\
		"run nfsargs addip addcons; bootm\0"			\
	"ide_nfs=run nfsargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"ide_ide=run ideargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"usb_self=run usbload; run ramargs addip addcons; "		\
		"bootm 200000 400000\0"					\
	"usbload=usb reset; usb scan; usbboot 200000 0:1; "		\
		"usbboot 400000 0:2\0"					\
	"bootfile=uImage\0"						\
	"load=tftp 200000 $(u-boot)\0"					\
	"u-boot=u-boot.bin\0"						\
	"update=protect off FC000000 FC05FFFF;"				\
		"erase FC000000 FC05FFFF;"				\
		"cp.b 200000 FC000000 $(filesize);"			\
		"protect on FC000000 FC05FFFF\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for I²C EEPROM M24C32
 * M24C64 should work also. For other EEPROMs config should be verified.
 *
 * The TQM5200 module may hold an EEPROM at address 0x50.
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x (TQM) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
# define CONFIG_RTC_M41T11	1
# define CONFIG_SYS_I2C_RTC_ADDR	0x68
#else
# define CONFIG_RTC_MPC5200	1	/* use MPC5200 internal RTC */
# define CONFIG_BOARD_EARLY_INIT_R
#endif

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver if no module variant is spezified */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */

#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
#endif	/* CONFIG_SYS_LOWBOOT */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
						"1408k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif /*CONFIG_POST*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(384 << 10) /* Reserve 384 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */

/*
 * Ethernet configuration
 *
 * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#undef CONFIG_MPC5xxx_MII10
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration on BC3450
 *
 *  PSC1:   UART1 (Service-UART)	 [0x xxxxxxx4]
 *  PSC2:   UART2			 [0x xxxxxx4x]
 *    or:   AC/97 if CONFIG_BC3450_AC97	 [0x xxxxxx2x]
 *  PSC3:   USB2			 [0x xxxxx1xx]
 *  USB:    UART4(ext.)/UART5(int.)	 [0x xxxx2xxx]
 *	      (this has to match
 *	      CONFIG_USB_CONFIG which is
 *	      used by usb_ohci.c to set
 *	      the USB ports)
 *  Eth:    10/100Mbit Ethernet		 [0x xxx0xxxx]
 *	      (this is reset to '5'
 *	      in FEC driver: fec.c)
 *  PSC6:   UART6 (int. to PS/2 contr.)	 [0x xx5xxxxx]
 *  ATA/CS: ???				 [0x x1xxxxxx]
 *	    FIXME! UM Fig 2-10 suggests	 [0x x0xxxxxx]
 *  CS1:    Use Pin gpio_wkup_6 as second
 *	    SDRAM chip select (mem_cs1)
 *  Timer:  CAN2 / SPI
 *  I2C:    CAN1 / I²C2		  [0x bxxxxxxx]
 */
#ifdef CONFIG_BC3450_AC97
# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502124
#else /* PSC2=UART2 */
# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502144
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
#define CONFIG_SYS_MAXARGS		16		/* max no of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Arg. Buffer Size    */

#define CONFIG_SYS_ALT_MEMTEST				/* Enable an alternative,   */
						/*  more extensive mem test */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	    */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	    */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	    */

#define CONFIG_SYS_HZ			1000		/* dec freq: 1ms ticks	    */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
#endif

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
# define CONFIG_SYS_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
#else
# define CONFIG_SYS_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
#endif
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* automatic configuration of chip selects */
#ifdef CONFIG_TQM5200
# define CONFIG_LAST_STAGE_INIT
#endif /* CONFIG_TQM5200 */

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define CONFIG_SYS_CS2_START		0xE5000000
# define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
# define CONFIG_SYS_CS2_CFG		0x0004D930
#endif /* CONFIG_TQM5200 */

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define SM501_FB_BASE		0xE0000000
# define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
# define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
# define CONFIG_SYS_CS1_CFG		0x8F48FF70
# define SM501_MMIO_BASE	CONFIG_SYS_CS1_START + 0x03E00000
#endif /* CONFIG_TQM5200 */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for	*/
						/*  flash and SM501	*/

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * USB stuff
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00002000	/* we're using Port 2	*/

/*
 * IDE/ATA stuff Supports IDE harddisk
 */
#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	  not supported */
#undef	CONFIG_IDE_LED			/* LED for ide	  not supported */

#define CONFIG_IDE_RESET		/* reset for ide      supported */
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
6ca24c64	1	/*
	2	* -- Version 1.1 --
	3	*
	4	* (C) Copyright 2003-2005
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* (C) Copyright 2004-2005
	8	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	9	*
	10	* (C) Copyright 2005
	11	* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
	12	*
	13	* History:
	14	* 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
	15	*
	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	*/
	34
	35	#ifndef __CONFIG_H
	36	#define __CONFIG_H
	37
	38	/*
	39	* High Level Configuration Options
	40	*/
	41	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	42	#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
	43	#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
	44
610cf367 WD	45	#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
	46	#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
	47	#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
6ca24c64	48	#define CONFIG_BC3450_USB 1 /* + USB support */
	49	# define CONFIG_FAT 1 /* + FAT support */
	50	# define CONFIG_EXT2 1 /* + EXT2 support */
	51	#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
	52	#undef CONFIG_BC3450_CAN /* + CAN transceiver */
	53	#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
610cf367 WD	54	#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
610cf367 WD	55	#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
6ca24c64	56	#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
	57	#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
	58
2ae18241 WD	59	/*
	60	* Valid values for CONFIG_SYS_TEXT_BASE are:
	61	* 0xFC000000 boot low (standard configuration with room for
	62	* max 64 MByte Flash ROM)
	63	* 0x00100000 boot from RAM (for testing only)
	64	*/
	65	#ifndef CONFIG_SYS_TEXT_BASE
	66	#define CONFIG_SYS_TEXT_BASE 0xFC000000
	67	#endif
	68
6d0f6bcf	69	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
6ca24c64	70
31d82672 BB	71	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	72
6ca24c64	73	/*
	74	* Serial console configuration
	75	*/
	76	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	77	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	78	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
6ca24c64	79
	80	/*
	81	* AT-PS/2 Multiplexer
	82	*/
	83	#ifdef CONFIG_BC3450_PS2
	84	# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
	85	# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
	86	# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf	87	# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
6ca24c64	88	# define CONFIG_BOARD_EARLY_INIT_R
	89	#endif /* CONFIG_BC3450_PS2 */
	90
	91	/*
	92	* PCI Mapping:
	93	* 0x40000000 - 0x4fffffff - PCI Memory
	94	* 0x50000000 - 0x50ffffff - PCI IO Space
	95	*/
	96	# define CONFIG_PCI 1
	97	# define CONFIG_PCI_PNP 1
610cf367	98	/* #define CONFIG_PCI_SCAN_SHOW 1 */
f33fca22	99	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
6ca24c64	100
	101	#define CONFIG_PCI_MEM_BUS 0x40000000
	102	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	103	#define CONFIG_PCI_MEM_SIZE 0x10000000
	104
	105	#define CONFIG_PCI_IO_BUS 0x50000000
	106	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	107	#define CONFIG_PCI_IO_SIZE 0x01000000
	108
	109	#define CONFIG_NET_MULTI 1
	110	/#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled /
6d0f6bcf	111	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
6ca24c64	112	#define CONFIG_NS8382X 1
6ca24c64	113
6ca24c64	114	/*
	115	* Video console
	116	*/
	117	# define CONFIG_VIDEO
	118	# define CONFIG_VIDEO_SM501
	119	# define CONFIG_VIDEO_SM501_32BPP
	120	# define CONFIG_CFB_CONSOLE
	121	# define CONFIG_VIDEO_LOGO
	122	# define CONFIG_VGA_AS_SINGLE_DEVICE
	123	# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
	124	# define CONFIG_VIDEO_SW_CURSOR
	125	# define CONFIG_SPLASH_SCREEN
6d0f6bcf	126	# define CONFIG_SYS_CONSOLE_IS_IN_ENV
6ca24c64	127
610cf367 WD	128	/*
610cf367 WD	129	* Partitions
6ca24c64	130	*/
	131	#define CONFIG_MAC_PARTITION
	132	#define CONFIG_DOS_PARTITION
	133	#define CONFIG_ISO_PARTITION
	134
610cf367 WD	135	/*
610cf367 WD	136	* USB
6ca24c64	137	*/
	138	#ifdef CONFIG_BC3450_USB
	139	# define CONFIG_USB_OHCI
6ca24c64	140	# define CONFIG_USB_STORAGE
6ca24c64	141	#endif /* CONFIG_BC3450_USB */
6ca24c64	142
610cf367 WD	143	/*
610cf367 WD	144	* POST support
6ca24c64	145	*/
6d0f6bcf JCPV	146	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	147	CONFIG_SYS_POST_CPU \| \
	148	CONFIG_SYS_POST_I2C)
6ca24c64	149
6ca24c64	150	#ifdef CONFIG_POST
6ca24c64	151	/* preserve space for the post_word at end of on-chip SRAM */
6ca24c64	152	# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
6ca24c64	153	#endif /* CONFIG_POST */
6ca24c64	154
de8b2a6e	155
11799434 JL	156	/*
	157	* BOOTP options
	158	*/
	159	#define CONFIG_BOOTP_BOOTFILESIZE
	160	#define CONFIG_BOOTP_BOOTPATH
	161	#define CONFIG_BOOTP_GATEWAY
	162	#define CONFIG_BOOTP_HOSTNAME
	163
	164
610cf367	165	/*
de8b2a6e	166	* Command line configuration.
6ca24c64	167	*/
de8b2a6e JL	168	#include <config_cmd_default.h>
	169
	170	#define CONFIG_CMD_ASKENV
	171	#define CONFIG_CMD_DATE
	172	#define CONFIG_CMD_DHCP
	173	#define CONFIG_CMD_ECHO
	174	#define CONFIG_CMD_EEPROM
	175	#define CONFIG_CMD_I2C
	176	#define CONFIG_CMD_JFFS2
	177	#define CONFIG_CMD_MII
	178	#define CONFIG_CMD_NFS
	179	#define CONFIG_CMD_PING
de8b2a6e JL	180	#define CONFIG_CMD_REGINFO
	181	#define CONFIG_CMD_SNTP
	182	#define CONFIG_CMD_BSP
	183
	184	#ifdef CONFIG_VIDEO
	185	#define CONFIG_CMD_BMP
	186	#endif
	187
6ca24c64	188	#ifdef CONFIG_BC3450_IDE
de8b2a6e JL	189	#define CONFIG_CMD_IDE
de8b2a6e JL	190	#endif
6ca24c64	191
de8b2a6e JL	192	#if defined(CONFIG_BC3450_IDE) \|\| defined(CONFIG_BC3450_USB)
	193	#ifdef CONFIG_FAT
	194	#define CONFIG_CMD_FAT
	195	#endif
6ca24c64	196
de8b2a6e JL	197	#ifdef CONFIG_EXT2
	198	#define CONFIG_CMD_EXT2
	199	#endif
	200	#endif
	201
	202	#ifdef CONFIG_BC3450_USB
	203	#define CONFIG_CMD_USB
	204	#endif
5728be38	205
de8b2a6e JL	206	#ifdef CONFIG_PCI
	207	#define CONFIG_CMD_PCI
	208	#endif
6ca24c64	209
af075ee9 JL	210	#ifdef CONFIG_POST
	211	#define CONFIG_CMD_DIAG
	212	#endif
	213
6ca24c64	214
610cf367	215	#define CONFIG_TIMESTAMP /* display image timestamps */
6ca24c64	216
14d0a02a	217	#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
6d0f6bcf	218	# define CONFIG_SYS_LOWBOOT 1
6ca24c64	219	#endif
	220
	221	/*
	222	* Autobooting
	223	*/
	224	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	225	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	226
	227	#define CONFIG_PREBOOT "echo;" \
32bf3d14	228	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6ca24c64	229	"echo;"
	230
	231	#undef CONFIG_BOOTARGS
	232
	233	#define CONFIG_EXTRA_ENV_SETTINGS \
	234	"netdev=eth0\0" \
	235	"ipaddr=192.168.1.10\0" \
	236	"serverip=192.168.1.3\0" \
	237	"netmask=255.255.255.0\0" \
610cf367	238	"hostname=bc3450\0" \
6ca24c64	239	"rootpath=/opt/eldk/ppc_6xx\0" \
610cf367 WD	240	"kernel_addr=fc0a0000\0" \
610cf367 WD	241	"ramdisk_addr=fc1c0000\0" \
6ca24c64	242	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	243	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	244	"nfsroot=$(serverip):$(rootpath)\0" \
610cf367	245	"ideargs=setenv bootargs root=/dev/hda2 ro\0" \
6ca24c64	246	"addip=setenv bootargs $(bootargs) " \
	247	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	248	":$(hostname):$(netdev):off panic=1\0" \
	249	"addcons=setenv bootargs $(bootargs) " \
	250	"console=ttyS0,$(baudrate) console=tty0\0" \
	251	"flash_self=run ramargs addip addcons;" \
	252	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	253	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
	254	"net_nfs=tftp 200000 $(bootfile); " \
	255	"run nfsargs addip addcons; bootm\0" \
610cf367 WD	256	"ide_nfs=run nfsargs addip addcons; " \
	257	"disk 200000 0:1; bootm\0" \
	258	"ide_ide=run ideargs addip addcons; " \
	259	"disk 200000 0:1; bootm\0" \
6ca24c64	260	"usb_self=run usbload; run ramargs addip addcons; " \
	261	"bootm 200000 400000\0" \
	262	"usbload=usb reset; usb scan; usbboot 200000 0:1; " \
	263	"usbboot 400000 0:2\0" \
	264	"bootfile=uImage\0" \
	265	"load=tftp 200000 $(u-boot)\0" \
	266	"u-boot=u-boot.bin\0" \
	267	"update=protect off FC000000 FC05FFFF;" \
	268	"erase FC000000 FC05FFFF;" \
	269	"cp.b 200000 FC000000 $(filesize);" \
	270	"protect on FC000000 FC05FFFF\0" \
	271	""
	272
	273	#define CONFIG_BOOTCOMMAND "run flash_self"
	274
	275	/*
	276	* IPB Bus clocking configuration.
	277	*/
6d0f6bcf	278	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6ca24c64	279
	280	/*
	281	* PCI Bus clocking configuration
	282	*
	283	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf	284	* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
c99512d6	285	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
6ca24c64	286	*/
6d0f6bcf JCPV	287	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
6d0f6bcf JCPV	288	# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
6ca24c64	289	#endif
	290
	291	/*
	292	* I2C configuration
	293	*/
	294	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	295	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
6ca24c64	296
	297	/*
	298	* I2C clock frequency
	299	*
	300	* Please notice, that the resulting clock frequency could differ from the
	301	* configured value. This is because the I2C clock is derived from system
	302	* clock over a frequency divider with only a few divider values. U-boot
6d0f6bcf	303	* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
6ca24c64	304	* approximation allways lies below the configured value, never above.
6ca24c64	305	*/
6d0f6bcf JCPV	306	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	307	#define CONFIG_SYS_I2C_SLAVE 0x7F
6ca24c64	308
6ca24c64	309	/*
610cf367	310	* EEPROM configuration for I²C EEPROM M24C32
6ca24c64	311	* M24C64 should work also. For other EEPROMs config should be verified.
610cf367	312	*
6ca24c64	313	* The TQM5200 module may hold an EEPROM at address 0x50.
6ca24c64	314	*/
6d0f6bcf JCPV	315	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
	316	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	317	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	318	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
6ca24c64	319
	320	/*
	321	* RTC configuration
	322	*/
	323	#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
	324	# define CONFIG_RTC_M41T11 1
6d0f6bcf	325	# define CONFIG_SYS_I2C_RTC_ADDR 0x68
6ca24c64	326	#else
	327	# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
	328	# define CONFIG_BOARD_EARLY_INIT_R
	329	#endif
	330
	331	/*
	332	* Flash configuration
	333	*/
14d0a02a	334	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
6ca24c64	335
6ca24c64	336	/* use CFI flash driver if no module variant is spezified */
6d0f6bcf	337	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	338	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	339	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
	340	#define CONFIG_SYS_FLASH_EMPTY_INFO
	341	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
	342	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	343	#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
	344
	345	#if !defined(CONFIG_SYS_LOWBOOT)
	346	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
	347	#else /* CONFIG_SYS_LOWBOOT */
	348	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
	349	#endif /* CONFIG_SYS_LOWBOOT */
	350	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
6ca24c64	351	(= chip selects) */
6d0f6bcf JCPV	352	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	353	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
6ca24c64	354
6ca24c64	355	/* Dynamic MTD partition support */
68d7d651	356	#define CONFIG_CMD_MTDPARTS
942556a9 SR	357	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	358	#define CONFIG_FLASH_CFI_MTD
6ca24c64	359	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
	360	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
	361	"1408k(kernel)," \
	362	"2m(initrd)," \
	363	"4m(small-fs)," \
	364	"16m(big-fs)," \
	365	"8m(misc)"
	366
	367	/*
	368	* Environment settings
	369	*/
5a1aceb0	370	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	371	#define CONFIG_ENV_SIZE 0x10000
	372	#define CONFIG_ENV_SECT_SIZE 0x20000
	373	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	374	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
6ca24c64	375
	376	/*
	377	* Memory map
	378	*/
6d0f6bcf JCPV	379	#define CONFIG_SYS_MBAR 0xF0000000
	380	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	381	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
6ca24c64	382
6ca24c64	383	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	384	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6ca24c64	385	#ifdef CONFIG_POST
6ca24c64	386	/* preserve space for the post_word at end of on-chip SRAM */
553f0982	387	# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
6ca24c64	388	#else
553f0982	389	# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
6ca24c64	390	#endif /CONFIG_POST/
6ca24c64	391
25ddd1fb	392	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	393	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6ca24c64	394
14d0a02a	395	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	396	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	397	# define CONFIG_SYS_RAMBOOT 1
6ca24c64	398	#endif
6ca24c64	399
6d0f6bcf JCPV	400	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	401	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	402	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6ca24c64	403
	404	/*
	405	* Ethernet configuration
	406	*
86321fc1	407	* Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
6ca24c64	408	*/
6ca24c64	409	#define CONFIG_MPC5xxx_FEC 1
86321fc1 BW	410	#define CONFIG_MPC5xxx_FEC_MII100
86321fc1 BW	411	#undef CONFIG_MPC5xxx_MII10
6ca24c64	412	#define CONFIG_PHY_ADDR 0x00
	413
	414	/*
	415	* GPIO configuration on BC3450
	416	*
610cf367 WD	417	* PSC1: UART1 (Service-UART) [0x xxxxxxx4]
	418	* PSC2: UART2 [0x xxxxxx4x]
	419	* or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
	420	* PSC3: USB2 [0x xxxxx1xx]
	421	* USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
	422	* (this has to match
	423	* CONFIG_USB_CONFIG which is
	424	* used by usb_ohci.c to set
	425	* the USB ports)
	426	* Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
	427	* (this is reset to '5'
	428	* in FEC driver: fec.c)
	429	* PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
	430	* ATA/CS: ??? [0x x1xxxxxx]
	431	* FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
6ca24c64	432	* CS1: Use Pin gpio_wkup_6 as second
610cf367	433	* SDRAM chip select (mem_cs1)
6ca24c64	434	* Timer: CAN2 / SPI
610cf367	435	* I2C: CAN1 / I²C2 [0x bxxxxxxx]
6ca24c64	436	*/
6ca24c64	437	#ifdef CONFIG_BC3450_AC97
6d0f6bcf	438	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
6ca24c64	439	#else /* PSC2=UART2 */
6d0f6bcf	440	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
6ca24c64	441	#endif
	442
	443	/*
	444	* Miscellaneous configurable options
	445	*/
6d0f6bcf JCPV	446	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	447	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
de8b2a6e	448	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	449	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6ca24c64	450	#else
6d0f6bcf	451	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6ca24c64	452	#endif
6d0f6bcf JCPV	453	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	454	#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
	455	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
6ca24c64	456
6d0f6bcf	457	#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
6ca24c64	458	/* more extensive mem test */
6ca24c64	459
6d0f6bcf JCPV	460	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	461	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
6ca24c64	462
6d0f6bcf	463	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6ca24c64	464
6d0f6bcf	465	#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
6ca24c64	466
6d0f6bcf	467	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
de8b2a6e	468	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	469	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
de8b2a6e JL	470	#endif
de8b2a6e JL	471
6ca24c64	472	/*
11799434	473	* Enable loopw command.
6ca24c64	474	*/
	475	#define CONFIG_LOOPW
	476
	477	/*
	478	* Various low-level settings
	479	*/
fd428c05 DZ	480	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
fd428c05 DZ	481	#define CONFIG_SYS_HID0_FINAL HID0_ICE
6ca24c64	482
6d0f6bcf JCPV	483	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	484	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	485	#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
	486	# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
6ca24c64	487	#else
6d0f6bcf	488	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
6ca24c64	489	#endif
6d0f6bcf JCPV	490	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	491	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
6ca24c64	492
	493	/* automatic configuration of chip selects */
	494	#ifdef CONFIG_TQM5200
	495	# define CONFIG_LAST_STAGE_INIT
	496	#endif /* CONFIG_TQM5200 */
	497
	498	/*
	499	* SRAM - Do not map below 2 GB in address space, because this area is used
	500	* for SDRAM autosizing.
	501	*/
	502	#ifdef CONFIG_TQM5200
6d0f6bcf JCPV	503	# define CONFIG_SYS_CS2_START 0xE5000000
	504	# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
	505	# define CONFIG_SYS_CS2_CFG 0x0004D930
6ca24c64	506	#endif /* CONFIG_TQM5200 */
	507
	508	/*
	509	* Grafic controller - Do not map below 2 GB in address space, because this
	510	* area is used for SDRAM autosizing.
	511	*/
	512	#ifdef CONFIG_TQM5200
	513	# define SM501_FB_BASE 0xE0000000
6d0f6bcf JCPV	514	# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
	515	# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
	516	# define CONFIG_SYS_CS1_CFG 0x8F48FF70
	517	# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
6ca24c64	518	#endif /* CONFIG_TQM5200 */
6ca24c64	519
6d0f6bcf JCPV	520	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	521	#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
6ca24c64	522	/* flash and SM501 */
6ca24c64	523
6d0f6bcf	524	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
6ca24c64	525
	526	/*
	527	* USB stuff
	528	*/
	529	#define CONFIG_USB_CLOCK 0x0001BBBB
610cf367	530	#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
6ca24c64	531
	532	/*
	533	* IDE/ATA stuff Supports IDE harddisk
	534	*/
	535	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	536
610cf367 WD	537	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
610cf367 WD	538	#undef CONFIG_IDE_LED /* LED for ide not supported */
6ca24c64	539
610cf367	540	#define CONFIG_IDE_RESET /* reset for ide supported */
6ca24c64	541	#define CONFIG_IDE_PREINIT
6ca24c64	542
6d0f6bcf JCPV	543	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	544	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
6ca24c64	545
6d0f6bcf	546	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
6ca24c64	547
6d0f6bcf	548	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
6ca24c64	549
6ca24c64	550	/* Offset for data I/O */
6d0f6bcf	551	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
6ca24c64	552
6ca24c64	553	/* Offset for normal register accesses */
6d0f6bcf	554	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
6ca24c64	555
6ca24c64	556	/* Offset for alternate registers */
6d0f6bcf	557	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
6ca24c64	558
6ca24c64	559	/* Interval between registers */
6d0f6bcf	560	#define CONFIG_SYS_ATA_STRIDE 4
6ca24c64	561
6ca24c64	562	#endif /* __CONFIG_H */