[people/ms/u-boot.git] / include / configs / BC3450.h

/*
 * -- Version 1.1 --
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2005
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * (C) Copyright 2005
 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
 *
 * History:
 *	1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU	    */
#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU)   */
#define CONFIG_TQM5200		1	/* ... on a TQM5200 module	    */

#define CONFIG_BC3450		1	/* ... on a BC3450 mainboard	    */
#define CONFIG_BC3450_PS2	1	/*  + a PS/2 converter onboard	    */
#define CONFIG_BC3450_IDE	1	/*  + IDE drives (Compact Flash)    */
#define CONFIG_BC3450_USB	1	/*  + USB support		    */
# define CONFIG_FAT		1	/*    + FAT support		    */
# define CONFIG_EXT2		1	/*    + EXT2 support		    */
#undef CONFIG_BC3450_BUZZER		/*  + Buzzer onboard		    */
#undef CONFIG_BC3450_CAN		/*  + CAN transceiver		    */
#undef CONFIG_BC3450_DS1340		/*  + a RTC DS1340 onboard	    */
#undef CONFIG_BC3450_DS3231		/*  + a RTC DS3231 onboard	tbd */
#undef CONFIG_BC3450_AC97		/*  + AC97 on PSC2,		tbd */
#define CONFIG_BC3450_FP	1	/*  + enable FP O/P		    */
#undef CONFIG_BC3450_CRT		/*  + enable CRT O/P (Debug only!)  */

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot		    */

#define CONFIG_HIGH_BATS	1	/* High BATs supported		    */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps		*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * AT-PS/2 Multiplexer
 */
#ifdef CONFIG_BC3450_PS2
# define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
# define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
# define CONFIG_PS2SERIAL	6		/* .. on PSC6		*/
# define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
# define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_BC3450_PS2 */

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
# define CONFIG_PCI		1
# define CONFIG_PCI_PNP		1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
/*#define CONFIG_EEPRO100	XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1

/*
 * Video console
 */
# define CONFIG_VIDEO
# define CONFIG_VIDEO_SM501
# define CONFIG_VIDEO_SM501_32BPP
# define CONFIG_CFB_CONSOLE
# define CONFIG_VIDEO_LOGO
# define CONFIG_VGA_AS_SINGLE_DEVICE
# define CONFIG_CONSOLE_EXTRA_INFO	/* display Board/Device-Infos */
# define CONFIG_VIDEO_SW_CURSOR
# define CONFIG_SPLASH_SCREEN
# define CONFIG_SYS_CONSOLE_IS_IN_ENV

/*
 * Partitions
 */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * USB
 */
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
# define CONFIG_USB_STORAGE
#endif /* CONFIG_BC3450_USB */

/*
 * POST support
 */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
				 CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_I2C)

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif /* CONFIG_POST */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_BSP

#ifdef CONFIG_VIDEO
    #define CONFIG_CMD_BMP
#endif

#ifdef CONFIG_BC3450_IDE
    #define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
    #ifdef CONFIG_FAT
	#define CONFIG_CMD_FAT
    #endif

    #ifdef CONFIG_EXT2
	#define CONFIG_CMD_EXT2
    #endif
#endif

#ifdef CONFIG_BC3450_USB
    #define CONFIG_CMD_USB
#endif

#ifdef CONFIG_PCI
    #define CONFIG_CMD_PCI
#endif

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif


#define CONFIG_TIMESTAMP		/* display image timestamps */

#if (TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo;"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"ipaddr=192.168.1.10\0"						\
	"serverip=192.168.1.3\0"					\
	"netmask=255.255.255.0\0"					\
	"hostname=bc3450\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"kernel_addr=fc0a0000\0"					\
	"ramdisk_addr=fc1c0000\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ideargs=setenv bootargs root=/dev/hda2 ro\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"addcons=setenv bootargs $(bootargs) "				\
		"console=ttyS0,$(baudrate) console=tty0\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"	\
	"net_nfs=tftp 200000 $(bootfile); "				\
		"run nfsargs addip addcons; bootm\0"			\
	"ide_nfs=run nfsargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"ide_ide=run ideargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"usb_self=run usbload; run ramargs addip addcons; "		\
		"bootm 200000 400000\0"					\
	"usbload=usb reset; usb scan; usbboot 200000 0:1; "		\
		"usbboot 400000 0:2\0"					\
	"bootfile=uImage\0"						\
	"load=tftp 200000 $(u-boot)\0"					\
	"u-boot=u-boot.bin\0"						\
	"update=protect off FC000000 FC05FFFF;"				\
		"erase FC000000 FC05FFFF;"				\
		"cp.b 200000 FC000000 $(filesize);"			\
		"protect on FC000000 FC05FFFF\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for I²C EEPROM M24C32
 * M24C64 should work also. For other EEPROMs config should be verified.
 *
 * The TQM5200 module may hold an EEPROM at address 0x50.
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x (TQM) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
# define CONFIG_RTC_M41T11	1
# define CONFIG_SYS_I2C_RTC_ADDR	0x68
#else
# define CONFIG_RTC_MPC5200	1	/* use MPC5200 internal RTC */
# define CONFIG_BOARD_EARLY_INIT_R
#endif

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver if no module variant is spezified */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */

#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
#endif	/* CONFIG_SYS_LOWBOOT */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
						"1408k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif /*CONFIG_POST*/

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* Bytes reserved for initial data  */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(384 << 10) /* Reserve 384 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */

/*
 * Ethernet configuration
 *
 * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#undef CONFIG_MPC5xxx_MII10
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration on BC3450
 *
 *  PSC1:   UART1 (Service-UART)	 [0x xxxxxxx4]
 *  PSC2:   UART2			 [0x xxxxxx4x]
 *    or:   AC/97 if CONFIG_BC3450_AC97	 [0x xxxxxx2x]
 *  PSC3:   USB2			 [0x xxxxx1xx]
 *  USB:    UART4(ext.)/UART5(int.)	 [0x xxxx2xxx]
 *	      (this has to match
 *	      CONFIG_USB_CONFIG which is
 *	      used by usb_ohci.c to set
 *	      the USB ports)
 *  Eth:    10/100Mbit Ethernet		 [0x xxx0xxxx]
 *	      (this is reset to '5'
 *	      in FEC driver: fec.c)
 *  PSC6:   UART6 (int. to PS/2 contr.)	 [0x xx5xxxxx]
 *  ATA/CS: ???				 [0x x1xxxxxx]
 *	    FIXME! UM Fig 2-10 suggests	 [0x x0xxxxxx]
 *  CS1:    Use Pin gpio_wkup_6 as second
 *	    SDRAM chip select (mem_cs1)
 *  Timer:  CAN2 / SPI
 *  I2C:    CAN1 / I²C2		  [0x bxxxxxxx]
 */
#ifdef CONFIG_BC3450_AC97
# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502124
#else /* PSC2=UART2 */
# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502144
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
#define CONFIG_SYS_MAXARGS		16		/* max no of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Arg. Buffer Size    */

#define CONFIG_SYS_ALT_MEMTEST				/* Enable an alternative,   */
						/*  more extensive mem test */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	    */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	    */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	    */

#define CONFIG_SYS_HZ			1000		/* dec freq: 1ms ticks	    */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
#endif

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
# define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
# define CONFIG_SYS_HID0_FINAL		HID0_ICE
#else
# define CONFIG_SYS_HID0_INIT		0
# define CONFIG_SYS_HID0_FINAL		0
#endif

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
# define CONFIG_SYS_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
#else
# define CONFIG_SYS_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
#endif
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* automatic configuration of chip selects */
#ifdef CONFIG_TQM5200
# define CONFIG_LAST_STAGE_INIT
#endif /* CONFIG_TQM5200 */

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define CONFIG_SYS_CS2_START		0xE5000000
# define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
# define CONFIG_SYS_CS2_CFG		0x0004D930
#endif /* CONFIG_TQM5200 */

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define SM501_FB_BASE		0xE0000000
# define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
# define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
# define CONFIG_SYS_CS1_CFG		0x8F48FF70
# define SM501_MMIO_BASE	CONFIG_SYS_CS1_START + 0x03E00000
#endif /* CONFIG_TQM5200 */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for	*/
						/*  flash and SM501	*/

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * USB stuff
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00002000	/* we're using Port 2	*/

/*
 * IDE/ATA stuff Supports IDE harddisk
 */
#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	  not supported */
#undef	CONFIG_IDE_LED			/* LED for ide	  not supported */

#define CONFIG_IDE_RESET		/* reset for ide      supported */
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
6ca24c64	1	/*
	2	* -- Version 1.1 --
	3	*
	4	* (C) Copyright 2003-2005
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* (C) Copyright 2004-2005
	8	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	9	*
	10	* (C) Copyright 2005
	11	* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
	12	*
	13	* History:
	14	* 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
	15	*
	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	*/
	34
	35	#ifndef __CONFIG_H
	36	#define __CONFIG_H
	37
	38	/*
	39	* High Level Configuration Options
	40	*/
	41	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	42	#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
	43	#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
	44
610cf367 WD	45	#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
	46	#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
	47	#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
6ca24c64	48	#define CONFIG_BC3450_USB 1 /* + USB support */
	49	# define CONFIG_FAT 1 /* + FAT support */
	50	# define CONFIG_EXT2 1 /* + EXT2 support */
	51	#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
	52	#undef CONFIG_BC3450_CAN /* + CAN transceiver */
	53	#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
610cf367 WD	54	#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
610cf367 WD	55	#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
6ca24c64	56	#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
	57	#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
	58
6d0f6bcf	59	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
6ca24c64	60
	61	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	62	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	63
31d82672 BB	64	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	65
6ca24c64	66	/*
	67	* Serial console configuration
	68	*/
	69	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	70	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	71	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
6ca24c64	72
	73	/*
	74	* AT-PS/2 Multiplexer
	75	*/
	76	#ifdef CONFIG_BC3450_PS2
	77	# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
	78	# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
	79	# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf	80	# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
6ca24c64	81	# define CONFIG_BOARD_EARLY_INIT_R
	82	#endif /* CONFIG_BC3450_PS2 */
	83
	84	/*
	85	* PCI Mapping:
	86	* 0x40000000 - 0x4fffffff - PCI Memory
	87	* 0x50000000 - 0x50ffffff - PCI IO Space
	88	*/
	89	# define CONFIG_PCI 1
	90	# define CONFIG_PCI_PNP 1
610cf367	91	/* #define CONFIG_PCI_SCAN_SHOW 1 */
f33fca22	92	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
6ca24c64	93
	94	#define CONFIG_PCI_MEM_BUS 0x40000000
	95	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	96	#define CONFIG_PCI_MEM_SIZE 0x10000000
	97
	98	#define CONFIG_PCI_IO_BUS 0x50000000
	99	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	100	#define CONFIG_PCI_IO_SIZE 0x01000000
	101
	102	#define CONFIG_NET_MULTI 1
	103	/#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled /
6d0f6bcf	104	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
6ca24c64	105	#define CONFIG_NS8382X 1
6ca24c64	106
6ca24c64	107	/*
	108	* Video console
	109	*/
	110	# define CONFIG_VIDEO
	111	# define CONFIG_VIDEO_SM501
	112	# define CONFIG_VIDEO_SM501_32BPP
	113	# define CONFIG_CFB_CONSOLE
	114	# define CONFIG_VIDEO_LOGO
	115	# define CONFIG_VGA_AS_SINGLE_DEVICE
	116	# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
	117	# define CONFIG_VIDEO_SW_CURSOR
	118	# define CONFIG_SPLASH_SCREEN
6d0f6bcf	119	# define CONFIG_SYS_CONSOLE_IS_IN_ENV
6ca24c64	120
610cf367 WD	121	/*
610cf367 WD	122	* Partitions
6ca24c64	123	*/
	124	#define CONFIG_MAC_PARTITION
	125	#define CONFIG_DOS_PARTITION
	126	#define CONFIG_ISO_PARTITION
	127
610cf367 WD	128	/*
610cf367 WD	129	* USB
6ca24c64	130	*/
	131	#ifdef CONFIG_BC3450_USB
	132	# define CONFIG_USB_OHCI
6ca24c64	133	# define CONFIG_USB_STORAGE
6ca24c64	134	#endif /* CONFIG_BC3450_USB */
6ca24c64	135
610cf367 WD	136	/*
610cf367 WD	137	* POST support
6ca24c64	138	*/
6d0f6bcf JCPV	139	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	140	CONFIG_SYS_POST_CPU \| \
	141	CONFIG_SYS_POST_I2C)
6ca24c64	142
6ca24c64	143	#ifdef CONFIG_POST
6ca24c64	144	/* preserve space for the post_word at end of on-chip SRAM */
6ca24c64	145	# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
6ca24c64	146	#endif /* CONFIG_POST */
6ca24c64	147
de8b2a6e	148
11799434 JL	149	/*
	150	* BOOTP options
	151	*/
	152	#define CONFIG_BOOTP_BOOTFILESIZE
	153	#define CONFIG_BOOTP_BOOTPATH
	154	#define CONFIG_BOOTP_GATEWAY
	155	#define CONFIG_BOOTP_HOSTNAME
	156
	157
610cf367	158	/*
de8b2a6e	159	* Command line configuration.
6ca24c64	160	*/
de8b2a6e JL	161	#include <config_cmd_default.h>
	162
	163	#define CONFIG_CMD_ASKENV
	164	#define CONFIG_CMD_DATE
	165	#define CONFIG_CMD_DHCP
	166	#define CONFIG_CMD_ECHO
	167	#define CONFIG_CMD_EEPROM
	168	#define CONFIG_CMD_I2C
	169	#define CONFIG_CMD_JFFS2
	170	#define CONFIG_CMD_MII
	171	#define CONFIG_CMD_NFS
	172	#define CONFIG_CMD_PING
de8b2a6e JL	173	#define CONFIG_CMD_REGINFO
	174	#define CONFIG_CMD_SNTP
	175	#define CONFIG_CMD_BSP
	176
	177	#ifdef CONFIG_VIDEO
	178	#define CONFIG_CMD_BMP
	179	#endif
	180
6ca24c64	181	#ifdef CONFIG_BC3450_IDE
de8b2a6e JL	182	#define CONFIG_CMD_IDE
de8b2a6e JL	183	#endif
6ca24c64	184
de8b2a6e JL	185	#if defined(CONFIG_BC3450_IDE) \|\| defined(CONFIG_BC3450_USB)
	186	#ifdef CONFIG_FAT
	187	#define CONFIG_CMD_FAT
	188	#endif
6ca24c64	189
de8b2a6e JL	190	#ifdef CONFIG_EXT2
	191	#define CONFIG_CMD_EXT2
	192	#endif
	193	#endif
	194
	195	#ifdef CONFIG_BC3450_USB
	196	#define CONFIG_CMD_USB
	197	#endif
5728be38	198
de8b2a6e JL	199	#ifdef CONFIG_PCI
	200	#define CONFIG_CMD_PCI
	201	#endif
6ca24c64	202
af075ee9 JL	203	#ifdef CONFIG_POST
	204	#define CONFIG_CMD_DIAG
	205	#endif
	206
6ca24c64	207
610cf367	208	#define CONFIG_TIMESTAMP /* display image timestamps */
6ca24c64	209
6ca24c64	210	#if (TEXT_BASE == 0xFC000000) /* Boot low */
6d0f6bcf	211	# define CONFIG_SYS_LOWBOOT 1
6ca24c64	212	#endif
	213
	214	/*
	215	* Autobooting
	216	*/
	217	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	218	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	219
	220	#define CONFIG_PREBOOT "echo;" \
32bf3d14	221	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6ca24c64	222	"echo;"
	223
	224	#undef CONFIG_BOOTARGS
	225
	226	#define CONFIG_EXTRA_ENV_SETTINGS \
	227	"netdev=eth0\0" \
	228	"ipaddr=192.168.1.10\0" \
	229	"serverip=192.168.1.3\0" \
	230	"netmask=255.255.255.0\0" \
610cf367	231	"hostname=bc3450\0" \
6ca24c64	232	"rootpath=/opt/eldk/ppc_6xx\0" \
610cf367 WD	233	"kernel_addr=fc0a0000\0" \
610cf367 WD	234	"ramdisk_addr=fc1c0000\0" \
6ca24c64	235	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	236	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	237	"nfsroot=$(serverip):$(rootpath)\0" \
610cf367	238	"ideargs=setenv bootargs root=/dev/hda2 ro\0" \
6ca24c64	239	"addip=setenv bootargs $(bootargs) " \
	240	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	241	":$(hostname):$(netdev):off panic=1\0" \
	242	"addcons=setenv bootargs $(bootargs) " \
	243	"console=ttyS0,$(baudrate) console=tty0\0" \
	244	"flash_self=run ramargs addip addcons;" \
	245	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	246	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
	247	"net_nfs=tftp 200000 $(bootfile); " \
	248	"run nfsargs addip addcons; bootm\0" \
610cf367 WD	249	"ide_nfs=run nfsargs addip addcons; " \
	250	"disk 200000 0:1; bootm\0" \
	251	"ide_ide=run ideargs addip addcons; " \
	252	"disk 200000 0:1; bootm\0" \
6ca24c64	253	"usb_self=run usbload; run ramargs addip addcons; " \
	254	"bootm 200000 400000\0" \
	255	"usbload=usb reset; usb scan; usbboot 200000 0:1; " \
	256	"usbboot 400000 0:2\0" \
	257	"bootfile=uImage\0" \
	258	"load=tftp 200000 $(u-boot)\0" \
	259	"u-boot=u-boot.bin\0" \
	260	"update=protect off FC000000 FC05FFFF;" \
	261	"erase FC000000 FC05FFFF;" \
	262	"cp.b 200000 FC000000 $(filesize);" \
	263	"protect on FC000000 FC05FFFF\0" \
	264	""
	265
	266	#define CONFIG_BOOTCOMMAND "run flash_self"
	267
	268	/*
	269	* IPB Bus clocking configuration.
	270	*/
6d0f6bcf	271	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6ca24c64	272
	273	/*
	274	* PCI Bus clocking configuration
	275	*
	276	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf	277	* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
c99512d6	278	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
6ca24c64	279	*/
6d0f6bcf JCPV	280	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
6d0f6bcf JCPV	281	# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
6ca24c64	282	#endif
	283
	284	/*
	285	* I2C configuration
	286	*/
	287	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	288	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
6ca24c64	289
	290	/*
	291	* I2C clock frequency
	292	*
	293	* Please notice, that the resulting clock frequency could differ from the
	294	* configured value. This is because the I2C clock is derived from system
	295	* clock over a frequency divider with only a few divider values. U-boot
6d0f6bcf	296	* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
6ca24c64	297	* approximation allways lies below the configured value, never above.
6ca24c64	298	*/
6d0f6bcf JCPV	299	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	300	#define CONFIG_SYS_I2C_SLAVE 0x7F
6ca24c64	301
6ca24c64	302	/*
610cf367	303	* EEPROM configuration for I²C EEPROM M24C32
6ca24c64	304	* M24C64 should work also. For other EEPROMs config should be verified.
610cf367	305	*
6ca24c64	306	* The TQM5200 module may hold an EEPROM at address 0x50.
6ca24c64	307	*/
6d0f6bcf JCPV	308	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
	309	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	310	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	311	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
6ca24c64	312
	313	/*
	314	* RTC configuration
	315	*/
	316	#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
	317	# define CONFIG_RTC_M41T11 1
6d0f6bcf	318	# define CONFIG_SYS_I2C_RTC_ADDR 0x68
6ca24c64	319	#else
	320	# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
	321	# define CONFIG_BOARD_EARLY_INIT_R
	322	#endif
	323
	324	/*
	325	* Flash configuration
	326	*/
6d0f6bcf	327	#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
6ca24c64	328
6ca24c64	329	/* use CFI flash driver if no module variant is spezified */
6d0f6bcf	330	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	331	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	332	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
	333	#define CONFIG_SYS_FLASH_EMPTY_INFO
	334	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
	335	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	336	#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
	337
	338	#if !defined(CONFIG_SYS_LOWBOOT)
	339	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
	340	#else /* CONFIG_SYS_LOWBOOT */
	341	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
	342	#endif /* CONFIG_SYS_LOWBOOT */
	343	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
6ca24c64	344	(= chip selects) */
6d0f6bcf JCPV	345	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	346	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
6ca24c64	347
6ca24c64	348	/* Dynamic MTD partition support */
68d7d651	349	#define CONFIG_CMD_MTDPARTS
6ca24c64	350	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
	351	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
	352	"1408k(kernel)," \
	353	"2m(initrd)," \
	354	"4m(small-fs)," \
	355	"16m(big-fs)," \
	356	"8m(misc)"
	357
	358	/*
	359	* Environment settings
	360	*/
5a1aceb0	361	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	362	#define CONFIG_ENV_SIZE 0x10000
	363	#define CONFIG_ENV_SECT_SIZE 0x20000
	364	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	365	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
6ca24c64	366
	367	/*
	368	* Memory map
	369	*/
6d0f6bcf JCPV	370	#define CONFIG_SYS_MBAR 0xF0000000
	371	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	372	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
6ca24c64	373
6ca24c64	374	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	375	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6ca24c64	376	#ifdef CONFIG_POST
6ca24c64	377	/* preserve space for the post_word at end of on-chip SRAM */
6d0f6bcf	378	# define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
6ca24c64	379	#else
6d0f6bcf	380	# define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
6ca24c64	381	#endif /CONFIG_POST/
6ca24c64	382
6d0f6bcf JCPV	383	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
	384	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	385	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6ca24c64	386
6d0f6bcf JCPV	387	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	388	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	389	# define CONFIG_SYS_RAMBOOT 1
6ca24c64	390	#endif
6ca24c64	391
6d0f6bcf JCPV	392	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	393	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	394	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6ca24c64	395
	396	/*
	397	* Ethernet configuration
	398	*
86321fc1	399	* Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
6ca24c64	400	*/
6ca24c64	401	#define CONFIG_MPC5xxx_FEC 1
86321fc1 BW	402	#define CONFIG_MPC5xxx_FEC_MII100
86321fc1 BW	403	#undef CONFIG_MPC5xxx_MII10
6ca24c64	404	#define CONFIG_PHY_ADDR 0x00
	405
	406	/*
	407	* GPIO configuration on BC3450
	408	*
610cf367 WD	409	* PSC1: UART1 (Service-UART) [0x xxxxxxx4]
	410	* PSC2: UART2 [0x xxxxxx4x]
	411	* or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
	412	* PSC3: USB2 [0x xxxxx1xx]
	413	* USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
	414	* (this has to match
	415	* CONFIG_USB_CONFIG which is
	416	* used by usb_ohci.c to set
	417	* the USB ports)
	418	* Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
	419	* (this is reset to '5'
	420	* in FEC driver: fec.c)
	421	* PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
	422	* ATA/CS: ??? [0x x1xxxxxx]
	423	* FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
6ca24c64	424	* CS1: Use Pin gpio_wkup_6 as second
610cf367	425	* SDRAM chip select (mem_cs1)
6ca24c64	426	* Timer: CAN2 / SPI
610cf367	427	* I2C: CAN1 / I²C2 [0x bxxxxxxx]
6ca24c64	428	*/
6ca24c64	429	#ifdef CONFIG_BC3450_AC97
6d0f6bcf	430	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
6ca24c64	431	#else /* PSC2=UART2 */
6d0f6bcf	432	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
6ca24c64	433	#endif
	434
	435	/*
	436	* Miscellaneous configurable options
	437	*/
6d0f6bcf JCPV	438	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	439	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
de8b2a6e	440	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	441	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6ca24c64	442	#else
6d0f6bcf	443	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6ca24c64	444	#endif
6d0f6bcf JCPV	445	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	446	#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
	447	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
6ca24c64	448
6d0f6bcf	449	#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
6ca24c64	450	/* more extensive mem test */
6ca24c64	451
6d0f6bcf JCPV	452	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	453	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
6ca24c64	454
6d0f6bcf	455	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6ca24c64	456
6d0f6bcf	457	#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
6ca24c64	458
6d0f6bcf	459	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
de8b2a6e	460	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	461	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
de8b2a6e JL	462	#endif
de8b2a6e JL	463
6ca24c64	464	/*
11799434	465	* Enable loopw command.
6ca24c64	466	*/
	467	#define CONFIG_LOOPW
	468
	469	/*
	470	* Various low-level settings
	471	*/
	472	#if defined(CONFIG_MPC5200)
6d0f6bcf JCPV	473	# define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	474	# define CONFIG_SYS_HID0_FINAL HID0_ICE
6ca24c64	475	#else
6d0f6bcf JCPV	476	# define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	477	# define CONFIG_SYS_HID0_FINAL 0
6ca24c64	478	#endif
6ca24c64	479
6d0f6bcf JCPV	480	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	481	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	482	#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
	483	# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
6ca24c64	484	#else
6d0f6bcf	485	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
6ca24c64	486	#endif
6d0f6bcf JCPV	487	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	488	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
6ca24c64	489
	490	/* automatic configuration of chip selects */
	491	#ifdef CONFIG_TQM5200
	492	# define CONFIG_LAST_STAGE_INIT
	493	#endif /* CONFIG_TQM5200 */
	494
	495	/*
	496	* SRAM - Do not map below 2 GB in address space, because this area is used
	497	* for SDRAM autosizing.
	498	*/
	499	#ifdef CONFIG_TQM5200
6d0f6bcf JCPV	500	# define CONFIG_SYS_CS2_START 0xE5000000
	501	# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
	502	# define CONFIG_SYS_CS2_CFG 0x0004D930
6ca24c64	503	#endif /* CONFIG_TQM5200 */
	504
	505	/*
	506	* Grafic controller - Do not map below 2 GB in address space, because this
	507	* area is used for SDRAM autosizing.
	508	*/
	509	#ifdef CONFIG_TQM5200
	510	# define SM501_FB_BASE 0xE0000000
6d0f6bcf JCPV	511	# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
	512	# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
	513	# define CONFIG_SYS_CS1_CFG 0x8F48FF70
	514	# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
6ca24c64	515	#endif /* CONFIG_TQM5200 */
6ca24c64	516
6d0f6bcf JCPV	517	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	518	#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
6ca24c64	519	/* flash and SM501 */
6ca24c64	520
6d0f6bcf	521	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
6ca24c64	522
	523	/*
	524	* USB stuff
	525	*/
	526	#define CONFIG_USB_CLOCK 0x0001BBBB
610cf367	527	#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
6ca24c64	528
	529	/*
	530	* IDE/ATA stuff Supports IDE harddisk
	531	*/
	532	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	533
610cf367 WD	534	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
610cf367 WD	535	#undef CONFIG_IDE_LED /* LED for ide not supported */
6ca24c64	536
610cf367	537	#define CONFIG_IDE_RESET /* reset for ide supported */
6ca24c64	538	#define CONFIG_IDE_PREINIT
6ca24c64	539
6d0f6bcf JCPV	540	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	541	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
6ca24c64	542
6d0f6bcf	543	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
6ca24c64	544
6d0f6bcf	545	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
6ca24c64	546
6ca24c64	547	/* Offset for data I/O */
6d0f6bcf	548	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
6ca24c64	549
6ca24c64	550	/* Offset for normal register accesses */
6d0f6bcf	551	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
6ca24c64	552
6ca24c64	553	/* Offset for alternate registers */
6d0f6bcf	554	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
6ca24c64	555
6ca24c64	556	/* Interval between registers */
6d0f6bcf	557	#define CONFIG_SYS_ATA_STRIDE 4
6ca24c64	558
6ca24c64	559	#endif /* __CONFIG_H */