projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 41d91011 PK |
1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 41d91011 PK |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * BSC9132 QDS board configuration file | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 4aafbb44 | 14 | #define CONFIG_SYS_GENERIC_BOARD |
| 15 | #define CONFIG_DISPLAY_BOARDINFO | |
| 16 | ||
| 41d91011 PK |
17 | #ifdef CONFIG_BSC9132QDS |
| 18 | #define CONFIG_BSC9132 | |
| 19 | #endif | |
| 20 | ||
| 21 | #define CONFIG_MISC_INIT_R | |
| 22 | ||
| 23 | #ifdef CONFIG_SDCARD | |
| 24 | #define CONFIG_RAMBOOT_SDCARD | |
| 25 | #define CONFIG_SYS_RAMBOOT | |
| 26 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 27 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| e222b1f3 | 28 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| 41d91011 PK |
29 | #endif |
| 30 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 | |
| 31 | #ifdef CONFIG_SPIFLASH | |
| 32 | #define CONFIG_RAMBOOT_SPIFLASH | |
| 33 | #define CONFIG_SYS_RAMBOOT | |
| 34 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 35 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| e222b1f3 | 36 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| 41d91011 | 37 | #endif |
| bea3cbb0 AB |
38 | #ifdef CONFIG_NAND_SECBOOT |
| 39 | #define CONFIG_RAMBOOT_NAND | |
| 40 | #define CONFIG_SYS_RAMBOOT | |
| 41 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 42 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| 43 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc | |
| 44 | #endif | |
| 41d91011 | 45 | |
| 83e0c2bb | 46 | #ifdef CONFIG_NAND |
| 83e0c2bb PK |
47 | #define CONFIG_SPL_INIT_MINIMAL |
| 48 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 49 | #define CONFIG_SPL_NAND_SUPPORT | |
| fbe76ae4 | 50 | #define CONFIG_SPL_NAND_BOOT |
| 83e0c2bb PK |
51 | #define CONFIG_SPL_FLUSH_IMAGE |
| 52 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 53 | ||
| 54 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
| 55 | #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 | |
| 56 | #define CONFIG_SPL_MAX_SIZE 8192 | |
| 57 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 | |
| 58 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
| e222b1f3 | 59 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
| 83e0c2bb PK |
60 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
| 61 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| 62 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 | |
| 63 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
| 64 | #endif | |
| 65 | ||
| 41d91011 | 66 | #ifndef CONFIG_SYS_TEXT_BASE |
| e222b1f3 | 67 | #define CONFIG_SYS_TEXT_BASE 0x8ff40000 |
| 41d91011 PK |
68 | #endif |
| 69 | ||
| 70 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
| 71 | #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc | |
| 72 | #endif | |
| 73 | ||
| 83e0c2bb PK |
74 | #ifdef CONFIG_SPL_BUILD |
| 75 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 76 | #else | |
| 77 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 41d91011 PK |
78 | #endif |
| 79 | ||
| 41d91011 PK |
80 | /* High Level Configuration Options */ |
| 81 | #define CONFIG_BOOKE /* BOOKE */ | |
| 82 | #define CONFIG_E500 /* BOOKE e500 family */ | |
| 41d91011 | 83 | #define CONFIG_FSL_IFC /* Enable IFC Support */ |
| 737537ef | 84 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
| 41d91011 PK |
85 | #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ |
| 86 | ||
| 87 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
| 88 | #if defined(CONFIG_PCI) | |
| 89 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
| 90 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 842033e6 | 91 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
| 41d91011 PK |
92 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
| 93 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 94 | ||
| 95 | #define CONFIG_CMD_NET | |
| 96 | #define CONFIG_CMD_PCI | |
| 97 | ||
| 98 | #define CONFIG_E1000 /* E1000 pci Ethernet card*/ | |
| 99 | ||
| 100 | /* | |
| 101 | * PCI Windows | |
| 102 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 103 | */ | |
| 104 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 105 | #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" | |
| 106 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 | |
| 107 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 | |
| 108 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 | |
| 109 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
| 110 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 | |
| 111 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 112 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 113 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 | |
| 114 | ||
| 115 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 116 | ||
| 117 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 118 | #define CONFIG_DOS_PARTITION | |
| 119 | #endif | |
| 120 | ||
| 121 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
| 122 | #define CONFIG_ENV_OVERWRITE | |
| 123 | #define CONFIG_TSEC_ENET /* ethernet */ | |
| 124 | ||
| 125 | #if defined(CONFIG_SYS_CLK_100_DDR_100) | |
| 126 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 127 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
| 128 | #elif defined(CONFIG_SYS_CLK_100_DDR_133) | |
| 129 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 130 | #define CONFIG_DDR_CLK_FREQ 133000000 | |
| 131 | #endif | |
| 132 | ||
| 133 | #define CONFIG_MP | |
| 134 | ||
| 135 | #define CONFIG_HWCONFIG | |
| 136 | /* | |
| 137 | * These can be toggled for performance analysis, otherwise use default. | |
| 138 | */ | |
| 139 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 140 | #define CONFIG_BTB /* enable branch predition */ | |
| 141 | ||
| 142 | #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ | |
| 143 | #define CONFIG_SYS_MEMTEST_END 0x01ffffff | |
| 144 | ||
| 145 | /* DDR Setup */ | |
| 5614e71b | 146 | #define CONFIG_SYS_FSL_DDR3 |
| 41d91011 PK |
147 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 148 | #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ | |
| 149 | #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ | |
| 150 | #define CONFIG_FSL_DDR_INTERACTIVE | |
| 151 | ||
| 152 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 153 | ||
| 154 | #define CONFIG_SYS_SDRAM_SIZE (1024) | |
| 155 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 156 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 157 | ||
| 158 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 159 | ||
| 160 | /* DDR3 Controller Settings */ | |
| 161 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 162 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
| 163 | #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 | |
| 164 | #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 | |
| 165 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 166 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 167 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 168 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 169 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 170 | #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F | |
| 171 | ||
| 172 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
| 173 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 174 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 175 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| 176 | #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 | |
| 177 | #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 | |
| 178 | #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 | |
| 179 | #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 | |
| 180 | ||
| 181 | #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 | |
| 182 | #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 | |
| 183 | #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 | |
| 184 | #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 | |
| 185 | ||
| 186 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 | |
| 187 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 | |
| 188 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 | |
| 189 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF | |
| 190 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
| 191 | #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 | |
| 192 | #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 | |
| 193 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 | |
| 194 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 | |
| 195 | ||
| 196 | #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 | |
| 197 | #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 | |
| 198 | #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 | |
| 199 | #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 | |
| 200 | #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 | |
| 201 | #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 | |
| 202 | #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 | |
| 203 | #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 | |
| 204 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 | |
| 205 | ||
| 206 | /*FIXME: the following params are constant w.r.t diff freq | |
| 207 | combinations. this should be removed later | |
| 208 | */ | |
| 209 | #if CONFIG_DDR_CLK_FREQ == 100000000 | |
| 210 | #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 | |
| 211 | #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 | |
| 212 | #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 | |
| 213 | #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 | |
| 214 | #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 | |
| 215 | #elif CONFIG_DDR_CLK_FREQ == 133000000 | |
| 216 | #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 | |
| 217 | #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 | |
| 218 | #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 | |
| 219 | #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 | |
| 220 | #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 | |
| 221 | #else | |
| 222 | #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 | |
| 223 | #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 | |
| 224 | #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 | |
| 225 | #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 | |
| 226 | #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 | |
| 227 | #endif | |
| 228 | ||
| 229 | ||
| 230 | /* relocated CCSRBAR */ | |
| 231 | #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT | |
| 232 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT | |
| 233 | ||
| 234 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR | |
| 235 | ||
| 64501c66 PJ |
236 | /* DSP CCSRBAR */ |
| 237 | #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT | |
| 238 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT | |
| 239 | ||
| 41d91011 PK |
240 | /* |
| 241 | * IFC Definitions | |
| 242 | */ | |
| 243 | /* NOR Flash on IFC */ | |
| 83e0c2bb PK |
244 | |
| 245 | #ifdef CONFIG_SPL_BUILD | |
| 246 | #define CONFIG_SYS_NO_FLASH | |
| 247 | #endif | |
| 41d91011 PK |
248 | #define CONFIG_SYS_FLASH_BASE 0x88000000 |
| 249 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ | |
| 250 | ||
| 251 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 252 | ||
| 253 | #define CONFIG_SYS_NOR_CSPR 0x88000101 | |
| 254 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 255 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) | |
| 256 | /* NOR Flash Timing Params */ | |
| 257 | ||
| 258 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ | |
| 259 | | FTIM0_NOR_TEADC(0x03) \ | |
| 260 | | FTIM0_NOR_TAVDS(0x00) \ | |
| 261 | | FTIM0_NOR_TEAHC(0x0f)) | |
| 262 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ | |
| 263 | | FTIM1_NOR_TRAD_NOR(0x09) \ | |
| 264 | | FTIM1_NOR_TSEQRAD_NOR(0x09)) | |
| 265 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ | |
| 266 | | FTIM2_NOR_TCH(0x4) \ | |
| 267 | | FTIM2_NOR_TWPH(0x7) \ | |
| 268 | | FTIM2_NOR_TWP(0x1e)) | |
| 269 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 270 | ||
| 271 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 272 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 273 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 274 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 275 | ||
| 276 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 277 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 278 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 279 | ||
| 280 | /* CFI for NOR Flash */ | |
| 281 | #define CONFIG_FLASH_CFI_DRIVER | |
| 282 | #define CONFIG_SYS_FLASH_CFI | |
| 283 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 284 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 285 | ||
| 286 | /* NAND Flash on IFC */ | |
| 287 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 288 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 289 | ||
| 290 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 291 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 292 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 293 | | CSPR_V) | |
| 294 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 295 | ||
| 296 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 297 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 298 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 299 | | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ | |
| 300 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 301 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
| 302 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 303 | ||
| 304 | /* NAND Flash Timing Params */ | |
| 305 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ | |
| 306 | | FTIM0_NAND_TWP(0x05) \ | |
| 307 | | FTIM0_NAND_TWCHT(0x02) \ | |
| 308 | | FTIM0_NAND_TWH(0x04)) | |
| 309 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ | |
| 310 | | FTIM1_NAND_TWBE(0x1e) \ | |
| 311 | | FTIM1_NAND_TRR(0x07) \ | |
| 312 | | FTIM1_NAND_TRP(0x05)) | |
| 313 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ | |
| 314 | | FTIM2_NAND_TREH(0x04) \ | |
| 315 | | FTIM2_NAND_TWHRE(0x11)) | |
| 316 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
| 317 | ||
| 318 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 319 | ||
| 320 | /* NAND */ | |
| 321 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 322 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 41d91011 PK |
323 | #define CONFIG_CMD_NAND |
| 324 | ||
| 325 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 326 | ||
| 83e0c2bb | 327 | #ifndef CONFIG_SPL_BUILD |
| 41d91011 | 328 | #define CONFIG_FSL_QIXIS |
| 83e0c2bb | 329 | #endif |
| 41d91011 PK |
330 | #ifdef CONFIG_FSL_QIXIS |
| 331 | #define CONFIG_SYS_FPGA_BASE 0xffb00000 | |
| 332 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 333 | #define QIXIS_BASE CONFIG_SYS_FPGA_BASE | |
| 334 | #define QIXIS_LBMAP_SWITCH 9 | |
| 335 | #define QIXIS_LBMAP_MASK 0x07 | |
| 336 | #define QIXIS_LBMAP_SHIFT 0 | |
| 337 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 338 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 339 | #define QIXIS_RST_CTL_RESET 0x83 | |
| 340 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 341 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 342 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 343 | ||
| 344 | #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE | |
| 345 | ||
| 346 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ | |
| 347 | | CSPR_PORT_SIZE_8 \ | |
| 348 | | CSPR_MSEL_GPCM \ | |
| 349 | | CSPR_V) | |
| 350 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
| 351 | #define CONFIG_SYS_CSOR2 0x0 | |
| 352 | /* CPLD Timing parameters for IFC CS3 */ | |
| 353 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 354 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 355 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 356 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 357 | FTIM1_GPCM_TRAD(0x1f)) | |
| 358 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 359 | FTIM2_GPCM_TCH(0x8) | \ |
| 41d91011 PK |
360 | FTIM2_GPCM_TWP(0x1f)) |
| 361 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
| 362 | #endif | |
| 363 | ||
| 364 | /* Set up IFC registers for boot location NOR/NAND */ | |
| 3051f3f9 | 365 | #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) |
| 83e0c2bb PK |
366 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 367 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 368 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 369 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 370 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 371 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 372 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 373 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
| 374 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 375 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 376 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 377 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 378 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 379 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 380 | #else | |
| 41d91011 PK |
381 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 382 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 383 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 384 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 385 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 386 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 387 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 388 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 389 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 390 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 391 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 392 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 393 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 394 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 83e0c2bb | 395 | #endif |
| 41d91011 PK |
396 | |
| 397 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ | |
| 398 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 399 | ||
| 400 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 401 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| 402 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
| 403 | ||
| 404 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ | |
| 405 | - GENERATED_GBL_DATA_SIZE) | |
| 406 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 407 | ||
| 9307cbab | 408 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 41d91011 PK |
409 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
| 410 | ||
| 411 | /* Serial Port */ | |
| 412 | #define CONFIG_CONS_INDEX 1 | |
| 413 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 414 | #define CONFIG_SYS_NS16550 | |
| 415 | #define CONFIG_SYS_NS16550_SERIAL | |
| 416 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 417 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 83e0c2bb PK |
418 | #ifdef CONFIG_SPL_BUILD |
| 419 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 420 | #endif | |
| 41d91011 PK |
421 | |
| 422 | #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ | |
| 423 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ | |
| 424 | ||
| 425 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 426 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 427 | ||
| 428 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) | |
| 429 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
| 430 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) | |
| 431 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) | |
| 432 | ||
| 433 | /* Use the HUSH parser */ | |
| 434 | #define CONFIG_SYS_HUSH_PARSER /* hush parser */ | |
| 435 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 436 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 437 | #endif | |
| 438 | ||
| 439 | /* | |
| 440 | * Pass open firmware flat tree | |
| 441 | */ | |
| 442 | #define CONFIG_OF_LIBFDT | |
| 443 | #define CONFIG_OF_BOARD_SETUP | |
| 444 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
| 445 | ||
| 446 | /* new uImage format support */ | |
| 447 | #define CONFIG_FIT | |
| 448 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
| 449 | ||
| 00f792e0 HS |
450 | #define CONFIG_SYS_I2C |
| 451 | #define CONFIG_SYS_I2C_FSL | |
| 452 | #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ | |
| 453 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 454 | #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ | |
| 455 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 456 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 457 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 41d91011 PK |
458 | |
| 459 | /* I2C EEPROM */ | |
| 460 | #define CONFIG_ID_EEPROM | |
| 461 | #ifdef CONFIG_ID_EEPROM | |
| 462 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 463 | #endif | |
| 464 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 465 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 466 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 467 | ||
| 468 | /* enable read and write access to EEPROM */ | |
| 469 | #define CONFIG_CMD_EEPROM | |
| 470 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
| 471 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 472 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 473 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 474 | ||
| 475 | /* I2C FPGA */ | |
| 476 | #define CONFIG_I2C_FPGA | |
| 477 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 478 | ||
| 479 | #define CONFIG_RTC_DS3231 | |
| 480 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 481 | ||
| 482 | /* | |
| 483 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
| 484 | * used for SLIC | |
| 485 | */ | |
| 486 | /* eSPI - Enhanced SPI */ | |
| 487 | #define CONFIG_FSL_ESPI /* SPI */ | |
| 488 | #ifdef CONFIG_FSL_ESPI | |
| 489 | #define CONFIG_SPI_FLASH | |
| 490 | #define CONFIG_SPI_FLASH_SPANSION | |
| 491 | #define CONFIG_CMD_SF | |
| 492 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 493 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 494 | #endif | |
| 495 | ||
| 496 | #if defined(CONFIG_TSEC_ENET) | |
| 497 | ||
| 498 | #define CONFIG_MII /* MII PHY management */ | |
| 499 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 500 | #define CONFIG_TSEC1 1 | |
| 501 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 502 | #define CONFIG_TSEC2 1 | |
| 503 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 504 | ||
| 505 | #define TSEC1_PHY_ADDR 0 | |
| 506 | #define TSEC2_PHY_ADDR 1 | |
| 507 | ||
| 508 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 509 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 510 | ||
| 511 | #define TSEC1_PHYIDX 0 | |
| 512 | #define TSEC2_PHYIDX 0 | |
| 513 | ||
| 514 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 515 | ||
| 516 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
| 517 | ||
| 518 | /* TBI PHY configuration for SGMII mode */ | |
| 519 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
| 520 | TBICR_PHY_RESET \ | |
| 521 | | TBICR_ANEG_ENABLE \ | |
| 522 | | TBICR_FULL_DUPLEX \ | |
| 523 | | TBICR_SPEED1_SET \ | |
| 524 | ) | |
| 525 | ||
| 526 | #endif /* CONFIG_TSEC_ENET */ | |
| 527 | ||
| 528 | #define CONFIG_MMC | |
| 529 | #ifdef CONFIG_MMC | |
| 530 | #define CONFIG_CMD_MMC | |
| 531 | #define CONFIG_DOS_PARTITION | |
| 532 | #define CONFIG_FSL_ESDHC | |
| 533 | #define CONFIG_GENERIC_MMC | |
| 534 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 535 | #endif | |
| 536 | ||
| 537 | #define CONFIG_USB_EHCI /* USB */ | |
| 538 | #ifdef CONFIG_USB_EHCI | |
| 539 | #define CONFIG_CMD_USB | |
| 540 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 541 | #define CONFIG_USB_EHCI_FSL | |
| 542 | #define CONFIG_USB_STORAGE | |
| 543 | #define CONFIG_HAS_FSL_DR_USB | |
| 544 | #endif | |
| 545 | ||
| 546 | /* | |
| 547 | * Environment | |
| 548 | */ | |
| 41d91011 PK |
549 | #if defined(CONFIG_RAMBOOT_SDCARD) |
| 550 | #define CONFIG_ENV_IS_IN_MMC | |
| e222b1f3 | 551 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| 41d91011 PK |
552 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 553 | #define CONFIG_ENV_SIZE 0x2000 | |
| 554 | #elif defined(CONFIG_RAMBOOT_SPIFLASH) | |
| 555 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 556 | #define CONFIG_ENV_SPI_BUS 0 | |
| 557 | #define CONFIG_ENV_SPI_CS 0 | |
| 558 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 559 | #define CONFIG_ENV_SPI_MODE 0 | |
| 560 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 561 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 562 | #define CONFIG_ENV_SIZE 0x2000 | |
| bea3cbb0 | 563 | #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) |
| 83e0c2bb PK |
564 | #define CONFIG_ENV_IS_IN_NAND |
| 565 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| e222b1f3 | 566 | #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) |
| 83e0c2bb PK |
567 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
| 568 | #elif defined(CONFIG_SYS_RAMBOOT) | |
| 41d91011 PK |
569 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
| 570 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 571 | #define CONFIG_ENV_SIZE 0x2000 | |
| 41d91011 PK |
572 | #else |
| 573 | #define CONFIG_ENV_IS_IN_FLASH | |
| 41d91011 | 574 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 41d91011 | 575 | #define CONFIG_ENV_SIZE 0x2000 |
| e222b1f3 | 576 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 41d91011 PK |
577 | #endif |
| 578 | ||
| 579 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 580 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 581 | ||
| 582 | /* | |
| 583 | * Command line configuration. | |
| 584 | */ | |
| 585 | #include <config_cmd_default.h> | |
| 586 | ||
| 587 | #define CONFIG_CMD_DATE | |
| 588 | #define CONFIG_CMD_DHCP | |
| 589 | #define CONFIG_CMD_ELF | |
| 590 | #define CONFIG_CMD_ERRATA | |
| 591 | #define CONFIG_CMD_I2C | |
| 592 | #define CONFIG_CMD_IRQ | |
| 593 | #define CONFIG_CMD_MII | |
| 594 | #define CONFIG_CMD_PING | |
| 595 | #define CONFIG_CMD_SETEXPR | |
| 596 | #define CONFIG_CMD_REGINFO | |
| 597 | ||
| 598 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
| 599 | #define CONFIG_CMD_EXT2 | |
| 600 | #define CONFIG_CMD_FAT | |
| 601 | #define CONFIG_DOS_PARTITION | |
| 602 | #endif | |
| 603 | ||
| 737537ef RG |
604 | /* Hash command with SHA acceleration supported in hardware */ |
| 605 | #ifdef CONFIG_FSL_CAAM | |
| 606 | #define CONFIG_CMD_HASH | |
| 607 | #define CONFIG_SHA_HW_ACCEL | |
| 608 | #endif | |
| 609 | ||
| 41d91011 PK |
610 | /* |
| 611 | * Miscellaneous configurable options | |
| 612 | */ | |
| 613 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 614 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 615 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 616 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 41d91011 PK |
617 | |
| 618 | #if defined(CONFIG_CMD_KGDB) | |
| 619 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 620 | #else | |
| 621 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 622 | #endif | |
| 623 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 624 | /* Print Buffer Size */ | |
| 625 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 626 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
| 41d91011 PK |
627 | |
| 628 | ||
| 629 | /* | |
| 630 | * For booting Linux, the board info and command line data | |
| 631 | * have to be in the first 64 MB of memory, since this is | |
| 632 | * the maximum mapped by the Linux kernel during initialization. | |
| 633 | */ | |
| 634 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
| 635 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 636 | ||
| 637 | #if defined(CONFIG_CMD_KGDB) | |
| 638 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 41d91011 PK |
639 | #endif |
| 640 | ||
| 42a9e2fe AK |
641 | /* |
| 642 | * Dynamic MTD Partition support with mtdparts | |
| 643 | */ | |
| 644 | #ifndef CONFIG_SYS_NO_FLASH | |
| 645 | #define CONFIG_MTD_DEVICE | |
| 646 | #define CONFIG_MTD_PARTITIONS | |
| 647 | #define CONFIG_CMD_MTDPARTS | |
| 648 | #define CONFIG_FLASH_CFI_MTD | |
| 649 | #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," | |
| 650 | #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ | |
| 651 | "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ | |
| 652 | "8m(kernel),512k(dtb),-(fs)" | |
| 653 | #endif | |
| 654 | /* | |
| 655 | * Override partitions in device tree using info | |
| 656 | * in "mtdparts" environment variable | |
| 657 | */ | |
| 658 | #ifdef CONFIG_CMD_MTDPARTS | |
| 659 | #define CONFIG_FDT_FIXUP_PARTITIONS | |
| 660 | #endif | |
| 661 | ||
| 41d91011 PK |
662 | /* |
| 663 | * Environment Configuration | |
| 664 | */ | |
| 665 | ||
| 666 | #if defined(CONFIG_TSEC_ENET) | |
| 667 | #define CONFIG_HAS_ETH0 | |
| 668 | #define CONFIG_HAS_ETH1 | |
| 669 | #endif | |
| 670 | ||
| 671 | #define CONFIG_HOSTNAME BSC9132qds | |
| 672 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 673 | #define CONFIG_BOOTFILE "uImage" | |
| 674 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
| 675 | ||
| 676 | #define CONFIG_BAUDRATE 115200 | |
| 37811ec2 | 677 | #define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ |
| 41d91011 PK |
678 | |
| 679 | #ifdef CONFIG_SDCARD | |
| 680 | #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" | |
| 681 | #else | |
| 682 | #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" | |
| 683 | #endif | |
| 684 | ||
| 685 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 686 | "netdev=eth0\0" \ | |
| 687 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
| 688 | "loadaddr=1000000\0" \ | |
| 689 | "bootfile=uImage\0" \ | |
| 690 | "consoledev=ttyS0\0" \ | |
| 691 | "ramdiskaddr=2000000\0" \ | |
| 692 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 693 | "fdtaddr=c00000\0" \ | |
| 694 | "fdtfile=bsc9132qds.dtb\0" \ | |
| 695 | "bdev=sda1\0" \ | |
| 696 | CONFIG_DEF_HWCONFIG\ | |
| 697 | "othbootargs=mem=880M ramdisk_size=600000 " \ | |
| 698 | "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ | |
| 699 | "isolcpus=0\0" \ | |
| 700 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 701 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 702 | "usb start;" \ | |
| 703 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 704 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 705 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| 706 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 707 | "debug_halt_off=mw ff7e0e30 0xf0000000;" | |
| 708 | ||
| 709 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 710 | "setenv bootargs root=/dev/nfs rw " \ | |
| 711 | "nfsroot=$serverip:$rootpath " \ | |
| 712 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 713 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 714 | "tftp $loadaddr $bootfile;" \ | |
| 715 | "tftp $fdtaddr $fdtfile;" \ | |
| 716 | "bootm $loadaddr - $fdtaddr" | |
| 717 | ||
| 718 | #define CONFIG_HDBOOT \ | |
| 719 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
| 720 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 721 | "usb start;" \ | |
| 722 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
| 723 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
| 724 | "bootm $loadaddr - $fdtaddr" | |
| 725 | ||
| 726 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 727 | "setenv bootargs root=/dev/ram rw " \ | |
| 728 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 729 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 730 | "tftp $loadaddr $bootfile;" \ | |
| 731 | "tftp $fdtaddr $fdtfile;" \ | |
| 732 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 733 | ||
| 734 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 735 | ||
| f978f7c2 AB |
736 | #include <asm/fsl_secure_boot.h> |
| 737 | ||
| 789490b6 RG |
738 | #ifdef CONFIG_SECURE_BOOT |
| 739 | #define CONFIG_CMD_BLOB | |
| 740 | #endif | |
| 741 | ||
| 41d91011 | 742 | #endif /* __CONFIG_H */ |