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a8d9758d MH |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
3aab0cd8 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
a8d9758d MH |
5 | */ |
6 | ||
7 | /* | |
8 | * C29XPCIE board configuration file | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
9a7eeb9c | 14 | #define CONFIG_DISPLAY_BOARDINFO |
a8d9758d MH |
15 | |
16 | #ifdef CONFIG_C29XPCIE | |
17 | #define CONFIG_PPC_C29X | |
18 | #endif | |
19 | ||
20 | #ifdef CONFIG_SPIFLASH | |
21 | #define CONFIG_RAMBOOT_SPIFLASH | |
22 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
e222b1f3 | 23 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
a8d9758d MH |
24 | #endif |
25 | ||
eb6b458c | 26 | #ifdef CONFIG_NAND |
eb6b458c PL |
27 | #ifdef CONFIG_TPL_BUILD |
28 | #define CONFIG_SPL_NAND_BOOT | |
29 | #define CONFIG_SPL_FLUSH_IMAGE | |
eb6b458c | 30 | #define CONFIG_SPL_NAND_INIT |
76f1f388 | 31 | #define CONFIG_TPL_DRIVERS_MISC_SUPPORT |
eb6b458c PL |
32 | #define CONFIG_SPL_COMMON_INIT_DDR |
33 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
34 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
35 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
e222b1f3 | 36 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) |
eb6b458c PL |
37 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
38 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
39 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
40 | #elif defined(CONFIG_SPL_BUILD) | |
41 | #define CONFIG_SPL_INIT_MINIMAL | |
eb6b458c PL |
42 | #define CONFIG_SPL_NAND_MINIMAL |
43 | #define CONFIG_SPL_FLUSH_IMAGE | |
44 | #define CONFIG_SPL_TEXT_BASE 0xff800000 | |
45 | #define CONFIG_SPL_MAX_SIZE 8192 | |
46 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
47 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 | |
48 | #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 | |
49 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
50 | #endif | |
51 | #define CONFIG_SPL_PAD_TO 0x20000 | |
52 | #define CONFIG_TPL_PAD_TO 0x20000 | |
53 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
54 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
55 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
56 | #endif | |
57 | ||
a8d9758d | 58 | #ifndef CONFIG_SYS_TEXT_BASE |
e222b1f3 | 59 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
a8d9758d MH |
60 | #endif |
61 | ||
62 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
63 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
64 | #endif | |
65 | ||
eb6b458c PL |
66 | #ifdef CONFIG_SPL_BUILD |
67 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
68 | #else | |
69 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
70 | #endif | |
71 | ||
72 | #ifdef CONFIG_SPL_BUILD | |
73 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
a8d9758d MH |
74 | #endif |
75 | ||
76 | /* High Level Configuration Options */ | |
77 | #define CONFIG_BOOKE /* BOOKE */ | |
78 | #define CONFIG_E500 /* BOOKE e500 family */ | |
a8d9758d | 79 | #define CONFIG_FSL_IFC /* Enable IFC Support */ |
737537ef | 80 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
a8d9758d MH |
81 | #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ |
82 | ||
83 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
84 | #ifdef CONFIG_PCI | |
b38eaec5 | 85 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
a8d9758d MH |
86 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
87 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
88 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
89 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
90 | ||
a8d9758d MH |
91 | #define CONFIG_CMD_PCI |
92 | ||
a8d9758d MH |
93 | /* |
94 | * PCI Windows | |
95 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
96 | */ | |
97 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
98 | #define CONFIG_SYS_PCIE1_NAME "Slot 1" | |
99 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
100 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
101 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
102 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
103 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
104 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
105 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
106 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
107 | ||
108 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
109 | ||
110 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
111 | #define CONFIG_DOS_PARTITION | |
112 | #endif | |
113 | ||
114 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
115 | #define CONFIG_TSEC_ENET | |
116 | #define CONFIG_ENV_OVERWRITE | |
117 | ||
118 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
119 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
120 | ||
121 | #define CONFIG_HWCONFIG | |
122 | ||
123 | /* | |
124 | * These can be toggled for performance analysis, otherwise use default. | |
125 | */ | |
126 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
127 | #define CONFIG_BTB /* toggle branch predition */ | |
128 | ||
129 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
130 | ||
131 | #define CONFIG_ENABLE_36BIT_PHYS | |
132 | ||
133 | #define CONFIG_ADDR_MAP 1 | |
134 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
135 | ||
136 | #define CONFIG_SYS_MEMTEST_START 0x00200000 | |
137 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
138 | #define CONFIG_PANIC_HANG | |
139 | ||
140 | /* DDR Setup */ | |
5614e71b | 141 | #define CONFIG_SYS_FSL_DDR3 |
a8d9758d MH |
142 | #define CONFIG_DDR_SPD |
143 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
144 | #define SPD_EEPROM_ADDRESS 0x50 | |
145 | #define CONFIG_SYS_DDR_RAW_TIMING | |
146 | ||
147 | /* DDR ECC Setup*/ | |
148 | #define CONFIG_DDR_ECC | |
149 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
150 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
151 | ||
152 | #define CONFIG_SYS_SDRAM_SIZE 512 | |
153 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
154 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
155 | ||
156 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
157 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
158 | ||
159 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
160 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
161 | ||
162 | /* Platform SRAM setting */ | |
163 | #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 | |
164 | #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ | |
165 | (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) | |
166 | #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) | |
167 | ||
eb6b458c PL |
168 | #ifdef CONFIG_SPL_BUILD |
169 | #define CONFIG_SYS_NO_FLASH | |
170 | #endif | |
171 | ||
a8d9758d MH |
172 | /* |
173 | * IFC Definitions | |
174 | */ | |
175 | /* NOR Flash on IFC */ | |
176 | #define CONFIG_SYS_FLASH_BASE 0xec000000 | |
177 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ | |
178 | ||
179 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
180 | ||
181 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } | |
182 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
183 | ||
184 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
185 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
186 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ | |
187 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ | |
188 | ||
189 | /* 16Bit NOR Flash - S29GL512S10TFI01 */ | |
190 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
191 | CSPR_PORT_SIZE_16 | \ | |
192 | CSPR_MSEL_NOR | \ | |
193 | CSPR_V) | |
194 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) | |
195 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) | |
ac2785c6 | 196 | |
a8d9758d MH |
197 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
198 | FTIM0_NOR_TEADC(0x5) | \ | |
199 | FTIM0_NOR_TEAHC(0x5)) | |
ac2785c6 PL |
200 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
201 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
202 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
a8d9758d MH |
203 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
204 | FTIM2_NOR_TCH(0x4) | \ | |
ac2785c6 | 205 | FTIM2_NOR_TWPH(0x0E) | \ |
a8d9758d MH |
206 | FTIM2_NOR_TWP(0x1c)) |
207 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
208 | ||
209 | /* CFI for NOR Flash */ | |
210 | #define CONFIG_FLASH_CFI_DRIVER | |
211 | #define CONFIG_SYS_FLASH_CFI | |
212 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
213 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
214 | ||
215 | /* NAND Flash on IFC */ | |
216 | #define CONFIG_NAND_FSL_IFC | |
217 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
218 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
219 | ||
220 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
221 | ||
222 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
a8d9758d | 223 | #define CONFIG_CMD_NAND |
eb6b458c | 224 | #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) |
a8d9758d MH |
225 | |
226 | /* 8Bit NAND Flash - K9F1G08U0B */ | |
227 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
228 | | CSPR_PORT_SIZE_8 \ | |
229 | | CSPR_MSEL_NAND \ | |
230 | | CSPR_V) | |
231 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
affd520f | 232 | #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ |
a8d9758d MH |
233 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
234 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
235 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
affd520f PK |
236 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ |
237 | | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ | |
238 | | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ | |
239 | | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ | |
a8d9758d MH |
240 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ |
241 | FTIM0_NAND_TWP(0x0c) | \ | |
242 | FTIM0_NAND_TWCHT(0x08) | \ | |
243 | FTIM0_NAND_TWH(0x06)) | |
244 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ | |
245 | FTIM1_NAND_TWBE(0x1d) | \ | |
246 | FTIM1_NAND_TRR(0x08) | \ | |
247 | FTIM1_NAND_TRP(0x0c)) | |
248 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ | |
249 | FTIM2_NAND_TREH(0x0a) | \ | |
250 | FTIM2_NAND_TWHRE(0x18)) | |
251 | #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) | |
252 | ||
253 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
254 | ||
255 | /* Set up IFC registers for boot location NOR/NAND */ | |
eb6b458c PL |
256 | #ifdef CONFIG_NAND |
257 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
258 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
259 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
260 | #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE | |
261 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
262 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
263 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
264 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
265 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
266 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
267 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
268 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
269 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
270 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
271 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
272 | #else | |
a8d9758d MH |
273 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
274 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
275 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
276 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
277 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
278 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
279 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
280 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
281 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
282 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
affd520f | 283 | #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE |
a8d9758d MH |
284 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
285 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
286 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
287 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
eb6b458c | 288 | #endif |
a8d9758d MH |
289 | |
290 | /* CPLD on IFC, selected by CS2 */ | |
291 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
292 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ | |
293 | | CONFIG_SYS_CPLD_BASE) | |
294 | ||
295 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
296 | | CSPR_PORT_SIZE_8 \ | |
297 | | CSPR_MSEL_GPCM \ | |
298 | | CSPR_V) | |
299 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
300 | #define CONFIG_SYS_CSOR2 0x0 | |
301 | /* CPLD Timing parameters for IFC CS2 */ | |
302 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
303 | FTIM0_GPCM_TEADC(0x0e) | \ | |
304 | FTIM0_GPCM_TEAHC(0x0e)) | |
305 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
306 | FTIM1_GPCM_TRAD(0x1f)) | |
307 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 308 | FTIM2_GPCM_TCH(0x8) | \ |
a8d9758d MH |
309 | FTIM2_GPCM_TWP(0x1f)) |
310 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
311 | ||
312 | #if defined(CONFIG_RAMBOOT_SPIFLASH) | |
313 | #define CONFIG_SYS_RAMBOOT | |
314 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
315 | #endif | |
316 | ||
317 | #define CONFIG_BOARD_EARLY_INIT_R | |
318 | ||
319 | #define CONFIG_SYS_INIT_RAM_LOCK | |
320 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 | |
b39d1213 | 321 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
a8d9758d | 322 | |
b39d1213 | 323 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
a8d9758d MH |
324 | - GENERATED_GBL_DATA_SIZE) |
325 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
326 | ||
9307cbab | 327 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
eb6b458c PL |
328 | #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) |
329 | ||
330 | /* | |
331 | * Config the L2 Cache as L2 SRAM | |
332 | */ | |
333 | #if defined(CONFIG_SPL_BUILD) | |
334 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
335 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
336 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
337 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
338 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
339 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
340 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) | |
341 | #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) | |
342 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) | |
343 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) | |
344 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) | |
345 | #elif defined(CONFIG_NAND) | |
346 | #ifdef CONFIG_TPL_BUILD | |
347 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
348 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
349 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
350 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
351 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
352 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
353 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
354 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
355 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
356 | #else | |
357 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
358 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
359 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
360 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
361 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) | |
362 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
363 | #endif | |
364 | #endif | |
365 | #endif | |
a8d9758d MH |
366 | |
367 | /* Serial Port */ | |
368 | #define CONFIG_CONS_INDEX 1 | |
a8d9758d MH |
369 | #define CONFIG_SYS_NS16550_SERIAL |
370 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
371 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
372 | ||
eb6b458c PL |
373 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
374 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
375 | #endif | |
376 | ||
a8d9758d MH |
377 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
378 | ||
379 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
380 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
381 | ||
382 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
383 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
384 | ||
a8d9758d MH |
385 | #define CONFIG_SYS_I2C |
386 | #define CONFIG_SYS_I2C_FSL | |
387 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
388 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
389 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
390 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
391 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
392 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
393 | ||
394 | /* I2C EEPROM */ | |
395 | /* enable read and write access to EEPROM */ | |
396 | #define CONFIG_CMD_EEPROM | |
a8d9758d MH |
397 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
398 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
399 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
400 | ||
a8d9758d | 401 | /* eSPI - Enhanced SPI */ |
a8d9758d MH |
402 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
403 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
404 | ||
405 | #ifdef CONFIG_TSEC_ENET | |
a8d9758d MH |
406 | #define CONFIG_MII /* MII PHY management */ |
407 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
408 | #define CONFIG_TSEC1 1 | |
409 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
410 | #define CONFIG_TSEC2 1 | |
411 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
412 | ||
413 | /* Default mode is RGMII mode */ | |
414 | #define TSEC1_PHY_ADDR 0 | |
415 | #define TSEC2_PHY_ADDR 2 | |
416 | ||
417 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
418 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
419 | ||
420 | #define CONFIG_ETHPRIME "eTSEC1" | |
421 | ||
422 | #define CONFIG_PHY_GIGE | |
423 | #endif /* CONFIG_TSEC_ENET */ | |
424 | ||
425 | /* | |
426 | * Environment | |
427 | */ | |
428 | #if defined(CONFIG_SYS_RAMBOOT) | |
429 | #if defined(CONFIG_RAMBOOT_SPIFLASH) | |
430 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
431 | #define CONFIG_ENV_SPI_BUS 0 | |
432 | #define CONFIG_ENV_SPI_CS 0 | |
433 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
434 | #define CONFIG_ENV_SPI_MODE 0 | |
435 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
436 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
437 | #define CONFIG_ENV_SIZE 0x2000 | |
438 | #endif | |
eb6b458c PL |
439 | #elif defined(CONFIG_NAND) |
440 | #define CONFIG_ENV_IS_IN_NAND | |
441 | #ifdef CONFIG_TPL_BUILD | |
442 | #define CONFIG_ENV_SIZE 0x2000 | |
443 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
444 | #else | |
445 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
446 | #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE | |
447 | #endif | |
448 | #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE | |
a8d9758d MH |
449 | #else |
450 | #define CONFIG_ENV_IS_IN_FLASH | |
a8d9758d | 451 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
a8d9758d MH |
452 | #define CONFIG_ENV_SIZE 0x2000 |
453 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
454 | #endif | |
455 | ||
456 | #define CONFIG_LOADS_ECHO | |
457 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
458 | ||
459 | /* | |
460 | * Command line configuration. | |
461 | */ | |
a8d9758d | 462 | #define CONFIG_CMD_ERRATA |
a8d9758d | 463 | #define CONFIG_CMD_IRQ |
a8d9758d MH |
464 | #define CONFIG_CMD_REGINFO |
465 | ||
737537ef RG |
466 | /* Hash command with SHA acceleration supported in hardware */ |
467 | #ifdef CONFIG_FSL_CAAM | |
468 | #define CONFIG_CMD_HASH | |
469 | #define CONFIG_SHA_HW_ACCEL | |
470 | #endif | |
471 | ||
a8d9758d MH |
472 | /* |
473 | * Miscellaneous configurable options | |
474 | */ | |
475 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
476 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
477 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
478 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
a8d9758d MH |
479 | |
480 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
481 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
482 | /* Print Buffer Size */ | |
483 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
484 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
a8d9758d MH |
485 | |
486 | /* | |
487 | * For booting Linux, the board info and command line data | |
488 | * have to be in the first 64 MB of memory, since this is | |
489 | * the maximum mapped by the Linux kernel during initialization. | |
490 | */ | |
491 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
492 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
493 | ||
494 | /* | |
495 | * Environment Configuration | |
496 | */ | |
497 | ||
498 | #ifdef CONFIG_TSEC_ENET | |
499 | #define CONFIG_HAS_ETH0 | |
500 | #define CONFIG_HAS_ETH1 | |
501 | #endif | |
502 | ||
503 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
504 | #define CONFIG_BOOTFILE "uImage" | |
505 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ | |
506 | ||
507 | /* default location for tftp and bootm */ | |
508 | #define CONFIG_LOADADDR 1000000 | |
509 | ||
a8d9758d MH |
510 | |
511 | #define CONFIG_BAUDRATE 115200 | |
512 | ||
9c25ee6d PL |
513 | #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on |
514 | ||
a8d9758d MH |
515 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
516 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ | |
517 | "netdev=eth0\0" \ | |
518 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
519 | "loadaddr=1000000\0" \ | |
520 | "consoledev=ttyS0\0" \ | |
521 | "ramdiskaddr=2000000\0" \ | |
522 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
b24a4f62 | 523 | "fdtaddr=1e00000\0" \ |
a8d9758d MH |
524 | "fdtfile=name/of/device-tree.dtb\0" \ |
525 | "othbootargs=ramdisk_size=600000\0" \ | |
526 | ||
527 | #define CONFIG_RAMBOOTCOMMAND \ | |
528 | "setenv bootargs root=/dev/ram rw " \ | |
529 | "console=$consoledev,$baudrate $othbootargs; " \ | |
530 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
531 | "tftp $loadaddr $bootfile;" \ | |
532 | "tftp $fdtaddr $fdtfile;" \ | |
533 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
534 | ||
535 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
536 | ||
3ca49c42 PL |
537 | #include <asm/fsl_secure_boot.h> |
538 | ||
a8d9758d | 539 | #endif /* __CONFIG_H */ |