[u-boot.git] / include / configs / CANBT.h

/*
 * (C) Copyright 2001
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_CANBT		1	/* ...on a CANBT board	        */

#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */

#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; "	\
	"bootm ffe00000 ffe80000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#undef  CONFIG_PCI_PNP			/* no pci plug-and-play		*/

#define	CONFIG_PHY_ADDR		0	/* PHY address			*/

#define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|       \
				CFG_CMD_IRQ	|       \
				CFG_CMD_EEPROM      ) & \
			       ~CFG_CMD_NET)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE      \
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFE0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */

#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */

#if 0 /* Use FLASH for environment variables */

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector	*/
#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/

#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/

#else /* Use EEPROM for environment variables */

#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C                 /* I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization                                  */
#define CFG_EBC_PB0AP           0x92015480
#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (CAN/USB) initialization                                       */
#define CFG_EBC_PB1AP           0x010053C0  /* enable Ready, BEM=1              */
#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 2 (Misc-IO/LEDs) initialization                                  */
#define CFG_EBC_PB2AP           0x000004c0  /* no Ready, BEM=1                  */
#define CFG_EBC_PB2CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 3 (CAN Features) initialization                                  */
#define CFG_EBC_PB3AP           0x80000040  /* no Ready, BEM=1                  */
#define CFG_EBC_PB3CR           0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in RAM)
 */
#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM                   */
#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
ab255f26 WD	1	/*
	2	* (C) Copyright 2001
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405CR 1 /* This is a PPC405CR CPU */
	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	38	#define CONFIG_CANBT 1 /* ...on a CANBT board */
	39
	40	#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
	41
	42	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
	43
	44	#define CONFIG_BAUDRATE 115200
	45	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
	46
	47	#undef CONFIG_BOOTARGS
	48	#define CONFIG_BOOTCOMMAND \
	49	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
	50	"bootm ffe00000 ffe80000"
	51
	52	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	53	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	54
	55	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
	56
	57	#define CONFIG_PHY_ADDR 0 /* PHY address */
	58
	59	#define CONFIG_COMMANDS (( CONFIG_CMD_DFL \| \
	60	CFG_CMD_IRQ \| \
	61	CFG_CMD_EEPROM ) & \
8bde7f77	62	~CFG_CMD_NET)
ab255f26 WD	63
	64	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	65	#include <cmd_confdefs.h>
	66
	67	#undef CONFIG_WATCHDOG /* watchdog disabled */
	68
	69	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	70
	71	/*
	72	* Miscellaneous configurable options
	73	*/
	74	#define CFG_LONGHELP /* undef to save memory */
	75	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	76	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	77	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	78	#else
	79	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	80	#endif
	81	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	82	#define CFG_MAXARGS 16 /* max number of command args */
	83	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	84
	85	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
	86
	87	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	88	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	89
	90	#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
	91
	92	/* The following table includes the supported baudrates */
	93	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	94	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	95	57600, 115200, 230400, 460800, 921600 }
ab255f26 WD	96
	97	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	98	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	99
	100	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	101
	102	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	103
	104	/*-----------------------------------------------------------------------
	105	* Start addresses for the final memory configuration
	106	* (Set up by the startup code)
	107	* Please note that CFG_SDRAM_BASE _must_ start at 0
	108	*/
	109	#define CFG_SDRAM_BASE 0x00000000
	110	#define CFG_FLASH_BASE 0xFFFE0000
	111	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	112	#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
	113	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	114
	115	/*
	116	* For booting Linux, the board info and command line data
	117	* have to be in the first 8 MB of memory, since this is
	118	* the maximum mapped by the Linux kernel during initialization.
	119	*/
	120	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	121	/*-----------------------------------------------------------------------
	122	* FLASH organization
	123	*/
	124	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	125	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	126
	127	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	128	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	129
	130	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	131	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	132	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
	133	/*
	134	* The following defines are added for buggy IOP480 byte interface.
	135	* All other boards should use the standard values (CPCI405 etc.)
	136	*/
	137	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	138	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	139	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
	140
	141	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	142
	143	#if 0 /* Use FLASH for environment variables */
	144
	145	#define CFG_ENV_IS_IN_FLASH 1
	146	#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
	147	#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	148
	149	#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
	150
	151	#else /* Use EEPROM for environment variables */
	152
	153	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	154	#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	155	#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
8bde7f77	156	/* total size of a CAT24WC08 is 1024 bytes */
ab255f26 WD	157	#endif
	158
	159	/*-----------------------------------------------------------------------
	160	* I2C EEPROM (CAT24WC08) for environment
	161	*/
	162	#define CONFIG_HARD_I2C /* I2C with hardware support */
	163	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	164	#define CFG_I2C_SLAVE 0x7F
	165
	166	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
	167	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	168	/* mask of address bits that overflow into the "EEPROM chip address" */
	169	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	170
	171	/*-----------------------------------------------------------------------
	172	* Cache Configuration
	173	*/
	174	#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
	175	#define CFG_CACHELINE_SIZE 32 /* ... */
	176	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	177	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	178	#endif
	179
	180	/*
	181	* Init Memory Controller:
	182	*
	183	* BR0/1 and OR0/1 (FLASH)
	184	*/
	185
	186	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	187	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	188
	189	/*-----------------------------------------------------------------------
	190	* External Bus Controller (EBC) Setup
	191	*/
	192
	193	/* Memory Bank 0 (Flash Bank 0) initialization */
	194	#define CFG_EBC_PB0AP 0x92015480
	195	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
	196
	197	/* Memory Bank 1 (CAN/USB) initialization */
	198	#define CFG_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
	199	#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	200
	201	/* Memory Bank 2 (Misc-IO/LEDs) initialization */
	202	#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
	203	#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
	204
	205	/* Memory Bank 3 (CAN Features) initialization */
	206	#define CFG_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
	207	#define CFG_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
	208
	209	/*-----------------------------------------------------------------------
	210	* Definitions for initial stack pointer and data area (in RAM)
	211	*/
	212	#define CFG_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
	213	#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
	214	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	215	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	216	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	217
	218
	219	/*
	220	* Internal Definitions
221	*
222	* Boot Flags
223	*/
224	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
225	#define BOOTFLAG_WARM 0x02 /* Software reboot */
226
227	#endif /* __CONFIG_H */